WO2011007613A1 - 表示装置および表示装置の駆動方法 - Google Patents
表示装置および表示装置の駆動方法 Download PDFInfo
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- WO2011007613A1 WO2011007613A1 PCT/JP2010/058037 JP2010058037W WO2011007613A1 WO 2011007613 A1 WO2011007613 A1 WO 2011007613A1 JP 2010058037 W JP2010058037 W JP 2010058037W WO 2011007613 A1 WO2011007613 A1 WO 2011007613A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0439—Pixel structures
- G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
- G09G2310/0205—Simultaneous scanning of several lines in flat panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0232—Special driving of display border areas
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/06—Colour space transformation
Definitions
- the present invention relates to a display device and a method for driving the display device, and more particularly to a technique for pre-charging the picture elements of the display unit.
- AC driving includes frame inversion driving, line inversion driving, dot inversion driving, and the like, which can be used in combination.
- a plurality of picture elements arranged in a matrix are formed, and gate bus lines for selecting picture elements in units of rows are formed for each row.
- a source bus line for supplying a data signal is formed for each column. While the data signal is output to the source bus line, the gate bus line is scanned to select a picture element, and the data signal is applied to the selected picture element, thereby driving the picture element.
- This pixel driving operation is a common operation performed even when various driving methods are used.
- the positive polarity and the negative polarity of the data signal applied to the picture element are alternately switched using the common potential as a reference of polarity.
- the dot inversion drive makes the data signal applied to the vertical, horizontal, and horizontal adjacent picture elements have opposite polarities, so that the picture element potential is stably input, so that the image quality is improved.
- the dot inversion drive has a problem that the rewriting cycle of the potential of the source bus line is shortened, resulting in insufficient charging of the pixels.
- the source bus line potential rewrite cycle is long.
- Patent Document 1 describes a technique in which dot inversion driving is apparently performed by alternately connecting pixels to source bus lines.
- this technique by adding one source bus line, the pixels in each column are alternately connected to the source bus lines adjacent to the left and right, one row at a time, while each source bus line has a row.
- a data signal is supplied that has the same polarity between adjacent pixels in the direction and a reverse polarity between adjacent pixels in the column direction, and the polarity relationship is inverted for each field.
- the source bus lines can have the same polarity in one field period.
- the picture element does not reach the potential of the applied data signal. This is because there has been a case where one horizontal period has to be shortened with an increase in the number of pixels, etc., so that the drive time for one picture element is shortened, or the source bus line in a large-area liquid crystal panel. This is due to the fact that the resistance and capacity of the capacitor increase. If the potential of the picture element, that is, charging is insufficient, display unevenness and a decrease in contrast occur, leading to a decrease in display quality. Therefore, the pixel is precharged (precharged) before the main charge.
- one pixel is connected to the source bus line adjacent to the left side and one connected to the source bus line adjacent to the right side.
- each pixel when precharging is performed using the data signal of the previous row by extending the output period of the scanning signal, dot-shaped unevenness is observed only on the left and right edges of the display screen. There is a problem that arises.
- the picture elements 101 in each column are adjacent to the source bus on the left side.
- 2 shows a configuration in which one connected to a line and one connected to a source bus line adjacent to the right side are alternately arranged.
- a configuration in which the pixels in each column are connected to the source bus line adjacent to the left side and those connected to the source bus line adjacent to the right side are arranged in a staggered manner. I will call it.
- picture elements 101 are connected to the source bus lines S1 and S2773 located at the left end and the right end every two rows.
- the picture element 101 is not connected to the source bus lines S1 and S2773, as indicated by arrows in FIG.
- the picture elements 101 located at the left and right ends may be charged faster than the other picture elements 101.
- a difference occurs in the ultimate potential charged in the liquid crystal.
- the luminance changes only at the left and right ends of the display screen, and unevenness occurs in a dot shape. This is particularly noticeable in display patterns such as halftone gray solids.
- the non-display area When the liquid crystal panel 100 is of a normally black (NB) display type, the non-display area is normally set to the black voltage that is the lowest gradation voltage, and thus the above unevenness looks a little black compared to others. On the contrary, when the liquid crystal panel 100 is a normally white (NW) display type, the non-display area usually has a white voltage that is the lowest gradation voltage, and thus the unevenness looks a little white compared to the others.
- NB normally black
- NW normally white
- the present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a display screen with a staggered arrangement, while performing pre-charging with the previous output, and a display screen.
- An object of the present invention is to provide a display device and a display device driving method capable of eliminating dot-like unevenness generated at the left and right ends.
- the display device of the present invention is an active matrix type display device, wherein the picture elements in each column of the effective display area are connected to data signal lines adjacent to one side of the picture elements. And those connected to the data signal line adjacent to the other side of the picture element are arranged immediately before the first period which is a horizontal period in which the signal is written at the beginning of the effective display area. From the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area, with a period corresponding to one horizontal period as the 0th period.
- each of the k-th periods (k is an integer from 0 to n) consecutive in the order of k, the potential polarity with the common potential as a reference is not changed in each data signal line, and Reverse polarity from the signal output to the adjacent data signal line
- a pixel having a potential polarity is output line-sequentially, and a pixel that completes writing of a signal in the k-th period in the effective display area is from the period of the (k ⁇ 1) period to the period of the k-th period.
- the display device driving method of the present invention is an active matrix display device driving method in order to solve the above-described problem, and the pixels in each column of the effective display area are on one side of the pixel.
- a horizontal period in which signals connected to adjacent data signal lines and those connected to adjacent data signal lines on the other side of the picture element are arranged and signals are written at the beginning of the effective display area The period having a length corresponding to one horizontal period immediately before the first period is the zeroth period, and the nth period is the horizontal period in which signal writing is completed from the zeroth period to the end of the effective display area.
- the common potential is used as a reference for the polarity of each data signal line.
- Adjacent data signal lines whose potential polarity does not change A signal having a polarity opposite to that of the output signal is output line-sequentially, and a pixel for which the signal is written in the k-th period in the effective display area is displayed during the period of the (k ⁇ 1) period.
- the signal output during the (k ⁇ 1) th period is output to the data signal line not connected to the picture element for which the signal has been written.
- the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture element and to the data signal line adjacent to the other side of the picture element.
- each data signal line has an invariable potential polarity with respect to the common potential as a reference, and adjacent data signal lines Since signals having a potential polarity opposite to that of the output signal are output line-sequentially, it is possible to substantially perform dot inversion driving.
- the picture elements that complete the signal writing in the kth period in the effective display area are (k ⁇ 1). )
- To complete the writing of a signal in the kth period in the effective display region by selecting to be connected to the connected data signal line from the period of the period k) to the period of the kth period. Is precharged by the same polarity signal output during the previous (k ⁇ 1) period, and then fully charged. Therefore, even when the main charging time is short, the potential of the signal to be written can be sufficiently reached.
- the data signal that is not connected to the pixel that completes the signal writing in the kth period is output to the line. Therefore, in the row where the connection of the picture element to the data signal line is switched to the previous line, the data signal line output voltage of the precharge period is changed between the picture element located at the left end or the right end and the other picture elements. The difference is eliminated, and as a result, the difference in potential charged in the liquid crystal can be eliminated.
- the display device of the present invention may have the following configuration.
- the display device of the present invention is an active matrix type display device in which the picture elements in each column of the effective display area are connected to a data signal line adjacent to one side of the picture elements, Are connected to the data signal line adjacent to the other side of the element, and are arranged for one horizontal period immediately before the first period which is the horizontal period in which the signal is written at the beginning of the effective display area.
- a period having a corresponding length is defined as a 0th period, and is continuous in the order of k from the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area.
- each data signal line has an invariable potential polarity with respect to the common potential, and the adjacent data signal lines
- the output signal has a polarity opposite to that of the output signal.
- the pixels are output in a line-sequential manner, and the pixels that complete the signal writing in the k-th period in the effective display area are connected from the period of the (k-1) period to the period of the k-th period.
- a signal line is characterized in that a signal corresponding to gray data is output.
- the display device of the present invention is an active matrix type display device in which the picture element in each column of the effective display area is connected to a data signal line adjacent to one side of the picture element. Are connected to the data signal line adjacent to the other side of the element, and are arranged for one horizontal period immediately before the first period which is the horizontal period in which the signal is written at the beginning of the effective display area.
- a period having a corresponding length is defined as a 0th period, and is continuous in the order of k from the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area.
- each data signal line has an invariable potential polarity with respect to the common potential, and the adjacent data signal lines A signal with a polarity opposite to that of the output signal Pixels that are output line-sequentially and that complete the signal writing in the k-th period in the effective display area are connected data from the period of the (k-1) period to the period of the k-th period.
- Each of the kth periods of 1 ⁇ k ⁇ n ⁇ 1 with respect to the effective display area is selected to be electrically connected to the signal line, and is not connected to a pixel that completes signal writing in the kth period; and A data signal line connected to a picture element for which signal writing is completed in the (k + 1) period is used as a signal to be written to the picture element in which signal writing is completed in the (k + 1) period. Based on this, one of a signal corresponding to the lowest luminance gradation and a signal corresponding to the maximum luminance gradation is output.
- the display device driving method of the present invention may have the following configuration.
- the driving method of the display device of the present invention is a driving method of an active matrix type display device, and the pixels in each column of the effective display area are connected to the data signal line adjacent to one side of the pixels. And those connected to the data signal line adjacent to the other side of the picture element are arranged immediately before the first period which is a horizontal period in which the signal is written at the beginning of the effective display area. From the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area, with a period corresponding to one horizontal period as the 0th period.
- the pixel is selected so as to be electrically connected to the data signal line connected to the middle, and in each of the kth periods of 1 ⁇ k ⁇ n ⁇ 1 with respect to the effective display area, the signal writing is completed in the kth period A signal corresponding to gray data is output to a data signal line that is not connected to.
- the display device driving method of the present invention is an active matrix display device driving method in which the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture elements. And those connected to the data signal line adjacent to the other side of the picture element are arranged immediately before the first period which is a horizontal period in which the signal is written at the beginning of the effective display area. From the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area, with a period corresponding to one horizontal period as the 0th period.
- the display device of the present invention is an active matrix type display device, and the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture elements. And one connected to the data signal line adjacent to the other side of the picture element are arranged one horizontal just before the first period which is a horizontal period in which the signal is written at the beginning of the effective display area.
- a period having a length corresponding to the period is defined as a 0th period, and the k period from the 0th period to the nth period (n is an integer), which is a horizontal period in which a signal is written at the end of the effective display area.
- each data signal line has an invariable potential polarity with respect to the common potential as a reference, and adjacent data.
- the potential polarity is opposite to that of the signal output to the signal line.
- the pixels that are output in a line-sequential manner and are written in the k-th period in the effective display area are connected from the period of the (k-1) period to the period of the k-th period.
- the pixel is not connected to a pixel that completes signal writing in the kth period.
- the data signal line is configured to output the signal output during the (k ⁇ 1) th period.
- the display device driving method of the present invention is an active matrix display device driving method in which the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture elements. And those connected to the data signal line adjacent to the other side of the picture element are arranged immediately before the first period which is a horizontal period in which the signal is written at the beginning of the effective display area. From the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area, with a period corresponding to one horizontal period as the 0th period.
- the data signal lines that are not connected to the picture elements that complete the signal writing in the kth period have (k ⁇ Since the signal output during the period of 1) is output, in the row where the connection of the pixel to the data signal line is switched to the previous row, the pixel located at the left end or the right end;
- the difference between the data signal line output voltages during the preliminary charging period is eliminated with the other picture elements, and as a result, the potential charged in the liquid crystal can be eliminated.
- FIG. 1 is a schematic diagram illustrating an embodiment of a display device according to the present invention. It is a top view which shows the structure of the liquid crystal panel in the said display apparatus. It is a figure which shows a mode that the video signal supplied to the said liquid crystal panel is rearranged for every line in the timing controller of the said display apparatus. It is a wave form diagram which shows each signal waveform of the display start vicinity when displaying the image of 1 frame on the said liquid crystal panel. It is a wave form diagram which shows each signal waveform of the display end vicinity when displaying the image of 1 frame on the said liquid crystal panel. It is a top view which shows the other structure of the liquid crystal panel in the said display apparatus.
- FIG. 1 is a schematic diagram showing a configuration example of the liquid crystal display device 10 of the present embodiment.
- FIG. 2 is a plan view showing a configuration example of the liquid crystal panel 20. 1 and 2 show characteristic portions, and other portions and well-known configurations are omitted as appropriate.
- the liquid crystal display device 10 is an active matrix type display device, and includes a timing controller 11, a source driver 18, a gate driver 19, and a liquid crystal panel 20, as shown in FIG.
- the liquid crystal display device 10 is configured as a TV liquid crystal module, for example, but is not limited thereto.
- the timing controller 11 controls the supply of a video signal to the liquid crystal panel 20, and includes a video signal receiving unit 12, an image processing unit 13, a line buffer unit 14, a video signal mapping unit 15, a video signal transmitting unit 16, and A source driver / gate driver control signal generator 17 is provided.
- the video signal receiver 12 receives a video signal supplied to the liquid crystal panel 20 based on an image to be displayed.
- the video signal is a digital signal sent from a CPU or the like by, for example, LVDS (Low Voltage Differential Signal) transmission.
- LVDS Low Voltage Differential Signal
- the liquid crystal module for TV mainly uses the LVDS standard, but is not limited to this.
- the video signal receiving unit 12 outputs the received video signal to the image processing unit 13.
- the image processing unit 13 performs image processing for improving the display quality of the liquid crystal panel 20 on the input video signal.
- the image processing unit 13 mainly performs image processing such as Over-Drive (overdrive), independent ⁇ correction, FRC (frame rate control), Dither (dither), but is not limited thereto.
- the image processing unit 13 outputs the image-processed video signal to the line buffer unit 14.
- the line buffer unit 14 temporarily stores video signals for several lines in order to adjust the timing of the video signal supplied to the liquid crystal panel 20 and the control signal supplied to the source driver 18 / gate driver 19.
- the line buffer unit 14 outputs the video signal to the video signal mapping unit 15 after the adjustment.
- the video signal mapping unit 15 rearranges the video signals in accordance with the picture elements 23 of the liquid crystal panel 20. That is, since the staggered arrangement is provided as will be described later, a picture element 23 adjacent to the left side or the right side is connected to one source bus line 21. Therefore, the video signal mapping unit 15 rearranges the video signals supplied to the source driver 18 so that the output is performed to the appropriate source bus line 21 for each row. At the same time, the video signal mapping unit 15 outputs, for example, six pairs of video signals for one row by mini-LVDS transmission from the video signal transmission unit 16, so that video signals are arranged in accordance with this output. We are changing. The video signal mapping unit 15 inserts dummy data when rearranging video signals for one row. This will be described in detail later.
- the video signal mapping unit 15 outputs the rearranged video signals to the video signal transmission unit 16. In addition, when a video signal to be rearranged is input, the video signal mapping unit 15 outputs a notification signal for notifying the video signal to the source driver / gate driver control signal generation unit 17.
- the video signal transmission unit 16 outputs the input video signal to the source driver 18.
- the liquid crystal module for TV mainly uses the mini-LVDS standard, but of course it is not limited to this.
- the source driver / gate driver control signal generation unit 17 generates a source driver control signal and a gate driver control signal in response to the notification signal from the video signal mapping unit 15.
- source driver control signals there are a latch signal LS, an inversion signal REV, and a frame start signal FS.
- the gate driver control signals include gate clock signals GCK1 to GCK4, gate start pulse signals GSP1 and GSP2, gate end pulse signals GEP1 and GEP2, and a signal GCL.
- the source driver / gate driver control signal generation unit 17 outputs a source driver control signal to the source driver 18 and outputs a gate driver control signal to the gate driver 19.
- the source driver 18 is a driver that generates and outputs a data signal for driving the picture element 23 of the liquid crystal panel 20.
- One or a plurality of source drivers 18 are provided so as to have an output corresponding to a source bus line 21 (data signal line) provided in the liquid crystal panel 20.
- the source driver 18 latches the video signal output from the timing controller 11 based on the latch signal LS, inputs the video signal for one row, and then the data signal (analog gradation voltage signal) based on each video signal. , And simultaneously output data signals for one row to the corresponding source bus lines 21 of the liquid crystal panel 20.
- the source driver 18 is configured to output a data signal having a reverse polarity to the adjacent source bus line 21. Further, the source driver 18 outputs to each source bus line 21 without changing the potential polarity with the common potential as a reference during the frame period, and based on the inverted signal REV that is switched every frame. The polarity is changed every frame period. For example, during the frame period, when the inverted signal REV is at a high level, each data signal is output to the odd-numbered source bus line 21 with positive polarity, and each data signal is output to the even-numbered source bus line 21. Output with negative polarity. When the inverted signal REV is at a low level, it is output with the opposite polarity.
- the gate driver 19 is a driver that generates and outputs a scanning signal for selecting the picture element 23 to which the data signal output from the source driver 18 is written.
- the gate driver 19 is monolithically built in the liquid crystal panel 20 so as to have an output corresponding to the gate bus line 22 provided in the liquid crystal panel 20.
- the gate driver 19 generates a scanning signal according to the gate driver control signal and outputs it to the corresponding gate bus line 22 of the liquid crystal panel 20.
- the liquid crystal panel 20 is configured to enclose liquid crystal in two transparent substrates facing each other, and display an image by electrically changing the orientation of the liquid crystal.
- a source bus line 21, a gate bus line 22, and a picture element 23 are formed on the surface on the side where the liquid crystal is sandwiched as shown in FIG.
- FIG. 2 mainly shows an effective display area configured with 768 ⁇ 1366 pixels (one pixel 24 with 2 ⁇ 2 picture elements 23) in the liquid crystal panel 20.
- the source bus lines 21 are formed so that the number of columns of the picture elements 23 + 1 (2773 in FIG. 2: source bus lines S1 to S2773) is formed so as to extend in the vertical direction, and one end is connected to the source driver 18 It is connected.
- the gate bus line 22 is formed so as to extend in the horizontal direction, the number of rows of the picture elements 23 + ⁇ (in FIG. 2, 1536 + 4), and one end is connected to the gate driver 19.
- the gate bus line 22 includes gate bus lines G1 to G1536 connected to the picture elements 23 (picture elements involved in display) located in the effective display area, and picture elements 23 located in a non-display area (not shown).
- the gate bus lines GD0 and GD1 the gate bus lines G1 to G1536, and the gate bus lines GD2 and GD3 are arranged in this order from the top.
- a plurality of picture elements 23 are formed in a matrix (1536 ⁇ 2772 in the effective display area, 4 ⁇ 2772 in the non-display area).
- the picture element 23 is connected to the source bus line 21 via, for example, a TFT (not shown) connected to the gate bus line 22.
- the gate terminals of the TFTs of the picture elements 23 in each row are connected in common to the corresponding gate bus lines 22.
- Two source terminals of the TFTs of the picture elements 23 in each column are alternately connected to the source bus lines 21 adjacent to the left and right.
- the picture elements 23 in the first and second rows of the effective display area are connected to the adjacent source bus line 21 on the left side.
- Each picture element 23 in the third and fourth rows is connected to a source bus line 21 adjacent on the right side.
- the picture elements 23 in each column are connected to the source bus line 21 adjacent to one side (left side) of the picture element 23, and the source bus lines 21 adjacent to the other side (right side) of the picture element 23. Are connected alternately to each other. That is, the liquid crystal panel 20 has a staggered configuration.
- the picture elements 23 are arranged in an effective display area shown in FIG. 2 and a non-display area (not shown).
- the picture elements 23 located in the effective display area are scanned by the gate bus lines G1 to G1536.
- the picture element 23 located in the non-display area is scanned by the gate bus lines GD0 to GD3.
- the picture elements 23 located in the non-display area are formed in two rows at the top and two rows at the bottom in the plan view shown in FIG.
- the top two picture elements are connected to the adjacent source bus line 21 on the right side.
- the bottom two picture elements are connected to the adjacent source bus line 21 on the left side.
- a color filter and a common electrode to which a common voltage is applied are laminated in this order on the surface on the side sandwiching the liquid crystal.
- the color filter takes four picture elements 23 as one unit, R (red) for the upper left picture element 23, G (green) for the upper right picture element 23, B (blue) for the lower left picture element 23, and the lower right picture element 23. It is arranged so that Y (yellow) is positioned corresponding to the picture element 23.
- one pixel 24 of RGBY is configured by 2 ⁇ 2 picture elements 23 adjacent in the vertical and horizontal directions.
- FIG. 3 is a diagram illustrating a state in which the video signal supplied to the liquid crystal panel 20 is rearranged for each row by the video signal mapping unit 15 of the timing controller 11.
- FIG. 4 is a waveform diagram showing signal waveforms in the vicinity of the start of display when an image of one frame is displayed on the liquid crystal panel 20.
- FIG. 5 is a waveform diagram showing signal waveforms near the end of display when an image of one frame is displayed on the liquid crystal panel 20.
- pseudo dot inversion driving is performed by combining a staggered pixel matrix and source bus line inversion driving. That is, the source driver 18 outputs substantially the same polarity with respect to the adjacent source bus line 21 within the frame period, and the liquid crystal panels 20 are arranged in a staggered manner. Dot inversion drive is performed. Further, in order to make all the picture elements 23 in the row reach a desired potential during the horizontal period, the data signal output to the source bus line 21 during the previous horizontal period, that is, the previous one. Precharging is performed using the output.
- a video signal for one row is supplied to the timing controller 11 in units of pixels based on the LVDS transmission clock signal LVDS_CLK.
- the timing controller 11 receives the video signal (R768, G768, B768) of the pixel 24 in the 768th row from the video signal (R1, G1, B1) of the pixel 24 in the first row during the period tHA while sandwiching the period tHB. Enter until.
- the video signal supplied to the timing controller 11 is received by the video signal receiving unit 12, subjected to image processing by the image processing unit 13, and then temporarily held in the line buffer unit 14, so that the video signal mapping unit 15 is input.
- the video signal mapping unit 15 supplies the video signal to the pixel 24 in the first row, that is, the first and second picture elements 23 in the effective display area.
- precharge data is generated.
- the precharge data is data that is output from all the source bus lines 21 and is generated according to a preset gradation.
- the precharge data is also data for writing to the picture elements 23 in the first and second rows of the non-display area.
- the video signal mapping unit 15 generates, for example, solid data corresponding to R / G of 128 gradations as data to be supplied to the picture element 23 in the first row of the non-display area, and rearranges the image data into 6 pairs to display the video data. Output to the signal transmitter 16. Subsequently, the video signal mapping unit 15 generates, for example, solid data corresponding to B / Y of 128 gradations as data to be supplied to the picture elements 23 in the second row of the non-display area, and rearranges them in 6 pairs. To the video signal transmitter 16.
- the solid-state data corresponding to R / G of 128 gradations and the solid data corresponding to B / Y of 128 gradations are sequentially output from the video signal transmission unit 16 to the source driver 18. Since the video signal transmission unit 16 outputs data for all the source bus lines 21 every six pairs, data for one row is output by repeating the output operation 456 times.
- the video signal mapping unit 15 supplies a video signal to be supplied to the picture elements 23 corresponding to R and G in the first row shown in FIG. As shown in n_Line in FIG. At this time, the video signal mapping unit 15 rearranges the video signals and inserts dummy data at the end, that is, after the video signal to be supplied to the G1366 picture element 23.
- the data at the same output position of the rearranged data of the previous line is used. That is, in this case, as the dummy data, data output from the data bus LV2P / M at the 456th output when the data corresponding to B / Y of 128 gradations generated as precharge data is rearranged ( Data corresponding to Y of 128 gradations) is used. In other words, data corresponding to the output of the source bus line S2773 in the previous row is used.
- the video signal mapping unit 15 outputs the video signal rearranged in this way and inserted with dummy data to the video signal transmission unit 16.
- the video signal in the first row is output from the video signal transmission unit 16 to the source driver 18.
- the video signal mapping unit 15 supplies a video signal to be supplied from the input video signal of the pixels 24 in the first row to the picture elements 23 corresponding to B and Y in the second row shown in FIG. As shown in n + 1_Line in FIG. At this time, the video signal mapping unit 15 rearranges the video signals and inserts dummy data at the end, that is, after the video signal to be supplied to the Y1366 picture element 23.
- the data at the same output position of the rearranged data of the previous line is used. That is, in this case, as the dummy data, data output from the data bus LV2P / M at the time of the 456th output when the video signal of the first row which is the previous row is rearranged (Y of 128 gradations). Data corresponding to).
- the video signal mapping unit 15 outputs the video signal rearranged in this way and inserted with dummy data to the video signal transmission unit 16.
- the video signal in the second row is output from the video signal transmission unit 16 to the source driver 18.
- the video signal mapping unit 15 outputs a notification signal to the source driver / gate driver control signal generation unit 17. Based on this notification signal, the source driver / gate driver control signal generator 17 outputs the frame start signal FS and then the inverted signal REV to the source driver 18. The source driver / gate driver control signal generator 17 outputs gate start pulses GSP1 and GSP2 to the gate driver 19. The output from the source driver / gate driver control signal generation unit 17 is performed before the solid data corresponding to R / G of 128 gradations is output from the video signal transmission unit 16.
- the source driver / gate driver control signal generation unit 17 outputs the latch signal LS to the source driver 18 for each horizontal period and outputs the gate clock signals GCK1 to GCK4 to the gate driver 19.
- the gate clock signals GCK1 to GCK4 have four phases, and the gate clock signals GCK3 and GCK4 having opposite phases are delayed by one horizontal period with respect to the gate clock signals GCK1 and GCK2 having opposite phases.
- the source driver 18 receives the video signal output from the video signal transmission unit 16 of the timing controller 11 based on the latch signal LS. Then, after the video signal for one row is input, a data signal corresponding to each video signal is generated, and the data signal for one row is output to the source bus line 21 of the liquid crystal panel 20 all at once.
- data signals based on the solid data are output to the source bus lines S1 to S2773.
- the data signal based on the video signal is output to the source bus lines S1 to S2772, and the source bus line S2773 is based on dummy data.
- a data signal is output.
- positive data signals are output to the odd-numbered source bus lines S1, S3,.
- a negative data signal is output to S2, S4,..., S2772. Note that, for each frame, the positive polarity and the negative polarity are switched based on the inverted signal REV.
- the gate driver 19 starts scanning the gate bus line 22 based on the gate start pulses GSP1 and GSP2.
- the scanning signal output to each gate bus line 22 is generated in synchronization with the gate clock signals GCK1 to GCK4, and the latter half of the output period is one horizontal period in which the corresponding data signal is written to the picture element 23. Is output.
- a scanning signal is output to the gate bus line GD0.
- blanking data is written in the first half of the output period to the picture element 23 connected to the gate bus line GD0, that is, the first row of picture elements 23 in the non-display area, and the second half of the output period is 128 gray levels.
- a data signal based on the solid data corresponding to R ⁇ G is written.
- the scanning signal is output to the gate bus line GD1 one horizontal period after the scanning signal is output to the gate bus line GD0.
- data based on solid data corresponding to R / G of 128 gradations in the first half of the output period is applied to the picture element 23 connected to the gate bus line GD1, that is, the picture element 23 in the second row of the non-display area.
- a signal is written, and in the second half of the output period, a data signal based on solid data corresponding to B ⁇ Y of 128 gradations is written.
- a scanning signal is output to the gate bus line G1 one horizontal period after the scanning signal is output to the gate bus line GD1.
- data based on solid data corresponding to B / Y of 128 gradations in the first half of the output period is applied to the picture element 23 connected to the gate bus line G1, that is, the picture element 23 in the first row of the effective display area.
- the signal is written, and the data signal of the first row is written in the second half of the output period.
- the scanning signal is output to the gate bus line G2 one horizontal period after the scanning signal is output to the gate bus line G1.
- the data signal of the first row is written in the first half of the output period to the picture element 23 connected to the gate bus line G2, that is, the second row of picture elements 23 in the effective display area, and the second half of the output period The data signal in the second row is written.
- the scanning signal is output overlapping with the output period of the scanning signal output to the previous gate bus line 22. That is, the scanning signal output during a certain horizontal period is output from the previous horizontal period.
- the picture element 23 in the (n + 1) th row is precharged after being precharged by the data signal to be written in the picture element 23 in the previous nth row. Therefore, even when the main charging time is short, the potential of the data signal to be written can be sufficiently reached.
- the video signal mapping unit 15 supplies the input video signal of the pixels 24 in the second row to the picture elements 23 corresponding to R and G in the third row shown in FIG. 2.
- the video signals to be rearranged are rearranged so that there are 6 pairs each as indicated by n + 2_Line in FIG.
- the video signal mapping unit 15 rearranges the video signals and inserts dummy data at the very beginning, that is, before the video signal to be supplied to the R0001 picture element 23.
- the data at the same output position of the rearranged data of the previous line is used. That is, in this case, as the dummy data, the data (data corresponding to B0001) output from the data bus LV0P / M at the first output when the video signal of the second row, which is the previous row, is rearranged. ) Is used.
- the video signal mapping unit 15 outputs the video signal rearranged in this way and inserted with dummy data to the video signal transmission unit 16.
- the video signal in the third row is output from the video signal transmission unit 16 to the source driver 18.
- the video signal mapping unit 15 supplies a video signal to be supplied from the input video signal of the pixels 24 in the second row to the picture elements 23 corresponding to B and Y in the fourth row shown in FIG. As shown by n + 3_Line in FIG. At this time, the video signal mapping unit 15 rearranges the video signals and inserts dummy data at the very beginning, that is, before the video signal to be supplied to the picture element 23 of B0001.
- the data at the same output position of the rearranged data of the previous line is used. That is, in this case, as the dummy data, the data (data corresponding to B0001) output from the data bus LV0P / M at the first output when the video signal in the third row, which is the previous row, is rearranged. ) Is used.
- the video signal mapping unit 15 outputs the video signal rearranged in this way and inserted with dummy data to the video signal transmission unit 16.
- the video signal in the fourth row is output from the video signal transmission unit 16 to the source driver 18.
- the video signal mapping unit 15 rearranges the video signals as shown in FIG. 3 up to the video signal of the pixel 24 in the 768th row in the same manner after the input of the video signal of the pixel 24 in the third row.
- the operation of inserting dummy data brought from the previous row at the very beginning or the very end in accordance with the row to which the video signal is supplied is repeated for each row.
- the row in which the picture element 23 is connected to the source bus line 21 adjacent to the left side (the picture element 23 located at the left end is connected to the source bus line S1 at the left end).
- the pixel 23 located at the right end is connected to the source bus line S2772 adjacent to the right end)
- it is held from the previous row at the very end of the rearranged data. Insert dummy data.
- the row in which the picture element 23 is connected to the adjacent source bus line 21 on the right side is the source bus line next to the left end.
- the picture element 23 located at the right end is connected to S2 and is connected to the source bus line S2773 on the right end
- it is brought from the previous line at the very beginning of the rearranged data. Insert dummy data.
- the source driver 18 receives the video signal output from the video signal transmission unit 16 of the timing controller 11 based on the latch signal LS. Then, after the video signal for one row is input, a data signal corresponding to each video signal is generated, and the data signal for one row is output to the source bus line 21 of the liquid crystal panel 20 all at once.
- a data signal based on dummy data is output to the source bus line S1
- a data signal based on the video signal is output to the source bus lines S2 to S2773. Is done.
- the data signal based on the video signal is output to the source bus lines S1 to S2772, and the data based on the dummy data is output to the source bus line S2773.
- a signal is output.
- the source bus lines S1 to S2772 have the above-mentioned A data signal based on the video signal is output, and a data signal based on the dummy data is output to the source bus line S2773.
- a data signal based on dummy data is output to the source bus line S1
- a data signal based on the video signal is output.
- the gate driver 19 outputs a scanning signal to the gate bus line G3 one horizontal period after the scanning signal is output to the gate bus line G2.
- the data signal of the second row is written to the picture element 23 connected to the gate bus line G3, that is, the picture element 23 of the third row, in the first half of the output period, and in the third half of the output period. Data signal is written.
- the scanning signal is output to the gate bus line G4 one horizontal period after the scanning signal is output to the gate bus line G3.
- the data signal of the third row is written in the picture element 23 connected to the gate bus line G4, that is, the picture element 23 of the fourth row in the first half of the output period, and the fourth row in the second half of the output period. Data signal is written.
- scanning signals are sequentially output to the gate bus lines G5 to G1536 in the same manner up to the output to the picture element 23 on the 1536th line, and the picture element 23 on each line outputs the previous output in the first half of the output period. Is precharged and the main charge is performed in the latter half of the output period. Finally, a scanning signal is output to the gate bus lines GD2 and GD3, and blanking data is written into the picture element 23 in the non-display area located at the bottom.
- the source driver 18 has an invariable polarity within the frame period and outputs an opposite polarity to the adjacent source bus line 21, and the liquid crystal panels 20 are arranged in a staggered manner. Thus, it is possible to perform dot inversion driving substantially.
- the source driver 18 when the source driver 18 is outputting to, for example, the picture element 23 in the second row, a data signal based on dummy data is output to the source bus line S2773.
- the source bus line S2773 at this time is not connected to the picture element 23, it is regarded as an empty state, that is, a non-display area, and has a minimum gradation voltage (for example, a black voltage in the case of normally black).
- the rightmost picture element 23 is not precharged and a data signal is written to the picture element 23 in the third row.
- the desired potential could not be sufficiently reached.
- the data signal based on the dummy data brought from the previous row is output to the source bus line S2773.
- the source bus line S1 or S2773 that is not connected to the picture element 23 that writes the data signal in the horizontal period is output during the previous horizontal period.
- the previously received data signal is output. Therefore, in the odd-numbered row, that is, the row in which the connection of the picture element 23 to the source bus line 21 is switched to the previous line, the spare picture element 23 is located at the left and right ends and the other picture elements 23 are reserved.
- the difference in the source output voltage during the charging period is eliminated, and as a result, it is possible to eliminate the difference in the potential charged in the liquid crystal.
- Embodiment 1 did not necessarily need to be staggered arrangement.
- the picture element and the gate bus line in the non-display area are not necessarily required.
- the order of selecting the picture elements for the main charging is not necessarily the order in which the rows are arranged, and the interlaced scanning for selecting the rows of the picture elements may be performed.
- the picture elements 23 in each column of the effective display area are connected to the source bus line 21 adjacent to one side of the picture element 23 and the source bus adjacent to the other side of the picture element 23. Is connected to the line 21 and has a period corresponding to one horizontal period immediately before the first period which is a horizontal period in which a signal is written at the beginning of the effective display area.
- the kth period (k is the consecutive period in the order of k) from the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area.
- each source bus line 21 has a potential polarity that does not change with respect to the common potential, and the signal output to the adjacent source bus line 21 is Signal with reverse polarity polarity
- the picture element 23 that is output next and completes signal writing in the k-th period in the effective display area is connected to the connected source from the period of the (k ⁇ 1) period to the period of the k-th period.
- the bus line 21 may be configured to output the signal output during the (k ⁇ 1) th period.
- the liquid crystal panel 20 is not limited to the one having the configuration shown in FIG. 2, but the number of the picture elements 23 in each column in the arrangement of the picture elements 23 constituting the pixels 24 or the staggered arrangement. Whether to connect to the source bus lines 21 adjacent to the left and right can be appropriately changed according to the design.
- a liquid crystal panel 30 as shown in FIG. 6 may be provided.
- FIG. 6 is a plan view showing a configuration example of the liquid crystal panel 30.
- FIG. 6 shows a case where the effective display area of the liquid crystal panel 30 is composed of 768 ⁇ 1366 pixels. Further, in FIG. 6, characteristic portions are illustrated, and other portions and known configurations are appropriately omitted.
- the liquid crystal panel 30 is different from the liquid crystal panel 20 of the first embodiment in the arrangement of picture elements 33 constituting one pixel 34 as shown in FIG.
- the picture elements 33 are connected in common to the corresponding gate bus lines 22 in row units, and are connected alternately one by one to the source bus lines 21 adjacent to the left and right in column units. That is, the liquid crystal panel 30 has a staggered configuration.
- the color filter is arranged so that three picture elements 33 are set as one unit, and R is located on the upper picture element 33, G is located on the middle picture element 33, and B is located on the lower picture element 33.
- R is located on the upper picture element 33
- G is located on the middle picture element 33
- B is located on the lower picture element 33.
- one pixel 34 of RGB is constituted by three picture elements 33 adjacent in the vertical direction.
- FIG. 7 is a diagram illustrating a state in which the video signals supplied to the liquid crystal panel 30 are rearranged for each row by the video signal mapping unit 15 of the timing controller 11.
- FIG. 8 is a waveform diagram showing signal waveforms in the vicinity of the display start when an image of one frame is displayed on the liquid crystal panel 30.
- FIG. 9 is a waveform diagram showing signal waveforms near the end of display when an image of one frame is displayed on the liquid crystal panel 30.
- the basic operation that is, the video signals (R1 ⁇ G1 ⁇ B1) of the pixels 34 in the first row to the video signals (R768 ⁇ G768 ⁇ B768) of the pixels 34 in the 768th row are sequentially input to the timing controller 11, A series of operations until the data signal based on the video signal is applied to the picture element 33 of the liquid crystal panel 30 in a line sequential manner is the same as the operation described in the first embodiment.
- the video signal mapping unit 15 of the timing controller 11 rearranges the video signals and performs the operation of inserting dummy data brought from the previous row at the very beginning or at the very end. Repeat every time.
- the source bus line S1 or S2773 that is not connected to the picture element 23 that writes the data signal in the horizontal period is output during the previous horizontal period.
- Data signal is output. Therefore, in each row, that is, in a row in which the connection of the picture element 33 to the source bus line 21 is switched to the previous line, the picture element 33 located on the left and right ends and the other picture elements 33 have a precharge period. The difference in source output voltage is eliminated, and as a result, the difference in potential charged in the liquid crystal can be eliminated.
- the liquid crystal display device 10 described above may include a liquid crystal panel 30 as shown in FIG. 10, for example.
- FIG. 10 is a plan view illustrating a configuration example of the liquid crystal panel 40.
- FIG. 10 shows a case where the effective display area of the liquid crystal panel 40 is composed of 768 ⁇ 1366 pixels. Further, in FIG. 10, characteristic portions are illustrated, and other portions and known configurations are appropriately omitted.
- the liquid crystal panel 40 differs from the liquid crystal panel 30 of the second embodiment in the arrangement of picture elements 43 constituting one pixel 34 as shown in FIG.
- the color filter is arranged so that three picture elements 43 are one unit and R is located on the left picture element 43, G is located on the middle picture element 43, and B is located on the right picture element 43.
- one pixel 44 of RGB is configured by three picture elements 43 adjacent in the horizontal direction.
- the liquid crystal display device 10 having the liquid crystal panel 40 is driven in the same manner as the liquid crystal display device 10 having the liquid crystal panel 30 of the second embodiment, thereby performing preliminary charging with the output of the previous row. It is possible to eliminate dot-like unevenness that occurs on the left and right edges of the display screen.
- the dummy data is not limited to this. In other words, display unevenness occurs when a difference occurs in the ultimate potential charged in the liquid crystal. Therefore, from the viewpoint of preliminary charging, the dummy data may be data having the same polarity as that of the main charging data.
- gray data halftone for each color
- the video signal mapping unit 15 may insert gray data stored in advance as dummy data, for example, when rearranging the video signals.
- the dummy data it is possible to use a black voltage (a signal corresponding to the lowest luminance gradation) and a white voltage (a signal corresponding to the highest luminance gradation) which is closer to the target potential of the main charging. By supplying this, you can charge quickly.
- a method is adopted in which data to be displayed later is stored early in the frame memory of the control board, and the signal potential for precharging is determined as a black voltage or a white voltage while referring to the data. It is possible.
- the pixel in each of the kth periods of 1 ⁇ k ⁇ n ⁇ 1 with respect to the effective display area, the pixel is not connected to the pixel that has completed writing the signal in the kth period, and in the (k + 1) th period.
- the source bus line 21 connected to the picture element for which signal writing is completed has the lowest luminance level based on the signal to be written to the picture element for which signal writing has been completed in the (k + 1) period.
- a configuration in which one of the signal corresponding to the tone and the signal corresponding to the maximum luminance gradation is output may be employed.
- the display device of the present invention is an active matrix type display device, and the pixels in each column of the effective display area are connected to the data signal line adjacent to one side of the pixels, The one connected to the data signal line adjacent to the other side is arranged and corresponds to one horizontal period immediately before the first period which is the horizontal period in which the signal is written at the beginning of the effective display area.
- a period having a length is defined as a 0th period, and a continuous period in the order of k from a 0th period to an nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area.
- each data signal line has the same potential polarity with respect to the common potential, and is output to the adjacent data signal line.
- the signal with the opposite polarity to the signal The pixel that is output to the pixel and completes the signal writing in the k-th period in the effective display area is connected to the data signal line connected from the period of the (k ⁇ 1) period to the period of the k-th period.
- the data signal lines that are not connected to the pixels that complete the signal writing in the kth period The signal output during the (k ⁇ 1) th period is output.
- the display device of the present invention is an active matrix type display device in which the picture element in each column of the effective display area is connected to a data signal line adjacent to one side of the picture element. Are connected to the data signal line adjacent to the other side of the element, and are arranged for one horizontal period immediately before the first period which is the horizontal period in which the signal is written at the beginning of the effective display area.
- a period having a corresponding length is defined as a 0th period, and is continuous in the order of k from the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area.
- each data signal line has an invariable potential polarity with respect to the common potential, and the adjacent data signal lines A signal with a polarity opposite to that of the output signal Pixels that are output line-sequentially and that complete the signal writing in the k-th period in the effective display area are connected data from the period of the (k-1) period to the period of the k-th period.
- a data signal line that is selected to be conductive with the signal line and is not connected to a pixel that completes signal writing in the kth period in each of the kth period of 1 ⁇ k ⁇ n ⁇ 1 with respect to the effective display area May be configured to output a signal corresponding to gray data.
- the display device of the present invention is an active matrix type display device in which the picture element in each column of the effective display area is connected to a data signal line adjacent to one side of the picture element. Are connected to the data signal line adjacent to the other side of the element, and are arranged for one horizontal period immediately before the first period which is the horizontal period in which the signal is written at the beginning of the effective display area.
- a period having a corresponding length is defined as a 0th period, and is continuous in the order of k from the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area.
- each data signal line has an invariable potential polarity with respect to the common potential, and the adjacent data signal lines A signal with a polarity opposite to that of the output signal Pixels that are output line-sequentially and that complete the signal writing in the k-th period in the effective display area are connected data from the period of the (k-1) period to the period of the k-th period.
- Each of the kth periods of 1 ⁇ k ⁇ n ⁇ 1 with respect to the effective display area is selected to be electrically connected to the signal line, and is not connected to a pixel that completes signal writing in the kth period; and A data signal line connected to a picture element for which signal writing is completed in the (k + 1) period is used as a signal to be written to the picture element in which signal writing is completed in the (k + 1) period.
- a configuration in which one of the signal corresponding to the minimum luminance gradation and the signal corresponding to the maximum luminance gradation is output may be employed.
- each picture element in the effective display area has 2 ⁇ 2 picture elements adjacent to each other in the vertical and horizontal directions, each corresponding to R, G, B, and Y as one pixel.
- the picture elements in each column of the effective display area arranged in a matrix are connected to the data signal line adjacent to one side of the picture element and the data signal adjacent to the other side of the picture element. It is preferable that the two connected to the line are alternately arranged.
- each picture element in the effective display area is arranged in a matrix with three picture elements corresponding to R, G, and B adjacent in the vertical or horizontal direction as one pixel.
- the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture element and to the data signal line adjacent to the other side of the picture element. It is preferable to arrange them alternately one by one.
- the display device drive method of the present invention is a drive method of an active matrix display device, wherein the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture elements. And the one connected to the data signal line adjacent to the other side of the picture element are arranged, and 1 immediately before the first period which is a horizontal period in which the signal is written at the beginning of the effective display area.
- a period having a length corresponding to the horizontal period is defined as a 0th period, from the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area.
- each data signal line is adjacent to the potential polarity with the common potential as a reference, and is adjacent to each data signal line.
- Potential of the opposite polarity to the signal output to the data signal line A pixel that is line-sequentially output, and a pixel that has been written in the effective display area in the k-th period from the period of the (k ⁇ 1) period to the period of the k-th period, It is selected to be electrically connected to the connected data signal line, and is connected to a pixel that completes signal writing in the kth period in each of the kth period of 1 ⁇ k ⁇ n ⁇ 1 with respect to the effective display area.
- the data signal line that has not been output has the configuration for outputting the signal output during the (k ⁇ 1) th period.
- the display device driving method of the present invention is an active matrix display device driving method in which the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture elements. And those connected to the data signal line adjacent to the other side of the picture element are arranged immediately before the first period which is a horizontal period in which the signal is written at the beginning of the effective display area. From the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area, with a period corresponding to one horizontal period as the 0th period.
- the data signal line that is not used may be configured to output a signal corresponding to gray data.
- the display device driving method of the present invention is an active matrix display device driving method in which the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture elements. And those connected to the data signal line adjacent to the other side of the picture element are arranged immediately before the first period which is a horizontal period in which the signal is written at the beginning of the effective display area. From the 0th period to the nth period (n is an integer) which is a horizontal period in which a signal is written at the end of the effective display area, with a period corresponding to one horizontal period as the 0th period.
- each picture element in the effective display area has 2 ⁇ 2 picture elements adjacent to each other in the vertical and horizontal directions, corresponding to R, G, B, and Y, respectively.
- the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture element, and adjacent to the other side of the picture element. It is preferable that two data signal lines connected to each other are alternately arranged.
- each picture element in the effective display area is a matrix in which three picture elements adjacent to the vertical or horizontal direction respectively corresponding to R, G, and B are defined as one pixel.
- the picture elements in each column of the effective display area are connected to the data signal line adjacent to one side of the picture element and the data signal line adjacent to the other side of the picture element. It is preferable that the connected ones are alternately arranged one by one.
- the present invention can be suitably used not only in a field related to a liquid crystal display device including a staggered liquid crystal panel but also in a field related to a method for manufacturing a liquid crystal display device, and further includes a liquid crystal display device.
- the present invention can be widely used in various fields related to electronic devices.
- Liquid crystal display device (display device) DESCRIPTION OF SYMBOLS 11 Timing controller 12 Video signal receiving part 13 Image processing part 14 Line buffer part 15 Video signal mapping part 16 Video signal transmission part 17 Source driver / gate driver control signal generation part 18 Source driver 19 Gate driver 20, 30, 40 Liquid crystal panel 21 Source bus line (data signal line) 22 gate bus lines 23, 33, 43 picture elements 24, 34, 44 pixels
Abstract
Description
本発明の一実施形態について図面に基づいて説明すれば、以下の通りである。
上述した液晶表示装置10において、液晶パネル20は、図2に示した構成を有するものに限らず、画素24を構成する絵素23の配置や、千鳥配置において各列の絵素23を何個ずつ左右に隣接するソースバスライン21に接続するかは、設計に応じて適宜変更可能であり、例えば図6に示すような液晶パネル30を備えてもよい。
上述した液晶表示装置10は、例えば図10に示すような液晶パネル30を備えてもよい。図10は、液晶パネル40の一構成例を示す平面図である。なお、図10は、液晶パネル40の有効表示領域が768×1366画素で構成されている場合を示している。また、図10では、特徴的な部分を図示しており、その他の部分や周知の構成は適宜省略している。
上述した液晶表示装置10では、タイミングコントローラ11の映像信号マッピング部15による映像信号の並び替えの際、1つ前の行から持ってきたダミーデータを挿入している。これにより、各水平期間において、当該水平期間にデータ信号を書き込む絵素23に接続されていないソースバスラインS1またはS2773には、1つ前の水平期間中に出力されていたデータ信号が出力される。
11 タイミングコントローラ
12 映像信号受信部
13 画像処理部
14 ラインバッファ部
15 映像信号マッピング部
16 映像信号送信部
17 ソースドライバ/ゲートドライバ用制御信号生成部
18 ソースドライバ
19 ゲートドライバ
20,30,40 液晶パネル
21 ソースバスライン(データ信号線)
22 ゲートバスライン
23,33,43 絵素
24,34,44 画素
Claims (10)
- アクティブマトリクス型の表示装置であって、
有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが配置されており、
有効表示領域の最初に信号を書き込み完了する水平期間である第1の期間の直前の1水平期間分に相当する長さを有する期間を第0の期間として、第0の期間から有効表示領域の最後に信号を書き込み完了する水平期間である第nの期間(nは整数)までの、kの順に連続する第kの期間(kは0からnまでの整数)の各期間中に、各データ信号線には、コモン電位を極性の基準とする電位極性が不変で、かつ、隣接するデータ信号線に出力される信号とは逆極性の電位極性である信号が線順次に出力され、有効表示領域における第kの期間に信号を書き込み完了する絵素は、第(k-1)の期間の期間中から第kの期間の期間中まで、接続されているデータ信号線と導通するように選択され、
有効表示領域に対する1≦k≦n-1の第kの期間のそれぞれにおいて、第kの期間に信号を書き込み完了する絵素に接続されていないデータ信号線には、第(k-1)の期間の期間中に出力されていた上記信号が出力されることを特徴とする表示装置。 - アクティブマトリクス型の表示装置であって、
有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが配置されており、
有効表示領域の最初に信号を書き込み完了する水平期間である第1の期間の直前の1水平期間分に相当する長さを有する期間を第0の期間として、第0の期間から有効表示領域の最後に信号を書き込み完了する水平期間である第nの期間(nは整数)までの、kの順に連続する第kの期間(kは0からnまでの整数)の各期間中に、各データ信号線には、コモン電位を極性の基準とする電位極性が不変で、かつ、隣接するデータ信号線に出力される信号とは逆極性の電位極性である信号が線順次に出力され、有効表示領域における第kの期間に信号を書き込み完了する絵素は、第(k-1)の期間の期間中から第kの期間の期間中まで、接続されているデータ信号線と導通するように選択され、
有効表示領域に対する1≦k≦n-1の第kの期間のそれぞれにおいて、第kの期間に信号を書き込み完了する絵素に接続されていないデータ信号線には、グレーデータに対応する信号が出力されることを特徴とする表示装置。 - アクティブマトリクス型の表示装置であって、
有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが配置されており、
有効表示領域の最初に信号を書き込み完了する水平期間である第1の期間の直前の1水平期間分に相当する長さを有する期間を第0の期間として、第0の期間から有効表示領域の最後に信号を書き込み完了する水平期間である第nの期間(nは整数)までの、kの順に連続する第kの期間(kは0からnまでの整数)の各期間中に、各データ信号線には、コモン電位を極性の基準とする電位極性が不変で、かつ、隣接するデータ信号線に出力される信号とは逆極性の電位極性である信号が線順次に出力され、有効表示領域における第kの期間に信号を書き込み完了する絵素は、第(k-1)の期間の期間中から第kの期間の期間中まで、接続されているデータ信号線と導通するように選択され、
有効表示領域に対する1≦k≦n-1の第kの期間のそれぞれにおいて、第kの期間に信号を書き込み完了する絵素に接続されておらず、かつ第(k+1)の期間に信号を書き込み完了する絵素に接続されているデータ信号線には、第(k+1)の期間に信号を書き込み完了する絵素に第(k+1)の期間に書き込む信号に基づいて、最低輝度階調に対応する信号および最大輝度階調に対応する信号のいずれか一方の信号が出力されることを特徴とする表示装置。 - 上記有効表示領域の各絵素は、垂直および水平方向に互いに隣接する2×2個の、R・G・B・Yにそれぞれ対応する絵素を1画素として、マトリクス状に配列されており、
上記有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが、2個ずつ交互に配置されていることを特徴とする請求項1~3のいずれか1項に記載の表示装置。 - 上記有効表示領域の各絵素は、垂直または水平方向に隣接する3個の、R・G・Bにそれぞれ対応する絵素を1画素として、マトリクス状に配列されており、
上記有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが、1個ずつ交互に配置されていることを特徴とする請求項1~3のいずれか1項に記載の表示装置。 - アクティブマトリクス型の表示装置の駆動方法であって、
有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが配置されており、
有効表示領域の最初に信号を書き込み完了する水平期間である第1の期間の直前の1水平期間分に相当する長さを有する期間を第0の期間として、第0の期間から有効表示領域の最後に信号を書き込み完了する水平期間である第nの期間(nは整数)までの、kの順に連続する第kの期間(kは0からnまでの整数)の各期間中に、各データ信号線には、コモン電位を極性の基準とする電位極性が不変で、かつ、隣接するデータ信号線に出力される信号とは逆極性の電位極性である信号を線順次に出力し、有効表示領域における第kの期間に信号を書き込み完了する絵素を、第(k-1)の期間の期間中から第kの期間の期間中まで、接続されているデータ信号線と導通するように選択し、
有効表示領域に対する1≦k≦n-1の第kの期間のそれぞれにおいて、第kの期間に信号を書き込み完了する絵素に接続されていないデータ信号線には、第(k-1)の期間の期間中に出力されていた上記信号を出力することを特徴とする表示装置の駆動方法。 - アクティブマトリクス型の表示装置の駆動方法であって、
有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが配置されており、
有効表示領域の最初に信号を書き込み完了する水平期間である第1の期間の直前の1水平期間分に相当する長さを有する期間を第0の期間として、第0の期間から有効表示領域の最後に信号を書き込み完了する水平期間である第nの期間(nは整数)までの、kの順に連続する第kの期間(kは0からnまでの整数)の各期間中に、各データ信号線には、コモン電位を極性の基準とする電位極性が不変で、かつ、隣接するデータ信号線に出力される信号とは逆極性の電位極性である信号を線順次に出力し、有効表示領域における第kの期間に信号を書き込み完了する絵素を、第(k-1)の期間の期間中から第kの期間の期間中まで、接続されているデータ信号線と導通するように選択し、
有効表示領域に対する1≦k≦n-1の第kの期間のそれぞれにおいて、第kの期間に信号を書き込み完了する絵素に接続されていないデータ信号線には、グレーデータに対応する信号を出力することを特徴とする表示装置の駆動方法。 - アクティブマトリクス型の表示装置の駆動方法であって、
有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが配置されており、
有効表示領域の最初に信号を書き込み完了する水平期間である第1の期間の直前の1水平期間分に相当する長さを有する期間を第0の期間として、第0の期間から有効表示領域の最後に信号を書き込み完了する水平期間である第nの期間(nは整数)までの、kの順に連続する第kの期間(kは0からnまでの整数)の各期間中に、各データ信号線には、コモン電位を極性の基準とする電位極性が不変で、かつ、隣接するデータ信号線に出力される信号とは逆極性の電位極性である信号を線順次に出力し、有効表示領域における第kの期間に信号を書き込み完了する絵素を、第(k-1)の期間の期間中から第kの期間の期間中まで、接続されているデータ信号線と導通するように選択し、
有効表示領域に対する1≦k≦n-1の第kの期間のそれぞれにおいて、第kの期間に信号を書き込み完了する絵素に接続されておらず、かつ第(k+1)の期間に信号を書き込み完了する絵素に接続されているデータ信号線には、第(k+1)の期間に信号を書き込み完了する絵素に第(k+1)の期間に書き込む信号に基づいて、最低輝度階調に対応する信号および最大輝度階調に対応する信号のいずれか一方の信号を出力することを特徴とする表示装置の駆動方法。 - 上記有効表示領域の各絵素は、垂直および水平方向に互いに隣接する2×2個の、R・G・B・Yにそれぞれ対応する絵素を1画素として、マトリクス状に配列されており、
上記有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが、2個ずつ交互に配置されていることを特徴とする請求項6~8のいずれか1項に記載の表示装置の駆動方法。 - 上記有効表示領域の各絵素は、垂直または水平方向に隣接する3個の、R・G・Bにそれぞれ対応する絵素を1画素として、マトリクス状に配列されており、
上記有効表示領域の各列の絵素は、絵素の一方側に隣接するデータ信号線に接続されているものと、絵素の他方側に隣接するデータ信号線に接続されているものとが、1個ずつ交互に配置されていることを特徴とする請求項6~8のいずれか1項に記載の表示装置の駆動方法。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015031950A (ja) * | 2013-08-02 | 2015-02-16 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 表示装置及びその駆動方法 |
US9412293B2 (en) | 2013-04-26 | 2016-08-09 | Mitsubishi Electric Corporation | Digital data transmission apparatus and digital data transmission method |
US9891483B2 (en) | 2013-05-15 | 2018-02-13 | Sharp Kabushiki Kaisha | Liquid crystal display device |
US9911390B2 (en) | 2013-09-05 | 2018-03-06 | Sharp Kabushiki Kaisha | Liquid crystal display device |
JP2019040021A (ja) * | 2017-08-24 | 2019-03-14 | シャープ株式会社 | 表示装置、テレビ受信装置及び表示装置の製造方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8275226B2 (en) | 2008-12-09 | 2012-09-25 | Spectral Applied Research Ltd. | Multi-mode fiber optically coupling a radiation source module to a multi-focal confocal microscope |
EP2510395B1 (en) | 2009-12-08 | 2015-09-09 | Spectral Applied Research Inc. | Imaging distal end of multimode fiber |
KR102061595B1 (ko) * | 2013-05-28 | 2020-01-03 | 삼성디스플레이 주식회사 | 액정표시장치 및 그 구동방법 |
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CN109410857A (zh) * | 2018-11-12 | 2019-03-01 | 惠科股份有限公司 | 一种显示面板的跨压补偿方法、显示面板和显示装置 |
US11594200B2 (en) * | 2019-01-31 | 2023-02-28 | Novatek Microelectronics Corp. | Driving apparatus of display panel and operation method thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001042287A (ja) | 1999-07-30 | 2001-02-16 | Sony Corp | 液晶表示装置およびその駆動方法 |
JP2006106062A (ja) * | 2004-09-30 | 2006-04-20 | Sharp Corp | アクティブマトリクス型液晶表示装置およびそれに用いる液晶表示パネル |
JP2008026377A (ja) * | 2006-07-18 | 2008-02-07 | Mitsubishi Electric Corp | 画像表示装置 |
JP2008164952A (ja) * | 2006-12-28 | 2008-07-17 | Hitachi Displays Ltd | 液晶表示装置 |
JP2009086564A (ja) * | 2007-10-03 | 2009-04-23 | Hitachi Displays Ltd | 液晶表示装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2066074C1 (ru) * | 1992-12-30 | 1996-08-27 | Малое научно-производственное предприятие "ЭЛО" | Активная отображающая матрица для жидкокристаллических экранов |
CN1111754C (zh) * | 1997-03-26 | 2003-06-18 | 精工爱普生株式会社 | 液晶装置、电光装置及使用了这种装置的投影型显示装置 |
US7397455B2 (en) * | 2003-06-06 | 2008-07-08 | Samsung Electronics Co., Ltd. | Liquid crystal display backplane layouts and addressing for non-standard subpixel arrangements |
KR101032948B1 (ko) * | 2004-04-19 | 2011-05-09 | 삼성전자주식회사 | 액정 표시 장치 및 그 구동 방법 |
JP5000124B2 (ja) | 2004-11-12 | 2012-08-15 | 三星電子株式会社 | 表示装置及びその駆動方法 |
JP2008064771A (ja) * | 2004-12-27 | 2008-03-21 | Sharp Corp | 表示パネルの駆動装置、それを備えた表示装置及び表示パネルの駆動方法、並びにプログラム、記録媒体 |
JP4356616B2 (ja) * | 2005-01-20 | 2009-11-04 | セイコーエプソン株式会社 | 電源回路、表示ドライバ、電気光学装置、電子機器及び電源回路の制御方法 |
US7586476B2 (en) | 2005-06-15 | 2009-09-08 | Lg. Display Co., Ltd. | Apparatus and method for driving liquid crystal display device |
JP4711404B2 (ja) | 2005-08-12 | 2011-06-29 | 株式会社 日立ディスプレイズ | 表示装置 |
KR20070043314A (ko) * | 2005-10-21 | 2007-04-25 | 삼성전자주식회사 | 액정 디스플레이 장치 |
KR101160839B1 (ko) * | 2005-11-02 | 2012-07-02 | 삼성전자주식회사 | 액정 표시 장치 |
JP5132566B2 (ja) * | 2006-09-28 | 2013-01-30 | シャープ株式会社 | 液晶表示装置およびテレビジョン受信機 |
JP2008116556A (ja) * | 2006-11-01 | 2008-05-22 | Nec Electronics Corp | 液晶表示装置の駆動方法およびそのデータ側駆動回路 |
US8232943B2 (en) | 2006-12-20 | 2012-07-31 | Lg Display Co., Ltd. | Liquid crystal display device |
KR101374099B1 (ko) * | 2007-03-20 | 2014-03-13 | 엘지디스플레이 주식회사 | 액정표시장치 및 이의 구동방법 |
-
2010
- 2010-05-12 WO PCT/JP2010/058037 patent/WO2011007613A1/ja active Application Filing
- 2010-05-12 RU RU2012100304/08A patent/RU2494475C2/ru not_active IP Right Cessation
- 2010-05-12 EP EP10799675.3A patent/EP2455932A4/en not_active Withdrawn
- 2010-05-12 CN CN2010800311388A patent/CN102473390A/zh active Pending
- 2010-05-12 JP JP2011522754A patent/JP5341191B2/ja not_active Expired - Fee Related
- 2010-05-12 BR BR112012000939A patent/BR112012000939A2/pt not_active IP Right Cessation
- 2010-05-12 US US13/382,167 patent/US8963912B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001042287A (ja) | 1999-07-30 | 2001-02-16 | Sony Corp | 液晶表示装置およびその駆動方法 |
JP2006106062A (ja) * | 2004-09-30 | 2006-04-20 | Sharp Corp | アクティブマトリクス型液晶表示装置およびそれに用いる液晶表示パネル |
JP2008026377A (ja) * | 2006-07-18 | 2008-02-07 | Mitsubishi Electric Corp | 画像表示装置 |
JP2008164952A (ja) * | 2006-12-28 | 2008-07-17 | Hitachi Displays Ltd | 液晶表示装置 |
JP2009086564A (ja) * | 2007-10-03 | 2009-04-23 | Hitachi Displays Ltd | 液晶表示装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2455932A4 * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9412293B2 (en) | 2013-04-26 | 2016-08-09 | Mitsubishi Electric Corporation | Digital data transmission apparatus and digital data transmission method |
US9891483B2 (en) | 2013-05-15 | 2018-02-13 | Sharp Kabushiki Kaisha | Liquid crystal display device |
JP2015031950A (ja) * | 2013-08-02 | 2015-02-16 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 表示装置及びその駆動方法 |
US9911390B2 (en) | 2013-09-05 | 2018-03-06 | Sharp Kabushiki Kaisha | Liquid crystal display device |
JP2019040021A (ja) * | 2017-08-24 | 2019-03-14 | シャープ株式会社 | 表示装置、テレビ受信装置及び表示装置の製造方法 |
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US8963912B2 (en) | 2015-02-24 |
EP2455932A4 (en) | 2013-05-22 |
RU2494475C2 (ru) | 2013-09-27 |
JPWO2011007613A1 (ja) | 2012-12-27 |
EP2455932A1 (en) | 2012-05-23 |
RU2012100304A (ru) | 2013-08-27 |
BR112012000939A2 (pt) | 2019-09-24 |
US20120127153A1 (en) | 2012-05-24 |
CN102473390A (zh) | 2012-05-23 |
JP5341191B2 (ja) | 2013-11-13 |
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