WO2010140307A1 - プラズマディスプレイパネルの製造方法 - Google Patents
プラズマディスプレイパネルの製造方法 Download PDFInfo
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- WO2010140307A1 WO2010140307A1 PCT/JP2010/003336 JP2010003336W WO2010140307A1 WO 2010140307 A1 WO2010140307 A1 WO 2010140307A1 JP 2010003336 W JP2010003336 W JP 2010003336W WO 2010140307 A1 WO2010140307 A1 WO 2010140307A1
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- temperature
- sealing
- voltage
- gas
- display panel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/24—Manufacture or joining of vessels, leading-in conductors or bases
- H01J9/241—Manufacture or joining of vessels, leading-in conductors or bases the vessel being for a flat panel display
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
- H01J11/10—AC-PDPs with at least one main electrode being out of contact with the plasma
- H01J11/12—AC-PDPs with at least one main electrode being out of contact with the plasma with main electrodes provided on both sides of the discharge space
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
- H01J11/20—Constructional details
- H01J11/52—Means for absorbing or adsorbing the gas mixture, e.g. by gettering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/24—Manufacture or joining of vessels, leading-in conductors or bases
- H01J9/26—Sealing together parts of vessels
- H01J9/261—Sealing together parts of vessels the vessel being for a flat panel display
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/38—Exhausting, degassing, filling, or cleaning vessels
- H01J9/39—Degassing vessels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2211/00—Plasma display panels with alternate current induction of the discharge, e.g. AC-PDPs
- H01J2211/20—Constructional details
- H01J2211/34—Vessels, containers or parts thereof, e.g. substrates
- H01J2211/40—Layers for protecting or enhancing the electron emission, e.g. MgO layers
Definitions
- the present invention relates to a method for manufacturing a plasma display panel (hereinafter, simply referred to as “PDP”), and more particularly to a technique for effectively removing impurities from the protective layer and modifying the protective layer.
- PDP plasma display panel
- Plasma display panels are attracting attention as display devices for applications such as computers and televisions.
- a PDP is a flat display device that uses radiation from a gas discharge, and is relatively easy to achieve high-speed display, high-definition display, large size, thin and light weight, and is used in fields such as video display devices and public information display devices.
- Patent Document 1 There are two types of PDP: DC type (DC type) and AC type (AC type). Of these, the surface discharge type AC type PDP has a particularly high technical potential in terms of life characteristics and enlargement, and has been commercialized.
- a typical conventional AC type PDP has a pair of substrates (a front substrate and a back substrate) arranged opposite to each other with a discharge space interposed therebetween, and a sealing portion including a sealing material such as a low melting point glass is formed around both substrates. And having an internally sealed configuration.
- the front substrate is formed by applying and baking Ag paste on one main surface of the front glass substrate serving as a base to form a plurality of pairs of display electrodes, and so as to cover each display electrode.
- a dielectric glass layer mainly composed of lead oxide is formed by applying and baking glass paste.
- a protective layer containing magnesium oxide (MgO) or a main component thereof is laminated by sputtering or the like.
- the back substrate has a plurality of strip-shaped address (data) electrodes arranged in parallel on one main surface of the back glass substrate by applying and baking Ag paste.
- a dielectric glass layer is sequentially laminated thereon by the same method as described above.
- partition walls are provided in stripes by applying and baking glass paste so as to partition each address electrode.
- a phosphor ink corresponding to any one of red (R), green (G), and blue (B) is applied to each side surface of adjacent barrier ribs and the surface of the dielectric glass layer between them.
- a phosphor layer is formed by baking at about 500 ° C. to remove the resin component in the paste.
- a sealing material obtained by mixing a resin (binder) and a solvent with a sealing material containing lead oxide glass and oxide filler with respect to the periphery of the substrate A paste is applied.
- the sealing material paste is heated by pre-baking to remove organic components in the paste to some extent.
- the surface of the front substrate on which the display electrodes are formed is opposed to the surface of the rear substrate on which the address electrodes are formed, and the both substrates are positioned so that the display electrodes and the address electrodes are orthogonal to each other.
- main baking is performed to form a sealing portion, thereby achieving internal sealing between both substrates.
- the tops of the partition walls of the rear substrate are in contact with the front substrate side, so that discharge cells are partitioned between adjacent partition walls.
- the space between the adjacent barrier ribs is a discharge space, and after exhausting the gas inside both substrates after the sealing step, a rare gas such as Xe-Ne or Xe-He is used as the discharge gas at a predetermined pressure (usually 40 KPa to 80 KPa).
- a gradation expression method for example, a time division display method in a field in which one field of video is divided into a plurality of subfields (SF) is used.
- a discharge is generated in the discharge space.
- the discharge gas is ionized to generate vacuum ultraviolet rays (mainly resonance lines mainly having a wavelength of 147 nm and molecular beams mainly having a wavelength of 173 nm) in the discharge space.
- This vacuum ultraviolet light excites the phosphor layer to emit light, so that visible light is emitted and color display is performed on the entire panel.
- PDPs of various standards exist due to diversification of uses of PDPs.
- SD standard
- HD high-definition
- full HD full high-definition
- the emission luminance can be improved. It has been known.
- the protective layer contains various impurities such as various resins, solvents and solvents contained in the sealing material paste, and carbon impurities and water vapor generated when these impurities are burned off during the pre-baking process or the sealing process. It has the property of adsorbing impurity gases (hereinafter simply referred to as “impurities”) and easily changing in quality, but by using a protective layer material that prevents such adsorption or is difficult to adsorb, It is considered to maintain the secondary electron emission characteristics.
- impurities adsorbing impurity gases
- the protective layer is composed of a composite oxide film using an alkaline earth metal oxide such as SrO, CaO, BaO instead of MgO,
- an alkaline earth metal oxide such as SrO, CaO, BaO instead of MgO
- the protective layer forming process to the sealing process are continuously performed in an air, N 2 , or O 2 atmosphere adjusted to a dry atmosphere to protect impurities such as H 2 O.
- a method for effectively preventing contamination into the layer is shown.
- Patent Document 5 a protective layer made of a composite oxide film using an alkaline earth metal oxide such as SrO, CaO, BaO is formed, and H 2 O, CO, CO 2 in the atmosphere is formed on the protective layer.
- a method is disclosed in which the sealing process and the exhausting process are performed consistently in a vacuum for the purpose of efficiently adsorbing impurities and preventing unnecessary reactions with the protective layer and exhausting the impurity gas in the discharge space efficiently. ing.
- impurities caused by the sealing material paste are gasified by being heated at a high temperature in the pre-baking process and the sealing process, and most of them are exhausted and removed in the exhausting process, but the impurities are still completely removed. It ’s difficult.
- the sealing material paste is heated at a high temperature above a certain temperature, tar is generated due to polymerization of organic components derived from the paste, and it is difficult to remove impurities. It has been revealed by.
- the protective layer made of a composite oxide film of the above alkaline earth metal has good secondary electron emission characteristics, but at present, the protective layer containing MgO exhibits better secondary electron emission characteristics. It's easy to do. Therefore, for the purpose of reducing power consumption, there is a demand for using a MgO-based material as much as possible as the protective layer material.
- An object of the present invention is to provide a method for manufacturing a plasma display panel capable of exhibiting the above with relatively low power consumption drive.
- the present invention provides a paste containing a sealing material around the main surface of one of the back substrate and the front substrate on which a protective layer containing MgO is formed.
- a second temperature lowering step for lowering the temperature of both the substrates from the first temperature to room temperature, and the first temperature lowering step can be performed in a shorter time than the second temperature lowering step.
- the first temperature in the first temperature lowering step can be set to 200 ° C.
- the time related to the first temperature lowering step can be set to 20 minutes to 30 minutes.
- the time of the second temperature lowering step can be set to be 5 times longer than the time of the first temperature lowering step.
- the non-oxidizing gas is preferably N 2 gas or Ar gas.
- the reducing gas is preferably H 2 gas or NH 3 (ammonia) gas.
- the reducing gas in the mixed atmosphere is preferably 0.1% or more and 3% or less as a gas partial pressure in the entire mixed atmosphere.
- the pre-baking maximum temperature may be 10 ° C. or lower than the softening point of the sealing material.
- the maximum temperature for pre-firing can be further lowered by 10 ° C. to 50 ° C. lower than the softening point of the sealing material.
- a sealing material containing a low-melting glass as a component is used as the sealing material, and the temperature is not lower than the glass transition point of the low-melting glass and lower than the softening point of the low-melting glass by 10 ° C. Firing can be performed.
- the glass transition point can be in the range of 336 ° C. or more and 365 ° C. or less.
- the softening point of the sealing material may be 410 ° C. to 450 ° C., and the sealing temperature may be 450 ° C. to 500 ° C.
- sealing material a sealing material containing at least one of cordierite, Al 2 O 3 , and SiO 2 as a filler can be used.
- sealing material a sealing material containing bismuth oxide and cordierite can also be used.
- sealing material containing lead oxide and cordierite can also be used as the sealing material.
- the sealing temperature may be set to a temperature that is 40 ° C. or higher than the softening point temperature of the sealing material.
- the pre-baking step can also be performed in an N 2 atmosphere having a dew point of ⁇ 45 ° C. or lower.
- the pre-baking step can also be performed in an N 2 atmosphere containing O 2 at a partial pressure of 1% or less.
- the pre-baking at the maximum pre-baking temperature can be maintained for 10 minutes to 50 minutes.
- the pre-baking step is preferably performed in an oxidizing atmosphere.
- a sealing temperature increasing step for increasing the temperature of both substrates from room temperature to the sealing temperature
- a sealing temperature maintaining step for maintaining the sealing temperature for a certain time after the sealing temperature increasing step
- the reducing temperature is mixed with the non-oxidizing gas in sequence
- the sealing temperature decreasing step of decreasing the temperature of the both substrates from the sealing temperature to a temperature lower than the softening point of the sealing material. More preferably, it can be carried out in an atmosphere in which 0.1% to 3% of H 2 gas is mixed in N 2 gas or Ar gas.
- an exhaust temperature maintaining step for maintaining the both substrates at a temperature equal to or higher than room temperature and lower than the softening point of the sealing material for a certain period of time;
- the steps can be sequentially performed under a reduced pressure atmosphere.
- the pitch of the barrier ribs adjacent to the main surface of the back substrate is set to 0.16 mm or less, and a plurality of barrier ribs are provided, and a phosphor layer is formed between the adjacent barrier ribs, A discharge gas containing Xe at a partial pressure of 15% or more can be sealed between the two substrates after the exhaust process.
- a plurality of partition walls are formed by setting a pitch of partition walls adjacent to the main surface of the back substrate so that the number of panel pixels is 1920 or more in the horizontal direction and 1080 or more in the vertical direction.
- a phosphor layer may be formed between adjacent barrier ribs, and a discharge gas containing Xe at a partial pressure of 15% or more may be sealed between the two substrates after the exhaust process.
- the present invention also relates to a driving method of a plasma display panel manufactured by the plasma display panel manufacturing method according to any one of the above-described present invention, wherein the plasma display panel is a display composed of scan electrodes and sustain electrodes.
- a plurality of electrode pairs, a plurality of data electrodes, a discharge cell at each of the positions where the display electrode pairs and the data electrodes intersect, and the plurality of display electrode pairs in a plurality of display electrode pair groups Dividing the display electrode pair group into one field period using a plurality of subfields having an address period for generating an address discharge in a discharge cell and a sustain period for generating a sustain discharge in the discharge cell;
- the number of display electrode pair groups is N (N is an integer of 2 or more), and one address operation is performed in the discharge cells of the entire panel.
- the pre-baking step in the pre-baking step, is performed with a temperature lower than the softening point temperature of the sealing material as the maximum temperature.
- the organic component derived from the paste of the sealing material can be left between the two substrates in the low molecular state after the preliminary firing step.
- the temperature of both substrates is lowered to room temperature in two steps.
- the first temperature lowering step the temperature is rapidly decreased from the maximum temperature to the first temperature lower than the binder disappearing temperature and higher than the room temperature as compared with the subsequent second temperature lowering step.
- the organic component derived from the paste of the sealing material remains in a low molecular state and is satisfactorily left between the two substrates. Therefore, together with other impurities, the organic component can be efficiently removed in the exhaust process. it can.
- the organic component is excessively heated and polymerized, tarred, or excessively decomposed at a high temperature and taken into the sealing portion, and even after completion of the PDP, the glass component of the sealing material. The risk of remaining is reduced.
- tar generated from the organic component of the sealant paste has a low vapor pressure and is difficult to remove even in the exhaust process, so it remains between the substrates. For this reason, the tar deteriorates the protective layer containing MgO and causes the discharge voltage of the PDP to increase, but in the present invention, as described above, tar generation is suppressed and organic components are efficiently removed in the exhaust process. Since it can be removed, deterioration of the protective layer of the PDP due to adsorption of impurities can be suppressed.
- the sealing step by performing the sealing step in a non-oxidizing atmosphere or a reducing atmosphere, polymerization of the organic component of the sealing material paste can be prevented, and the organic component can be satisfactorily removed while being in a low molecular state in the exhausting step.
- alteration of the protective layer is suppressed, and when the sealing step is performed in a reducing atmosphere, unnecessary oxidation of the protective layer is prevented, the crystal structure is modified, and the secondary electron emission characteristics are improved.
- the improvement effect can also be expected.
- Such an embodiment of the present invention can exhibit extremely effective effects when applied to a high-definition / ultra-high-definition panel or a large-screen panel.
- FIG. 1 is a cross-sectional perspective view showing a schematic configuration of a PDP in Embodiment 1.
- FIG. FIG. 3 is an electrode array diagram of the PDP in the first embodiment.
- FIG. 2 is a circuit block diagram of the PDP device according to the first embodiment.
- FIG. 3 is a circuit diagram of a scan electrode drive circuit in the PDP device according to the first embodiment.
- FIG. 3 is a circuit diagram of a sustain electrode drive circuit in the PDP device according to the first embodiment.
- FIG. 6 is another electrode arrangement diagram of the PDP in the PDP device according to the first embodiment.
- FIG. 5 is a circuit diagram of another scan electrode driving circuit of the PDP in the PDP device according to the first embodiment.
- FIG. 6 is a diagram for explaining a time chart during driving of the PDP device according to the first embodiment. 6 is a diagram for explaining a setting method of a subfield configuration in the PDP apparatus in the first embodiment.
- FIG. It is a figure which shows the drive voltage waveform applied to each electrode of PDP in the PDP apparatus of Embodiment 1.
- FIG. FIG. 5 is a flowchart for explaining a method of manufacturing a PDP included in the PDP device according to the first embodiment. It is a figure which shows the temperature profile of the temporary baking process of this invention. It is a figure which shows piping structures, such as a sealing apparatus and a gas introduction apparatus. It is a figure which shows the temperature profile of a sealing process, an exhaust process, and a discharge gas introduction process.
- the PDP apparatus 1000 is configured by connecting predetermined drive circuits 111 to 113 to the PDP 1.
- FIG. 1 is a partial perspective view showing a schematic configuration of the PDP 1 and partially shows a peripheral region around the sealing portion around the PDP 1.
- FIG. 2 is a diagram schematically showing the overall configuration of the electrode array in the PDP 1.
- the PDP 1 has a front substrate (front panel) 2 that is a first substrate and a rear substrate (back panel) 9 that is a second substrate arranged so that their inner main surfaces face each other.
- the periphery of both the substrates 2 and 9 is sealed with the sealing portion 16.
- a front substrate glass 3 serving as a substrate of the front substrate 2 has a pair of display electrode pairs 6 (scanning electrode 4 and sustaining electrode 5) disposed so as to form a predetermined discharge gap on one main surface thereof. (SC1 and SU1 in FIG. 2 are illustrated), and a plurality of pairs are formed in a stripe shape.
- each display electrode pair 6 includes strip-like transparent electrodes 51 and 41 each made of a conductive metal oxide such as indium tin oxide (ITO), zinc oxide (ZnO), and tin oxide (SnO 2 ) as a transparent conductive material.
- bus lines 52 and 42 made of Ag thick film, Al thin film, Cr / Cu / Cr laminated thin film or the like are laminated. The sheet resistance of the transparent electrodes 51 and 41 is lowered by the bus lines 52 and 42.
- the display electrode pair 6 can also be composed of only a metal material such as Ag. Further, the electrode shape is not limited to a belt shape, and may be configured using a plurality of fine lines or a desired pattern.
- the front substrate glass 3 on which the display electrode pair 6 is disposed is made of lead oxide (PbO), bismuth oxide (Bi 2 O 3 ), phosphorus oxide (PO 4 ), or zinc oxide (ZnO) over the entire main surface.
- a dielectric layer 7 of low melting point glass (thickness of about 30 ⁇ m) as a main component is formed by a screen printing method or the like.
- the dielectric layer 7 has a current limiting function peculiar to the AC type PDP, and is an element that realizes a longer life than the DC type PDP.
- the protective layer 8 is a thin film disposed for the purpose of protecting the dielectric layer 7 from ion bombardment during discharge and reducing the discharge start voltage, and includes MgO having excellent sputter resistance and secondary electron emission coefficient ⁇ . Formed by material. The material has better optical transparency and electrical insulation.
- a rear substrate glass 10 which is a substrate of the rear substrate 9 has a data (address) electrode 11 (in FIG. 1) made of Ag thick film, Al thin film, Cr / Cu / Cr laminated thin film or the like on one main surface.
- D1-D4 in FIG. 2 are arranged in stripes at regular intervals in the y direction with the x direction as the longitudinal direction.
- a dielectric layer 12 is disposed over the entire surface of the back substrate glass 9 so as to enclose each data electrode 11.
- the dielectric layer 12 has the same configuration as the above 7, but in order to function as a visible light reflecting layer, the dielectric layer 12 is mixed so that particles having visible light reflection characteristics such as TiO 2 particles are dispersed in the glass material. May be.
- a grid-shaped barrier rib 13 (combination of barrier rib portions 1231 and 1232) is formed in accordance with the gap between the adjacent data electrodes 11, and thereby discharge cells are partitioned.
- the discharge cells are partitioned by the barrier ribs 13, thereby preventing erroneous discharge and optical crosstalk between adjacent ones.
- the partition wall 13 is not limited to a cross-girder shape, and can be formed in various shapes such as a stripe shape and a honeycomb shape (including those having a deep depth in the thickness direction of the panel).
- Phosphor layers 14 (corresponding to red (R), green (G), and blue (B) for color display on the side surfaces of two adjacent barrier ribs 13 and the surface of the dielectric layer 12 therebetween. 14 (R), 14 (G), or 14 (B)) is formed.
- the dielectric layer 12 is not essential, and the data electrode 11 may be directly covered with the phosphor layer 14.
- the front substrate 2 and the rear substrate 9 are aligned so that the respective surfaces on which the display electrode pair 6 and the data electrode 11 are formed face each other and the longitudinal directions of the display electrode pair 6 and the data electrode 11 intersect each other.
- the outer peripheral edge portions of both substrates 2 and 9 are airtightly joined (sealed) by a sealing portion 16 containing a predetermined sealing material.
- a discharge gas composed of an inert gas component containing He, Xe, Ne or the like (here, Ne—Xe-based gas containing Xe at 15 volume% or more). ) Is sealed at a predetermined pressure.
- the discharge space 15 is a space between the adjacent barrier ribs 13, and is aligned with each position where a pair of adjacent display electrode pairs 6 and one data electrode 11 intersect with each other across the discharge space 15 to discharge cells for image display. (Also referred to as “sub-pixel”).
- One pixel is composed of three discharge cells corresponding to adjacent RGB colors.
- the 2160 display electrode pairs 6 including the scan electrodes SC1 to SC2160 and the sustain electrodes SU1 to SU2160 are divided into a plurality of display electrode pair groups.
- the method of determining the number N of display electrode pair groups will be described later.
- 1080 scan electrodes SC1 to SC1080 and 1080 sustain electrodes SU1 to SU1080 belong to the first display electrode pair group
- 1080 scan electrodes SC1081 to SC2160 and 1080 sustain electrodes SU1081 to SU2160 are the second. It belongs to the display electrode pair group.
- FIG. 3 is a circuit block diagram of the PDP apparatus 1000.
- the PDP apparatus 1000 supplies necessary power to the image signal processing circuit 110, the data electrode drive circuit 113, the scan electrode drive circuit 111, the sustain electrode drive circuit 112, the timing generation circuit 114, and each circuit block in addition to the above PDP1. It is composed of a power supply circuit (not shown) and the like. Of these, scan electrodes SC1 to SC2160 are electrically connected to drive circuit 111, sustain electrodes SU1 to SU2160 are electrically connected to drive circuit 112, and data electrodes D1 to Dm are electrically connected to drive circuit 113, respectively.
- the image signal processing circuit 110 converts an image signal input from the outside into image data indicating light emission / non-light emission for each subfield.
- the data electrode drive circuit 113 includes m switches for applying a voltage Vd or a voltage 0 (V) to each of the m data electrodes D1 to Dm.
- the image data output from the image signal processing circuit 110 is converted into address pulses corresponding to the data electrodes D1 to Dm and applied to the data electrodes D1 to Dm.
- the timing generation circuit 114 generates various timing signals for controlling the operation of each circuit based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to each circuit.
- Scan electrode drive circuit 111 drives scan electrodes SC1 to SC1080 belonging to the first display electrode pair group and scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group based on the timing signal.
- Sustain electrode drive circuit 112 drives sustain electrodes SU1 to SU1080 belonging to the first display electrode pair group and sustain electrodes SU1081 to SU2160 belonging to the second display electrode pair group based on the timing signal.
- FIG. 4 is a circuit diagram of the scan electrode driving circuit 111.
- Scan electrode driving circuit 111 includes scan electrode side sustain pulse generation circuit 500 (hereinafter simply referred to as “sustain pulse generation circuit 500”), ramp waveform generation circuit 600, scan pulse generation circuit 700a, scan pulse generation circuit 700b, scan The electrode side switch circuit 750a (hereinafter simply referred to as “switch circuit 750a”), the scan electrode side switch circuit 750b (hereinafter simply referred to as “switch circuit 750b”), and the like.
- Sustain pulse generation circuit 500 includes power recovery unit 510 and voltage clamp unit 550, and scan electrodes SC1 to SC1080 belonging to the first display electrode pair group or scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group. A sustain pulse to be applied to is generated.
- the power recovery unit 510 includes a power recovery capacitor C510, switching elements Q510 and Q520, backflow prevention diodes D510 and D520, and resonance inductors L510 and L520, and an interelectrode capacitance between each pair of display electrodes. And the inductor L510 or the inductor L520 are LC-resonated to rise and fall the sustain pulse. When the sustain pulse rises, the charge stored in the power recovery capacitor C510 is transferred to the interelectrode capacitance via the switching element Q510, the diode D510, and the inductor L510.
- the power recovery unit 510 rises and falls the sustain pulse by LC resonance without being supplied with power from the power source, and thus the power consumption is ideally “0”.
- the power recovery capacitor C510 has a sufficiently large capacity compared to the interelectrode capacity, and is charged to about Vs / 2, which is half the voltage Vs, so as to serve as a power source for the power recovery unit 510.
- the voltage clamp unit 550 includes switching elements Q550 and Q560. Then, by turning on switching element Q550, the output voltage of sustain pulse generating circuit 500 (the voltage at node C in FIG. 4) is clamped to voltage Vs. Further, by turning on switching element Q560, the output voltage of sustain pulse generating circuit 500 is clamped to voltage 0 (V). Therefore, the impedance at the time of voltage application by the voltage clamp unit 550 is small, and a large discharge current due to the sustain discharge can be flowed stably.
- sustain pulse generating circuit 500 generates sustain pulses by controlling switching elements Q510, Q520, Q550, and Q560.
- these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.
- FIG. 4 shows a circuit configuration using an IGBT as a switching element.
- IGBTs IGBTs
- a diode D550 is connected in parallel to the switching element Q550
- a diode D560 is connected in parallel to the switching element Q560.
- a diode may be connected in parallel to each of switching element Q510 and switching element Q520 in order to protect the IGBT.
- the switching element Q590 is a separation switch, and when the voltage at the node C rises above Vs like Vi2 during the initialization period, the current flows from the ramp waveform generation circuit 600, which will be described later, to the voltage Vs via the diode D550. It is provided to prevent backflow.
- the ramp waveform generation circuit 600 includes two Miller integration circuits 610 and 620.
- Miller integrating circuit 610 gently increases the output voltage of ramp waveform generating circuit 600 (the voltage at node C in FIG. 4) toward voltage Vt.
- Miller integrating circuit 620 gently increases the output voltage of ramp waveform generating circuit 600 toward voltage Vr.
- Scan pulse generation circuit 700a includes power supply E710a of voltage Vp, Miller integration circuit 710a, switching elements Q710H1 to Q710H1080, and switching elements Q710L1 to Q710L1080.
- Miller integrating circuit 710a gently decreases the voltage on the low voltage side of power supply E 710a (the voltage at node A in FIG. 4) toward voltage Va. Further, the voltage on the low voltage side of the power supply E 710a is clamped to the voltage Va.
- Each of switching elements Q710L1 to Q710L1080 applies a low-voltage side voltage of power supply E710a to the corresponding scan electrode, and each of switching elements Q710H1 to Q710H1080 applies a high-voltage side voltage of power supply E710a to the corresponding scan electrode.
- Scan pulse generation circuit 700b has the same configuration as scan pulse generation circuit 700a, and includes power supply E 710b having voltage Vp, Miller integration circuit 710b, switching elements Q710H1081 to Q710H2160, and switching elements Q710L1081 to Q710L2160. Then, the high voltage side voltage or the low voltage side voltage of the power supply E 710b is applied to each of the scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group.
- Switch circuit 750a has switching element Q760a, and electrically connects or disconnects sustain pulse generation circuit 500, ramp waveform generation circuit 600 and scan pulse generation circuit 700a.
- Switch circuit 750b has switching element Q760b, and electrically connects or disconnects sustain pulse generating circuit 500, ramp waveform generating circuit 600 and scan pulse generating circuit 700b.
- the drive waveforms shown in FIG. 10 to be described later are applied to the scan electrodes SC1 to SC1080 as the first display electrode pair group and the scan electrodes SC1081 to SC2160 as the second display electrode pair group. Can be applied.
- the switching elements Q760a and Q760b of the switch circuits 750a and 750b are turned on, the switching elements Q710H1 to Q710H2160 of the scan pulse generation circuits 700a and 700b are turned on, and the Q710L1 to Q710L2160 are turned off.
- a voltage obtained by adding the voltage Vp to the output from the generation circuit 600 can be applied simultaneously to the scan electrodes SC1 to SC2160.
- the switching elements Q760a and Q760b of the switch circuits 750a and 750b are turned off, the switching elements Q710H1 to Q710H2160 of the scan pulse generation circuits 700a and 700b are turned off, the Q710L1 to Q710L2160 are turned on, and then the Miller integrating circuits 710a and 710b By turning on, a downward ramp voltage up to voltage Vi4 can be applied to scan electrodes SC1 to SC2160 all at once. Thereafter, by turning off Q710L1 to Q710L2160 and turning on switching elements Q710H1 to Q710H2160, voltage Vc can be applied simultaneously to scan electrodes SC1 to SC2160.
- the switching elements Q710Hn and Q710Ln are turned on / off in a state where the switching element Q760a of the switch circuit 750a is turned off and the Miller integrating circuit 710a is turned on.
- a scan pulse can be applied. This is because the scan pulse can be applied to the corresponding scan electrode SCn in the same manner during the address period of the second display electrode pair group.
- the switching element Q760a of the switch circuit 750a is turned on, the switching elements Q710H1 to Q710H1080 of the scan pulse generation circuit 700a are turned off, and the switching elements Q710L1 to Q710L1080 are turned on.
- the output of the generation circuit 500 can be applied to the first display electrode pair groups SC1 to SC1080.
- the switching element Q760b of the switch circuit 750b is turned off, and the output of the sustain pulse generating circuit 500 is the scan electrode SC1081 belonging to the second display electrode pair group. No effect on SC2160. Therefore, the above-described address operation can be performed on scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group without depending on the output of sustain pulse generating circuit 500.
- the switching element Q760a of the switch circuit 750a is turned off. There is no effect on scan electrodes SC1 to SC1080 belonging to one display electrode pair group.
- switching element Q760a of switch circuit 750a is turned on, switching elements Q710H1 to Q710H1080 of scan pulse generating circuit 700a are turned off, and switching elements Q710L1 to Q710L1080 are turned on.
- the output from the ramp waveform generating circuit 600 is applied to the scan electrodes SC1 to SC1080.
- the second display electrode pair group is in the writing period (more precisely, the period in which the writing operation is interrupted), and the switching element Q760b of the switch circuit 750b is turned off.
- the output voltage has no effect on the scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group.
- the switching element Q760b Since the switching element Q760b is turned off, the output voltage of the ramp waveform generation circuit 600 is not applied to the scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group. It does not affect.
- the scan electrode drive circuit 111 is not affected by the applied voltage of the other display electrode pair group by turning off the switch circuits 750a and 750b in the period of applying the downward ramp voltage and the address period. A desired voltage can be applied.
- FIG. 5 is a circuit diagram of the sustain electrode driving circuit 112.
- Sustain electrode drive circuit 112 includes sustain electrode side sustain pulse generation circuit 800 (hereinafter simply referred to as “sustain pulse generation circuit 800”), constant voltage generation circuit 900a, constant voltage generation circuit 900b, and sustain electrode side switch circuit 100a (
- the storage electrode side switch circuit 100b (hereinafter simply referred to as “switch circuit 100b”) is provided.
- Sustain pulse generation circuit 800 includes power recovery unit 810 and voltage clamp unit 850, and sustain electrodes SU1 to SU1080 belonging to the first display electrode pair group or sustain electrodes SU1081 to SU2160 belonging to the second display electrode pair group. A sustain pulse to be applied to is generated.
- the power recovery unit 810 includes a power recovery capacitor C810, switching elements Q810 and Q820, backflow prevention diodes D810 and D820, and resonance inductors L810 and L820.
- the sustaining pulse rises and falls by causing LC resonance between the interelectrode capacitance between the display electrodes and the inductor L810 or the inductor L820.
- Voltage clamp unit 850 includes switching elements Q850 and Q860. Similarly to voltage clamp unit 550, output voltage (voltage at node D in FIG. 5) of sustain pulse generation circuit 800 is set to voltage Vs or voltage 0 (V). Clamp to
- the constant voltage generation circuit 900a includes switching elements Q910a, Q920a, Q930a, and Q940a.
- Switching element Q930a and switching element Q940a form a bidirectional switch connected in series so that the directions of currents to be controlled are opposite to each other.
- a constant voltage Ve1 is applied to sustain electrodes SU1 to SU1080 belonging to the first display electrode pair group via switching elements Q910a, Q930a, and Q940a, and constant voltage is applied to sustain electrodes SU1 to SU1080 via switching elements Q920a, Q930a, and Q940a.
- a voltage Ve2 is applied.
- the constant voltage generation circuit 900b has the same configuration as the constant voltage generation circuit 900a, and includes switching elements Q910b, Q920b, Q930b, and Q940b. Then, the constant voltage Ve1 or the constant voltage Ve2 is applied to the sustain electrodes SU1081 to SU2160 belonging to the second display electrode pair group.
- FIG. 5 shows a circuit configuration using MOSFETs and IGBTs.
- IGBTs are used for the switching elements Q940a and Q940b, and a diode D940a is connected in parallel to the switching element Q940a in order to secure a current path in a direction opposite to the direction of the current to be controlled, and the diode D940b in parallel to the switching element Q940b. Is connected.
- the switching element Q940a is provided to allow current to flow from the sustain electrodes SU1 to SU1080 toward the power sources of the voltages Ve1 and Ve2. However, the switching element Q940a supplies current only from the power sources of the voltages Ve1 and Ve2 to the sustain electrodes SU1 to SU1080. When flowing, switching element Q940a may be omitted. The same applies to switching element Q940b.
- a capacitor C930a is connected between the gate and drain of the switching element Q930a
- a capacitor C930b is connected between the gate and drain of the switching element Q930b.
- These capacitors C930a and C930b are provided in order to moderate the rise when the voltages Ve1 and Ve2 are applied, but are not necessarily required. In particular, when the voltage Ve1 and the voltage Ve2 are changed stepwise, these capacitors C930a and C930b are unnecessary.
- the switch circuit 100a includes switching elements Q101a and Q102a, and the switching element Q101a and the switching element Q102a form a bidirectional switch connected in series so that the directions of currents to be controlled are opposite to each other. Then, sustain pulse generating circuit 800 and sustain electrodes SU1 to SU1080 belonging to the first display electrode pair group are electrically connected or separated.
- the switch circuit 100b has switching elements Q101b and Q102b, and forms a bidirectional switch connected in series so that directions of currents to be controlled by the switching element Q101b and the switching element Q102b are opposite to each other. Then, sustain pulse generating circuit 800 and sustain electrodes SU1081 to SU2160 belonging to the second display electrode pair group are electrically connected or separated.
- a drive waveform shown in FIG. 10 described later is applied to sustain electrodes SU1 to SU1080 as a first display electrode pair group and scan electrodes SU1081 to SU2160 as a second display electrode pair group. Can be applied. The operation will be specifically described below.
- the switching elements Q101a, Q101b, Q102a, and Q102b of the switch circuits 100a and 100b are turned on and the output of the sustain pulse generation circuit 800 is set to 0 (V) during the period in which the upward ramp waveform is applied to the scan electrodes SC1 to SC2160. ), 0 (V) can be applied to the sustain electrodes SU1 to SU2160 all at once.
- 0 (V) can be applied to the sustain electrodes SU1 to SU2160 all at once.
- switching elements Q101a, Q101b, Q102a, Q102b of switch circuits 100a, 100b are turned off, and constant voltage generation circuits 900a, 900b are turned off.
- voltage Ve1 can be applied to sustain electrodes SU1 to SU2160 all at once.
- the switching element Q910a, Q910b is turned off and Q920a, Q920b is turned on to output the voltage Ve2.
- the switching elements Q101a and Q102a of the switch circuit 100a are turned on, the switching elements Q930a and Q940a of the constant voltage generation circuit 900a are turned off, and the sustain pulse generation circuit 800 outputs A pulse can be applied to the sustain electrodes SU1 to SU1080.
- the second display electrode pair group is in the address period, but since the switching elements Q101b and Q102b of the switch circuit 100b are turned off, the voltage output from the sustain pulse generation circuit 800 has no effect on the sustain electrodes SU1081 to SU2160. do not do.
- the second display electrode pair group is the sustain period and the first display electrode pair group is the address period.
- switching elements Q101b and Q102b of switch circuit 100b are turned on, switching elements Q930b and Q940b of constant voltage generation circuit 900b are turned off, and a sustain pulse output from sustain pulse generation circuit 800 is applied to sustain electrodes SU1081 to SU2160. Can do.
- the first display electrode pair group is in the address period, but since the switching elements Q101a and Q102a of the switch circuit 100a are turned off, the voltage output from the sustain pulse generation circuit 800 does not affect the sustain electrodes SU1 to SU1080. do not do.
- the sustain electrodes SU1 to SU1080 belonging to the subsequent first display electrode pair group output the potential 0 (V) from the sustain pulse generation circuit 800 during the erasing period, and during the rest period, the switching elements Q101a, By turning off Q102a and turning on switching elements Q910a, Q930a, and Q940a of constant voltage generating circuit 900a, voltage Ve1 can be applied to sustain electrodes SU1 through SU1080.
- voltage Ve2 can be applied to sustain electrodes SU1 to SU1080 by turning off switching element Q910a and turning on Q920a of constant voltage generating circuit 900a.
- the sustain electrodes SU1081 to SU2160 belonging to the second display electrode pair group are not affected even in the first erase period, the rest period, and the second erase period.
- the sustain electrode SU1081 to SU2160 belonging to the second display electrode pair group are in the erasing period and the rest period, and the sustain electrodes SU1 to SU1080 belonging to the first display electrode pair group are in the address period, the sustain electrode SU1081 is similarly applied.
- the voltage applied to SU2160 has no effect on sustain electrodes SU1 to SU1080.
- the sustain electrode drive circuit 112 can apply a desired voltage without being affected by the applied voltage of the other display electrode pair group by turning off the switch circuits 100a and 100b in the address period. it can.
- the sustain pulse generation circuit, the ramp waveform generation circuit, and the like shown in this embodiment are merely examples of specific examples. Other circuit configurations may be used as long as the same drive voltage waveform can be generated.
- the power recovery unit 510 illustrated in FIG. 4 moves the charge of the capacitor C510 to the interelectrode capacitance via the switching element Q510, the diode D510, the inductor L510, and the switching element Q590 at the rising edge of the sustain pulse, and the falling of the sustain pulse
- the circuit configuration sometimes returns the charge of the interelectrode capacitance to the capacitor C510 via the inductor L520, the diode D520, and the switching element Q520.
- connection of one terminal of the inductor L510 is changed from the source of the switching element Q590 to the node C, and the charge of the capacitor C510 is moved to the interelectrode capacitance via the switching element Q510, the diode D510 and the inductor L510 at the rising edge of the sustain pulse.
- a circuit configuration may be adopted. Further, a circuit configuration in which the inductor L510 and the inductor L520 are shared by one inductor may be employed.
- FIG. 4 shows a circuit configuration including two Miller integration circuits 610 and 620, the circuit configuration includes one voltage switching circuit and one Miller integration circuit. Also good.
- the capacitor C510 of the power recovery unit 510 shown in FIG. 4 is deleted, all of the power recovery unit 810 shown in FIG. 5 is deleted, and the connection point between the node D of FIG. 5 and the switching elements Q510 and Q520 of FIG. May be connected to each other.
- the capacitor C810 of the power recovery unit 810 shown in FIG. 5 is deleted, and the connection point and the node C of the switching elements Q810 and Q820 of FIG. It may be a circuit configuration.
- the first display electrode pair group is a pair of display electrodes SC1 to SC1080 and sustain electrodes SU1 to SU1080, and a pair of display electrodes SC2161 to SC3240 and sustain electrodes SU2161 to SU3240.
- the display electrode pair group may be a pair of display electrodes SC1081 to SC2160 and sustain electrodes SU1081 to SU2160, and a pair of display electrodes SC3241 to SC4320 and sustain electrodes SU3241 to SU4320.
- data electrodes D1 to Dm intersect only the display electrode pairs of the scan electrodes SC1 to SC2160 and the sustain electrodes SU1 to SU2160, no matter what operation the scan electrodes SC2161 to SC4320 and the sustain electrodes SU2161 to SU4320 perform. Not affected. Similarly, data electrodes Dm + 1 to D2m are not affected at all by scan electrodes SC1 to SC2160 and sustain electrodes SU1 to SU2160.
- the PDP 101 shown in FIG. 6 can be regarded as a configuration that operates independently at the top and bottom, even if the number of display electrode pairs is double, the same is true if each data electrode is divided into two at the top and bottom of the panel. Is possible.
- FIG. 7 is a circuit diagram of a scan electrode driving circuit 431 for driving the scan electrodes of the PDP 101 of FIG.
- the difference from scan electrode driving circuit 111 is that switching elements Q710H2161 to Q710H3240 and Q710L2161 to Q710L3240 for driving scan electrodes SC2161 to SC3240 are added to scan pulse generating circuit 700e as compared to scan pulse generating circuit 700a.
- scan pulse generating circuit 700f is additionally provided with switching elements Q710H3241 to Q710H4320 and Q710L3241 to Q710L4320 for driving scan electrodes SC3241 to SC4320.
- the operation pulse generation circuit 500 and the ramp waveform generation circuit 600 are the same.
- an address pulse can be applied to SC 2161 simultaneously with an address pulse applied to scan electrode SC1 in the address period of the first display electrode pair group.
- the sustain electrode drive circuit may have the same configuration (not shown). That is, sustain electrodes SU2161 to SU3240 may be additionally connected to sustain electrode drive circuits connected to sustain electrodes SU1 to SU1080. Similarly, sustain electrodes SU3241 to SU4320 are connected to circuits connected to sustain electrodes SU1081 to SU2160. May be additionally connected.
- ⁇ PDP driving method> an example of a method for driving the PDP apparatus 1000 having the above configuration will be described.
- the description of the driving method is also described in, for example, Japanese Patent Application No. 2008-116719.
- the timing of the scan pulse and the address pulse is set so that the address operation is continuously performed except for the initialization period.
- the maximum number of subfields (SF) can be set within one field period.
- the start time of the subfield of each display electrode pair group is set so that the write periods of two or more display electrode pair groups do not overlap in time among the N display electrode pair groups.
- the setting is shifted.
- Tw the time required to perform one address operation over all discharge cells of the entire PDP 1
- Tw the time of the sustain period of each subfield in each display electrode pair group
- each display electrode pair group is subjected to a write operation continuously over N groups, excluding the initialization period, within the entire time of one field.
- Write period can be assigned.
- the driving method disclosed in Patent Document 4 merely shifts the start time of the subfields so that the writing periods of two or more blocks do not overlap in time, and a sufficient number of subfields is always ensured. I can't say I can.
- SF1 is written to the first group. From time t2 to time t3, SF1 is written to the second group. From time tN to time tN + 1, SF1 is written to the Nth group. In this way, SF1 is written at a constant time Tw / N (time t1 to time tN + 1).
- SF3 is written at a fixed time Tw / N (time t2N + 1 to time t3N + 1).
- the writing of the Kth subfield SFK is also performed at a fixed time Tw / N (time t (K ⁇ 1) N + 1 to time tKN + 1).
- the time for performing one write operation is Tw / N
- the time length of one subfield is a fixed time Tw, so that it is maintained in one subfield.
- the maximum number of subfields can be set within one field period.
- the writing operation can be continuously performed in any one of the display electrode pair groups in the period excluding the initialization period and the erasing period of each subfield.
- FIG. 9 is a diagram illustrating the setting of the subfield of the driving method. 9A to 9D, the vertical axis represents scan electrodes SC1 to SC2160, and the horizontal axis represents time. The timing for performing the write operation is indicated by a solid line, and the timing of the sustain period and the erase period described later is indicated by hatching.
- the time for one field period is set to 16.7 ms, but the present invention is not limited to this.
- an initializing period for generating initializing discharges simultaneously in all the discharge cells is provided.
- the time required for the initialization period is set to 500 ⁇ s.
- the time Tw required to sequentially apply the scan pulses to the scan electrodes SC1 to SC2160 is estimated. At this time, it is desirable to apply the scan pulse as short as possible and continuously as much as possible so that the writing operation is continuously performed.
- the number of display electrode pair groups is determined based on the required number of sustain pulses.
- “60”, “44”, “30”, “18”, “11”, “6”, “3”, “2”, “1”, “1” in each subfield. ”Is applied. If the sustain pulse period is 10 ⁇ s, the maximum time Ts required to apply the sustain pulse is 10 ⁇ 60 600 ⁇ s.
- the number N of display electrode pair groups is an inequality (2) obtained by modifying the inequality (1).
- N ⁇ Tw / (Tw ⁇ Ts) Can be determined based on That is, Ts must not exceed Tw (N ⁇ 1) / N.
- the display electrode pairs are divided into two display electrode pair groups as shown in FIG. Then, as shown in FIG. 9D, a sustain period in which a sustain pulse is applied is provided after writing of the scan electrodes belonging to each group. Although it is necessary to provide an erasing period subsequent to the end of the sustaining period of each subfield, in FIG. 9D, both the sustaining period and the erasing period are indicated by hatched hatching from upper right to lower left.
- the erasing period is ignored, but it is desirable to set so that no writing operation is performed when any of the display electrode pair groups is in the erasing period. This is not only for erasing the wall voltage in the erasing period, but also for adjusting the wall voltage on the data electrode in preparation for the writing operation in the next writing period, so the voltage of the data electrode is fixed in the erasing period. It is desirable to keep it.
- FIG. 10 is a diagram illustrating an example of a drive voltage waveform applied to each electrode of the PDP 1.
- an initializing period for generating an initializing discharge in each discharge cell is provided at the beginning of one field. Further, after the sustain period of each subfield of each display electrode pair group, there is provided an erase period for generating an erase discharge for the discharge cells discharged in the sustain period.
- FIG. 10 shows the initialization period, the writing periods of SF1 to SF2 and SF3 for the first display electrode pair group, and SF1 to SF2 for the second display electrode pair group.
- the initialization period will be explained.
- voltage 0 (V) is applied to data electrodes D1 to Dm and sustain electrodes SU1 to SU2160, respectively, and scan waveform SC1 to SC2160 has a ramp waveform voltage that gradually increases from voltage Vi1 to voltage Vi2. Apply. While this ramp waveform voltage rises, a weak initializing discharge is generated between scan electrodes SC1 to SC2160, sustain electrodes SU1 to SU2160, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SC2160, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SU2160.
- the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like. Note that Vd may be applied to the data electrodes D1 to Dm during this period.
- a positive constant voltage Ve1 is applied to sustain electrodes SU1 to SU2160, and a ramp waveform voltage that gently decreases from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SC2160.
- a weak initializing discharge is generated between scan electrodes SC1 to SC2160, sustain electrodes SU1 to SU2160, and data electrodes D1 to Dm.
- the negative wall voltage on scan electrodes SC1 to SC2160 and the positive wall voltage on sustain electrodes SU1 to SU2160 are weakened, and the positive wall voltage on data electrodes D1 to Dm is adjusted to a value suitable for the write operation.
- voltage Vc is applied to scan electrodes SC1 to SC2160.
- the positive constant voltage Ve2 is applied to the sustain electrodes SU1 to SU1080.
- a scan pulse having a negative voltage Va is applied to the scan electrode SC1
- the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the difference between the externally applied voltages (Vd ⁇ Va).
- the discharge start voltage is exceeded.
- a discharge starts between data electrode Dk and scan electrode SC1 progresses to a discharge between sustain electrode SU1 and scan electrode SC1, and an address discharge is generated.
- a positive wall voltage is accumulated on scan electrode SC1
- a negative wall voltage is accumulated on sustain electrode SU1
- a negative wall voltage is also accumulated on data electrode Dk.
- an address operation is performed in which an address discharge is generated in the discharge cells to be lit in the first row and the wall voltage is accumulated on each electrode.
- the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so the address discharge does not occur.
- a scan pulse is applied to the scan electrode SC2 in the second row, and an address pulse is applied to the data electrode Dk corresponding to the discharge cell to emit light in the second row. Then, an address discharge occurs in the discharge cells in the second row to which the scan pulse and the address pulse are simultaneously applied, and an address operation is performed.
- Voltage Vi1 is applied to scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group.
- a constant voltage Ve2 is applied to sustain electrodes SU1081 to SU2160.
- the scan electrodes SC1081 to SC2160 are held as high as possible within a range where no discharge occurs, so that the wall charge can be suppressed from decreasing, and a stable address operation can be performed in the subsequent address period. Can do.
- the voltage applied to each electrode belonging to the second display electrode pair group is not limited to the above, and another voltage in a range where no discharge is generated may be applied.
- the positive constant voltage Ve2 is continuously applied to the sustain electrodes SU1081 to SU2160. Then, a scan pulse is applied to scan electrode SC1081, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, an address discharge occurs between data electrode Dk and scan electrode SC1081, and between sustain electrode SU1081 and scan electrode SC1081. Next, a scan pulse is applied to scan electrode SC1082, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, an address discharge is generated in the discharge cells in the 1082th row to which the scan pulse and the address pulse are simultaneously applied.
- the above address operation is repeated until reaching the discharge cell in the 2160th row, and an address discharge is selectively generated in the discharge cells to be lit to form wall charges.
- the sustain period of SF1 is applied to the first display electrode pair group, and “60” sustain pulses are alternately applied to scan electrodes SC1 to SC1080 and sustain electrodes SU1 to SU1080 belonging to the first display electrode pair group. This is applied to cause the discharge cell that has performed the address discharge to emit light.
- the sustain pulses applied alternately to the display electrode pairs are sustain pulses having a timing at which the scan electrodes SC1 to SC1080 and the sustain electrodes SU1 to SU1080 are simultaneously at a high potential. That is, when positive voltage Vs is applied to scan electrodes SC1 to SC1080 and voltage 0 (V) is applied to sustain electrodes SU1 to SU1080, the voltage of scan electrodes SC1 to SC1080 is first changed from voltage 0 (V) to voltage. The voltage is increased toward Vs, and then the voltage of sustain electrodes SU1 to SU1080 is decreased from voltage Vs toward voltage 0 (V).
- the sustain pulse so that the scan electrodes SC1 to SC1080 and the sustain electrodes SU1 to SU1080 have a high potential at the same time, the scan electrodes can be stabilized without being affected by the write pulse applied to the data electrodes.
- the sustained discharge can be continued. The reason will be described below.
- the first erasing period a ramp waveform voltage rising toward the voltage Vr is applied to the scan electrodes SC1 to SC1080, and the positive wall voltage on the data electrode Dk is left, and the walls on the scan electrode SCi and the sustain electrode SUi.
- the voltage is being erased.
- the erasing period is not only for erasing the wall voltage but also for adjusting the wall voltage on the data electrode in preparation for the writing operation in the next writing period, so it is desirable to fix the voltage of the data electrode. Therefore, in the driving voltage waveform in the driving method, the writing operation of the second display electrode pair group is stopped in the erasing period of the first display electrode pair group.
- the first display electrode pair group is in the second half of the erase period, and after applying a constant voltage Ve1 to the sustain electrodes SU1 to SU1080, a ramp waveform voltage that decreases toward the voltage Vi4 is applied to the scan electrodes SC1 to SC1080.
- the wall voltage on the data electrode is adjusted in preparation for an address operation in the next address period.
- an address period starts and the address operation starts from scan electrode SC1.
- the constant voltage Ve2 is continuously applied to the sustain electrodes SU1 to SU1080. Then, scan pulses are sequentially applied to scan electrodes SC1 to SC1080 in the same manner as the address period of SF1, and an address pulse is applied to data electrode Dk to perform an address operation in the discharge cells in the first to 1080th rows.
- the sustain pulse applied alternately to the display electrode pair is a sustain pulse having a timing at which the scan electrodes SC1081 to SC2160 and the sustain electrodes SU1081 to SU2160 simultaneously become high potentials.
- a ramp waveform voltage rising toward voltage Vr is applied to scan electrodes SC1081 to SC2160, and the positive wall voltage on data electrode Dk is left, and the walls on scan electrode SCi and sustain electrode SUi are left.
- the voltage is being erased.
- the address operation of the first display electrode pair group is stopped in the erasing period of the second display electrode pair group.
- the second display electrode pair group is in the latter erasing period, and after applying a constant voltage Ve1 to the sustain electrodes SU1081 to SU2160, a ramp waveform voltage that decreases toward the voltage Vi4 is applied to the scan electrodes SC1081 to SC2160.
- the wall voltage on the data electrode is adjusted in preparation for an address operation in the next address period.
- an address period starts and the address operation starts from scan electrode SC1.
- the SF2 address period for the second display electrode pair group the SF3 address period for the first display electrode pair group,..., The SF10 address period for the second display electrode pair group, and so on.
- one field ends after the sustain period and erase period of SF10 for the second display electrode pair group.
- the timing of the scan pulse and the address pulse is set so that the address operation is continuously performed in any one of the display electrode pair groups after the initialization period.
- ten subfields can be set within one field period.
- the number of subfields is the maximum number that can be set within one field period in the present embodiment.
- one field ends with the sustain period and the erase period for the second display electrode pair group. Therefore, the driving time can be shortened by arranging the subfield having the smallest luminance weight in the last subfield.
- the voltage Vi1 is 150 (V), the voltage Vi2 is 400 (V), the voltage Vi3 is 200 (V), the voltage Vi4 is ⁇ 150 (V), the voltage Vc is ⁇ 10 (V), and the voltage Vb is 150 (V), voltage Va is -160 (V), voltage Vs is 200 (V), voltage Vr is 200 (V), voltage Ve1 is 140 (V), voltage Ve2 is 150 (V), and voltage Vd is 60 (V).
- the gradient of the upward ramp waveform voltage applied to scan electrodes SC1 to SC2160 is 10 (V / ⁇ s), and the gradient of the downward ramp waveform voltage is ⁇ 2 (V / ⁇ s).
- these voltage values and gradients are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the PDP and the specifications of the PDP device.
- FIG. 9 illustrates an example of a subfield configuration in which the subfield phases of the first display electrode pair group and the second display electrode pair group are shifted in all subfields.
- the application of the present invention is not limited to the above-described subfield configuration.
- the present invention is a subfield configuration including several subfields of an address / maintenance separation system in which the phases of the sustain periods for all the discharge cells are aligned. Can also be applied.
- the protective layer is required to maintain and exhibit good secondary electron emission characteristics inside the product over the period of use after the product is completed. This is important from the viewpoint of lowering the drive voltage when the Xe partial pressure of the discharge gas is increased in order to improve the efficiency of the PDP.
- a PDP having a high-definition or ultra-high-definition cell structure that exceeds the resolution of full HD, such as the PDP 1 mentioned as an example, and a large-screen PDP with many scanning lines an increase in power consumption is suppressed.
- the front substrate 2 and the rear substrate 9 are heated and sealed in a mixed atmosphere of a non-oxidizing gas and a reducing gas.
- a mixed atmosphere excluding oxygen
- organic components such as a binder and a solvent contained in a sealing material paste that is a precursor material of the sealing portion 16 are oxidized and polymerized during the heating to discharge space. 15 is prevented from remaining.
- the organic component is maintained in a low molecular state and is efficiently exhausted and removed from the inside of the panel in a later exhaust process. This prevents the organic component from adsorbing as an impurity gas to the protective layer 8 and deteriorating the organic component, thereby impairing the secondary electron emission characteristics.
- Such an effect of the present invention is considered to be obtained more efficiently as the PDP becomes higher in definition and ultra-high in definition.
- the surface area of the discharge cell facing the discharge space is relatively large, and the gas in the discharge space does not easily flow.
- a relatively large amount of various organic components contained in the constituent elements of the PDP, such as phosphors and partition materials can adhere to the protective layer 8.
- the surface area of a cell in contact with a gas in the discharge space is increased about 2.4 times compared to a 42-inch full HD panel. Accordingly, it is considered that impurities are more likely to adhere to the protective layer by the increased surface integration as the cell is miniaturized. And the effect of this invention is exhibited effectively in proportion to the increase in such a surface area.
- the present invention by applying the present invention to a PDP having a particularly fine cell structure, it is possible to appropriately prevent alteration of the protective layer due to adhesion of impurities and maintain secondary electron emission characteristics in good quality. As a result, the driving voltage of the PDP 1 can be favorably reduced.
- the PDP having a discharge cell having a deep honeycomb rib structure in which the surface area facing the discharge space is relatively large and the gas is likely to stay is excellent in low power drivability and image display. Expect to get performance.
- a predetermined amount of reducing gas such as hydrogen gas is added to the mixed gas atmosphere in the sealing step (for example, H 2 gas having a partial pressure of 0.1% to 3% in the entire mixed gas is added).
- H 2 gas having a partial pressure of 0.1% to 3% in the entire mixed gas is added.
- the reduction effect of the reducing gas prevents unnecessary oxidation of the protective layer and forms an oxygen deficient portion in the MgO crystal structure forming the protective layer.
- the oxygen deficient portion is formed, this is used as a so-called light emission center, and an effect of improving the secondary electron emission characteristics of the protective layer 8 can be expected.
- the PDP 1 can be driven at a high speed and a high-speed response even when a driving method specialized for the PDP having fine cells is applied.
- the display of excellent image display performance can be expected based on the property.
- the PDP obtained by the manufacturing method of the present invention is particularly suitable for combination with a predetermined driving method (see FIGS. 3 to 10) using the above-described driving circuits 111 to 113 and the like.
- FIG. 11 is a flowchart showing an outline of a method for manufacturing the PDP 1.
- the front substrate 2 is manufactured (steps A1 to A4), and the rear substrate 9 is separately manufactured (steps B1 to B6).
- the produced substrates 2 and 9 are superposed at a predetermined position (superposition process / positioning process).
- the PDP 1 is completed through the sealing process, the exhaust process, and the discharge gas sealing process shown in FIG. (Front substrate manufacturing process)
- the display electrode pair 6 is produced on one main surface of the front substrate glass 3 (step A2).
- the display electrode pair 6 is formed by a printing method is shown, but other than this, it can be formed by a die coating method, a blade coating method, or the like.
- a transparent electrode material such as ITO, SnO 2 , or ZnO is applied on the front substrate glass in a predetermined pattern such as a stripe with a final thickness of about 100 nm and dried. Thereby, the transparent electrodes 41 and 51 are produced.
- a photosensitive paste obtained by mixing a photosensitive resin (photodegradable resin) with Ag powder and an organic vehicle is prepared, and this is applied to the transparent electrodes 41 and 51 so as to overlap with each other. Cover with a mask having openings matched to the pattern. Then, the mask is exposed and baked at a baking temperature of about 590 to 600 ° C. through a development process. As a result, bus lines 42 and 52 having a final thickness of several ⁇ m are formed on the transparent electrodes 41 and 51. According to this photomask method, the bus lines 42 and 52 can be thinned to a line width of about 30 ⁇ m as compared with the screen printing method in which the line width of 100 ⁇ m is conventionally limited.
- bus lines 42 and 52 As a metal material of the bus lines 42 and 52, in addition to Ag, Pt, Au, Al, Ni, Cr, tin oxide, indium oxide, or the like can be used. In addition to the above method, the bus lines 42 and 52 can also be formed by performing an etching process after forming an electrode material by vapor deposition or sputtering.
- an organic binder composed of lead-based or non-lead-based low melting glass having a softening point of 550 ° C. to 600 ° C., SiO 2 material powder, butyl carbitol acetate, or the like is mixed from above the display electrode pair 6.
- firing is performed at about 550 ° C. to 650 ° C. to form a dielectric layer 7 having a final thickness of several ⁇ m to several tens of ⁇ m (step A3).
- the lead-free low melting glass include bismuth oxide low melting glass.
- glass material an example of this case, 60 wt% bismuth oxide (Bi 2 O 3), boron oxide (B 2 O 3) 15 wt% of silicon oxide (SiO 2) 10 wt%, zinc oxide (ZnO) 15 It can adjust as a composition of weight%.
- a protective layer containing MgO is formed on the surface of the dielectric layer 7 by vacuum vapor deposition, sputtering, EB vapor deposition, or the like (step A4).
- a protective layer can be obtained as a vapor deposition film by using MgO pellets and circulating O 2 in an EB vapor deposition apparatus at 0.1 (sccm).
- a conductive material mainly composed of Ag is applied in stripes at regular intervals by screen printing to form a data electrode 11 having a thickness of several ⁇ m (for example, about 5 ⁇ m).
- a conductive material mainly composed of Ag is applied in stripes at regular intervals by screen printing to form a data electrode 11 having a thickness of several ⁇ m (for example, about 5 ⁇ m).
- materials such as metals such as Ag, Al, Ni, Pt, Cr, Cu, and Pd, conductive ceramics such as carbides and nitrides of various metals, combinations thereof, or combinations thereof are used.
- a laminated electrode formed by laminating can also be used as necessary.
- the interval is set to 0.16 mm or less, for example, in the range of 0.10 mm to 0.16 mm in accordance with the cell pitch. There is a need.
- a glass paste made of lead or non-lead low melting point glass or SiO 2 material is applied to the entire surface of the back substrate glass 10 on which the data electrodes 11 are formed by a screen printing method with a thickness of about 20 to 30 ⁇ m. And firing to form the dielectric layer 12 (step B3).
- partition walls 13 are formed in a predetermined pattern on the surface of the dielectric layer 12 (step B4).
- the partition wall 13 is formed by applying a paste containing glass particles containing bismuth oxide as a main component, a filler, and a photosensitive resin based on a die coating method, exposing it in a predetermined pattern by a photolithography method, and then performing an etching process. To do.
- the partition wall 13 having a predetermined pattern can be formed by sand blasting after applying a paste containing glass and then drying.
- the red (R) phosphor and the green (G) fluorescent light normally used in the AC type PDP are formed on the wall surfaces of the barrier ribs 13 and the surface of the dielectric layer 12 exposed between the adjacent barrier ribs 13.
- the fluorescent ink containing either the body or the blue (B) phosphor is applied. This is dried and baked to form phosphor layers 14 (step B5).
- each color fluorescence examples include as follows. Red phosphor: (Y, Gd) BO 3 : Eu, Y (P, V) O 4 : Eu Green phosphor: Zn 2 SiO 4 : Mn, MgO or Al 2 O 3 coated Zn 2 SiO 4 : Mn, (Y, Gd) BO 3 : Tb, (Y, Gd) Al 3 (BO 3 4 : Tb Blue phosphor; BaMgAl 10 O 17 : Eu
- the present invention is not limited to these composition examples, but in a PDP having a high-definition cell structure, it is necessary to make the charged state of the phosphor uniform in order to stably drive the PDP.
- the phosphors used in PDPs are positively charged. Since Zn 2 SiO 4 : Mn used as the green phosphor is negatively charged, it is desirable to adjust the polarity. Specifically, it is preferable to coat the phosphor with positively charged MgO or Al 2 O 3 .
- the back substrate 9 provided with the phosphor is sealed in a non-oxidizing atmosphere containing only N 2. It is desirable that sealing be performed in a mixed gas atmosphere containing 0.1% to 3% of a reducing gas such as H 2 or NH 3 in a non-oxidizing gas. Thereby, the brightness of the panel can be effectively improved, and the discharge start voltage (Vf) can be reduced.
- a reducing gas such as H 2 or NH 3
- Al 2 O 3 aluminum oxide
- MgO magnesium oxide
- the lysate to Zn 2 SiO 4 by introducing the Mn to prepare a mixed solution, stirred under heating.
- the mixed solution is filtered and dried, and then the dried product is fired at 400 ° C. to 800 ° C. in the air.
- Zn 2 SiO 4 Mn whose surface is coated with Al 2 O 3 or MgO is obtained.
- the coating thickness is preferably 3 nm to 10 nm.
- the film thickness can be adjusted by the stirring time, the concentration of the mixed solution, the pH of the mixed solution, or the like.
- Each phosphor material preferably has an average particle size of 2.0 ⁇ m. This is put in a server at a rate of 50% by mass, 1.0% by mass of ethyl cellulose and 49% by mass of a solvent ( ⁇ -terpineol) are added, and stirred and mixed in a sand mill to give 1.5 ⁇ 10 ⁇ 2 Pa ⁇ s.
- the phosphor ink is prepared. And this is sprayed and applied between the partition walls 13 from a nozzle having a diameter of 60 ⁇ m by a pump. At this time, the panel is moved in the longitudinal direction of the partition wall 20, and the phosphor ink is applied in a stripe shape. Thereafter, the phosphor layer 14 is formed by baking at 500 ° C. for 10 minutes.
- a predetermined sealing material low melting point glass or the like
- a resin binder and a solvent to obtain a sealing material paste.
- various known materials such as acrylic resin, nitrocellulose, and ethylcellulose can be used as the resin binder.
- the solvent various known materials such as isoamyl acetate and terpineol can be used.
- the amount of the resin binder added can be adjusted, for example, to be about 5% by weight with respect to the solvent.
- the softening point of the sealing material (the temperature at which the sealing material begins to soften) is preferably in the range of 410 ° C to 450 ° C.
- the flow temperature of the sealing material (the temperature at which the sealing material flows) is preferably in the range of 450 ° C. to 500 ° C.
- the glass transition point glass transition temperature, Tg
- Tg glass transition temperature
- a low melting point glass material such as bismuth oxide or lead oxide is mixed with a filler such as cordierite, Al 2 O 3 , or SiO 2 .
- a filler such as cordierite, Al 2 O 3 , or SiO 2 .
- the low melting point glass material is mixed at a ratio of 45 to 95% by volume and the filler is mixed at a ratio of 5 to 55% by volume.
- the specific composition (as the composition after completion of the PDP) is as follows: Bi 2 O 3 is 67 to 90% by weight, B 2 O 3 is 2 to 12 wt%, Al 2 O 3 0-5 wt%, ZnO 1-20 wt%, SiO 2 0-0.3 wt%, BaO 0-10 wt%, CuO 0-5 wt%, A composition comprising Fe 2 O 3 in an amount of 0 to 2% by weight, CeO 2 in an amount of 0 to 5% by weight, and Sb 2 O 3 in an amount of 0 to 5% by weight can be obtained.
- the low melting point glass material if the main component of lead oxide-based glass, concrete compositions (as composition after PDP completion) is 65 to 85 wt% of PbO, B 2 O 3 10 to 20 weight %, ZnO 0 to 20% by weight, SiO 2 0 to 2.0% by weight, CuO 0 to 10% by weight, and Fe 2 O 3 0 to 5% by weight. it can.
- the sealing material paste thus obtained is applied so as to surround the periphery of the rear substrate outside the display area (sealing material paste application process).
- This sealing material paste application step can be carried out at a certain high temperature for the purpose of volatilizing the solvent, but it is less than the softening point of the sealing material, which is the maximum temperature of the pre-baking step described below. Must be carried out at temperature.
- glass tubes 31 for introducing exhaust gas are introduced and fixed (see B6 in FIG. 11).
- the glass tube 31 can be disposed immediately after the sealing process and immediately before the exhaust process.
- the back substrate is introduced into a firing furnace to perform temporary firing.
- the maximum temperature in the pre-baking step is equal to or higher than the disappearance temperature of the binder of the sealing material paste (in the case of using a plurality of binders, the temperature is equal to or higher than the minimum disappearance temperature in the binder to be used). Adjust the temperature to be lower than the softening point of the material.
- low melting glass when using low melting glass as a sealing material component, it adjusts more than the glass transition point of the said low melting glass, and 10 degreeC or more lower than the softening point of the said low melting glass.
- the burning temperature here refers to the temperature at which the binder almost disappears from the paste. Specifically, it refers to a temperature that is 10 ° C. or less lower than the softening point, and more specifically, a temperature that is 10 ° C. to 50 ° C. lower than the softening point.
- the components of the polymer confined in the PDP after completion are gradually released from the sealing portion into the discharge space, and adhere to the protective layer made of MgO to deteriorate the secondary electron emission characteristics. Cause the discharge voltage to rise.
- the phosphor layer is also miniaturized, and the occupied area is increased by 2 to 4 times compared to the standard PDP. If the polymer component adheres to the phosphor layer as much as the surface area increases in this way, the luminance is lowered and the image display performance is deteriorated.
- the organic components remain in a low molecular state without being oxidized, and can be effectively removed in the subsequent exhaust step. adjust.
- FIG. 12 is a graph showing an example of a temperature profile in the temporary firing step.
- the back substrate 9 in the state of B6 in FIG. 11 is introduced into the firing furnace.
- the firing atmosphere can be set to an atmosphere containing some oxygen (for example, an atmosphere containing oxygen at a partial pressure of 1% or less).
- a non-oxidizing atmosphere for example, an atmosphere containing nitrogen having a dew point of ⁇ 45 ° C. or lower.
- the firing furnace is raised from room temperature to the pre-baking temperature (400 ° C.) (step 1, pre-baking temperature raising step).
- This pre-baking temperature is the maximum temperature in the pre-baking step, and is a value set as below the softening point of the low-melting glass of the sealing material as described above.
- the maximum temperature (400 ° C.) of the pre-baking is maintained for a predetermined period (for example, 10 to 30 minutes) and pre-baked (step 2, pre-baking temperature maintaining step).
- the temperature lowering step includes a first temperature lowering step (“3-a” in FIG. 5) for lowering both the substrates from the maximum temperature (400 ° C.) to a first temperature higher than the binder disappearance temperature and room temperature, A second temperature lowering step (“3-b” in FIG. 5) for lowering both the substrates from temperature to room temperature is sequentially performed.
- the first temperature lowering step is performed in a shorter time than the second temperature lowering step, and both the substrates are cooled relatively rapidly to the first temperature.
- the first temperature is set to 200 ° C.
- the first temperature lowering step is performed in a short time of 20 minutes to 30 minutes.
- a 2nd temperature fall step it adjusts so that it may fall slowly over 2 hours or more until the temperature fall of at least about 50 degreeC.
- the reason why the first temperature lowering step is set to the upper limit of 30 minutes or less is that the power consumption of the completed PDP is compared with the case where the first temperature lowering step is performed for a time exceeding 30 minutes according to the study by the present inventors. This is based on the fact that the knowledge that can be further reduced is obtained.
- the power consumption of the PDP is favorably reduced by performing the first temperature lowering step at the above temperature setting and in a short time as described above.
- the reason for this is that since the amount of impurities gradually released from the sealing portion 16 to the discharge space 15 after the completion of the PDP is reduced, the alteration of the protective layer 8 containing MgO is suppressed, and the secondary electron emission characteristics are improved. This is probably because the decrease was effectively prevented.
- the reason why the amount of impurities released from the sealing portion 16 is reduced can be considered as follows.
- the decomposition (lower molecular weight) of the organic component of the binder of the sealing material paste proceeds at a temperature higher than the disappearance temperature.
- Such an organic component decomposed at a high temperature hereinafter referred to as a low molecular component
- the low-molecular component is re-bonded (polymerized) before disappearing, so that the organic material that has been polymerized from the beginning, that is, is less likely to volatilize. It may become tar. This tar remains inside both substrates even after the exhaust process, and may cause a negative effect on the performance of the PDP.
- the pre-baking temperature is set as a heating temperature of the organic component of the binder, a temperature higher than the disappearance temperature of the binder of the sealing material paste, and lower than the softening point of the low-melting glass of the sealing material. As described above, it is effective to perform tarring of the low molecular component.
- Step 2 in which the maximum temperature of the pre-baking is maintained for a certain period, most of the organic components of the binder are decomposed (lower molecular weight) and disappear. However, the decomposition is not completely performed within the period of Step 2, and some organic components may remain without being reduced in molecular weight.
- step 3 temperature lowering step
- decomposition proceeds in that period.
- the temperature of the entire step 3 is gradually decreased, the low molecular component generated by decomposition in the period of step 3 has a characteristic that it is difficult to disappear compared to step 2 in which the maximum temperature is kept.
- the low molecular component is easily taken into the sealing portion 16. In this way, the low molecular component remaining in the sealing portion 16 is released as impurities (impure gas) from the sealing portion 16 in the completed PDP.
- a first temperature lowering step is provided at the beginning of step 3, and both substrates are quickly moved from the maximum temperature of pre-baking to the first temperature lower than the disappearance temperature of the binder of the sealing material paste and higher than room temperature. The temperature is adjusted to drop.
- the organic component is prevented from remaining as a low molecular component as much as possible, and the amount of impurities released from the sealing portion 16 to the discharge space 15 in the completed PDP is reduced. Yes.
- the temperature lowering rate of the first temperature lowering step is as fast as possible for the above reason.
- the rate of temperature drop in the first temperature drop step is too high, the glass substrate of the PDP may be broken, and the substrate may be damaged. Therefore, it is necessary to consider the setting of the temperature drop temperature including this point. There is.
- the binder is not decomposed within the temperature range in the temperature lowering step below the binder disappearance temperature and to the room temperature. Therefore, the temperature decreasing pace in the temperature range may be arbitrarily determined.
- the solvent or binder component in the sealing material paste is generally burned to generate and remove carbon dioxide (CO 2 ), but an oxidizing gas component such as oxygen in the pre-baking atmosphere. If a large amount of carbon dioxide is contained, carbon dioxide gas is rapidly generated, and the glass component of the sealing material is foamed, which may result in incomplete sealing. Incomplete sealing should be avoided because it will cause discharge gas leakage later.
- CO 2 carbon dioxide
- an oxidizing gas component such as oxygen in the pre-baking atmosphere.
- a weak oxidizing atmosphere for example, a mixed atmosphere containing nitrogen as a main component and oxygen having a partial pressure of 1% or less
- a non-oxidizing atmosphere It is desirable to perform pre-baking in an atmosphere containing nitrogen. If it contains an acrylic resin in the resin component of the sealing material paste and, if Bi 2 O 3 based glass and P 2 O 5 based glass is used in the sealing material, a non-oxidizing atmosphere with N 2, etc. It is preferable to carry out a temporary baking step.
- FIG. 11 the sealing portion 16 before the sealing step is illustrated. However, after sealing, the glass of the sealing portion 16 is melted to reduce the height, and the top of the partition wall 13 is connected to the protective layer 8. Abut.
- FIG. 13 shows a sealing furnace 220, an exhaust device 160, and a gas introduction device 140 (in FIG.
- valves 180, 190, 200, 210, and 230 are shown. Exhaust, gas flow, and gas introduction from both substrates are adjusted by opening or closing any of the valves 180, 190, 200, 210, and 230 at a predetermined timing. Furthermore, the valve 190 can adjust the dew point and pressure inside the sealing and discharging furnace 220.
- valves 180, 210, and 230 may be provided inside the gas introduction device 140, and the valve 200 may be provided inside the exhaust device 160.
- FIG. 14 is a graph showing temperature profile examples of the sealing process, the exhaust process, and the discharge gas introduction process. In addition, these heating temperature and temperature and a maintenance period are only examples.
- the sealing atmosphere in the sealing and discharging heating furnace 220 is adjusted. For this reason, the valves 190 and 210 are opened, and a non-oxidizing gas (Ar gas or dew point of ⁇ 45 ° C. or less as an example) is introduced from the gas introducing device 140 into the inside of both substrates or the inside of the sealing heating furnace 220. N 2 gas) and a reducing gas (H 2 gas as an example) are mixed and flowed and filled in a mixed atmosphere.
- a non-oxidizing gas Ar gas or dew point of ⁇ 45 ° C. or less as an example
- the amount of reducing gas added to the sealing atmosphere is preferably such that the partial pressure is in the range of 0.1% or more and 3% or less as a ratio of the entire mixed atmosphere. Even if the partial pressure is less than 0.1%, it is possible to lower the discharge start voltage. However, when a Zn 2 SiO 4 : Mn phosphor coated with MgO or Al 2 O 3 is used, the oxygen may be reduced depending on the coating. In addition, the adsorption amount of water and water increase, and the effect of reducing the discharge start voltage hardly appears. On the other hand, if the partial pressure exceeds 3%, defects are observed in the dielectric layer, and display unevenness can occur on the display surface of the PDP, which is not preferable.
- oxidizing gas such as oxygen derived from the atmosphere may be mixed in the sealing atmosphere in some cases, but sealing in a gas atmosphere in which a small amount of reducing gas is substantially mixed in non-oxidizing gas. Adjust so that the influence of mixing of oxidizing gas is reduced as much as possible so that the deposition process can be performed.
- a reducing gas as a sealing atmosphere component, even if an oxidizing gas such as oxygen is mixed in, the adverse effect is suppressed as much as possible by the reducing action, and the polymerization of organic components and the panel are performed. Residual inside can be suppressed.
- the dew point and pressure in the gas furnace in which a small amount of reducing gas is mixed in the non-oxidizing gas are set to a slightly positive pressure by controlling the valve 190.
- the heaters 260 are energized to heat both substrates while controlling the valves 180, 190, and 210 to send a gas obtained by mixing a small amount of a reducing gas into a non-oxidizing gas into both the substrates and the furnace. .
- the temperature of both substrates is raised from room temperature to the softening point temperature (410 ° C. to 450 ° C.) of the sealing material.
- step 1 When the temperature of both substrates rises to the softening point temperature, the temperature is maintained for a certain period (about 1 hour) as a sealing temperature maintenance step (step 1 so far). Note that maintaining the temperature at the softening point is not essential, and may be omitted if it is desired to moderate the temperature rise to the pour point of the sealing material.
- both substrates are kept at the pour point (melting temperature, 450 ° C. to 500 ° C.) (sealing temperature increasing step). In other words, this temperature is 40 ° C. or more higher than the softening point of the sealing material. This temperature is maintained for a certain period (about 1 hour) (sealing temperature maintaining step), and then cooled to the exhaust temperature (400 ° C. to 420 ° C.) or lower as the sealing temperature lowering step (step 2 so far).
- the low melting point glass of the sealing material is melted to become a dense structure, and is solidified again by cooling to form the completed sealing portion 16.
- the valve 180 is closed, the valves 190, 200, and 210 are opened, and the gas between the two substrates is evacuated by the exhaust device 160, and the sealing / exhaust heating furnace 220 is brought into the vacuum exhaust furnace state.
- the temperature of both the substrates is increased to a predetermined exhaust temperature.
- the temperature is maintained for a certain time (4 hours).
- the exhaust temperature is preferably set to be lower than the softening point of the sealing material (preferably a temperature lower by 10 ° C. to 30 ° C. than the softening point).
- both substrate temperatures are cooled to room temperature (step 3).
- an organic component (CH-based component) derived from the sealing material paste that has been kept in a low molecular state in the pre-baking process is vaporized and removed from between both substrates together with the flowing gas. Since this organic component is not polymerized and is in a low molecular state, it can be detached from the surfaces and sealing materials inside both substrates relatively easily by gas flow during the exhaust process, and efficiently from both substrates. Can be removed.
- carbon dioxide gas such as CO and CO 2 generated between the two substrates is also removed simultaneously.
- This carbon dioxide gas is generated by burning some organic components remaining between both substrates during the exhaust process, but the exhaust process is relatively low temperature, so it does not generate a large amount and generates a small amount. That's it.
- the valve 190, 200, 210 is closed and the valve 180 is opened, and a discharge gas containing 15% or more of Xe, for example, a Ne—Xe-based discharge gas (for example, 70% Ne— 30% Xe gas) is introduced at a predetermined pressure (for example, 66 KPa).
- a Ne—Xe-based discharge gas for example, 70% Ne— 30% Xe gas
- the glass tube 31 After introducing the discharge gas, the glass tube 31 is chipped off and sealed internally (chip off process). This completes the PDP manufacturing process.
- both the substrates being manufactured after the sealing step can be once taken out into the atmosphere, and then the exhaust step can be performed by connecting an exhaust device to the both substrates. Further, both substrates taken out into the atmosphere can be temporarily stored before the exhaust process.
- the present invention unlike the prior art, there is no need to consistently manufacture the PDP in a reduced pressure atmosphere isolated from the atmosphere over each process, and a large scale for maintaining a reduced pressure atmosphere during or between each process.
- a manufacturing device such as a decompression device is unnecessary.
- the present invention can store both substrates being manufactured before the exhaust process as described above, there is also an advantage that the execution plan of the manufacturing process can be flexibly adjusted. As described above, the present invention is also very advantageous in that it has high feasibility.
- Example 1 A PDP having a fine cell structure with a cell pitch of 0.10 mm is used, and MgO pellets for forming a protective layer are used in the front substrate manufacturing process, and 0.1 (sccm) of O 2 is circulated in the EB vapor deposition apparatus. A protective layer was formed.
- (Y, Gd) BO 3 : Eu was used as the red phosphor
- Zn 2 SiO 4 : Mn was used as the green phosphor
- BaMgAl 10 O 17 : Eu was used as the blue phosphor.
- the composition of the sealing material PbO—B 2 O 3 —RO—MO glass shown in Table 1 described later, which is mainly composed of lead oxide glass (PbO), was used.
- the softening point is 430 ° C. and the pour point is 490 ° C.
- the maximum temperature in the pre-baking process (step 2 of the temperature profile in FIG. 12) was set to 400 ° C., which is 30 ° C. lower than the softening point of the sealing material, and was performed in an air atmosphere for 50 minutes.
- step 1 of the sealing process (step 1 of the temperature profile in FIG. 14), first, a gas in which 0.1% of H 2 gas is mixed with N 2 gas having a dew point temperature of ⁇ 50 ° C. in the heating furnace 120 for sealing exhaust. was filled. Next, the temperature in the furnace is adjusted by using the heater 160 in the sealing heating furnace 120 while blowing a gas in which 0.1% of H 2 gas is mixed with N 2 gas at a flow rate of 5 L / min. The temperature was raised to around the softening point (420 ° C.) of the sealing material (at this time, the valves 100, 90, 110 of the exhaust device 60 were closed).
- step 2 of the sealing process subsequent to the above step 1, 0.1% of H 2 gas is added to N 2 gas having a dew point temperature of ⁇ 50 ° C.
- the mixed gas was filled at a partial pressure of.
- the flow rate of the gas obtained by mixing the N 2 gas with the H 2 gas at a partial pressure of 0.1% is set to be equal to or less than half of the step 1 (2 L / min).
- the temperature of the sealing and discharging heating furnace 120 is raised to a sealing temperature (flow temperature) (490 ° C.) at which the sealing material is sufficiently softened. This sealing temperature was maintained for about 50 minutes, and then the furnace temperature was lowered to a temperature below the softening point of the sealing material (300 ° C.).
- step 3 of FIG. 14 following the sealing process (steps 1 and 2), the valves 80 and 110 are closed and the valves 100, 90 and 130 are opened, thereby evacuating between the substrates and in the furnace. did.
- the temperature of the heating furnace 120 for sealing and discharging is again increased from 300 ° C. to 410 ° C. below the softening point of the sealing material (20 ° C. lower than the softening point of the sealing material) and maintained at that temperature for about 4 hours. did. Thereafter, the temperature of the furnace was lowered to room temperature while evacuating.
- Step 4 of FIG. 14 the valves 100, 90, and 130 are closed and the valve 80 is opened at room temperature, and the discharge gas (100% Xe) having the above composition is supplied from the gas introduction device 40. It was sealed between both substrates at a pressure of 66 KPa.
- Example 2 As shown in Table 1, the sealing step was performed in an atmosphere in which H 2 gas was mixed with N 2 gas at a partial pressure of 3.0%. Points other than the above were basically set in the same manner as in Example 1.
- Example 3 Cell pitch and PDP cell structure of 0.15 mm, in the front substrate preparing step, 100 ppm of SiO 2 to MgO, The pellets were added respectively Al 2 O 3 at a concentration of 500 ppm, an O 2 in the EB vapor deposition apparatus 0 .1 (sccm) was obtained to obtain a protective layer made of MgO to which the above materials were added.
- the composition of the sealing material was a mixed composition of glass composed mainly of Bi 2 O 3 and filler composed of Al 2 O 3 , SiO 2 , and cordierite (Bi 2 O 3 —B 2 O shown in Table 1). 3 -Uses RO-MO glass). In this case, the softening point of the sealing material is 450 ° C., and the sealing temperature is 500 ° C.
- the maximum temperature in the pre-baking step was set to 410 ° C. which was 40 ° C. lower than the softening point of the sealing material.
- the sealing step was performed in an atmosphere in which N 2 gas having a dew point of ⁇ 55 ° C. was mixed with H 2 gas at a partial pressure of 1.5%.
- step 3 of FIG. 14 following the sealing process (steps 1 and 2), the valves 80 and 110 are closed and the valves 100, 90 and 130 are opened, thereby evacuating between the substrates and in the furnace. did.
- the temperature of the heating furnace 120 for sealing and discharging is again increased from 300 ° C. to 420 ° C. below the softening point of the sealing material (30 ° C. lower than the softening point of the sealing material) and maintained at that temperature for about 4 hours. did. Thereafter, the temperature of the furnace was lowered to room temperature while evacuating.
- Step 4 of FIG. 14 the valves 100, 90, and 130 are closed and the valve 80 is opened at room temperature, and the discharge gas (85% Ne-15) having the above composition is supplied from the gas introduction device 40. % Xe) was sealed between both substrates at a pressure of 66 KPa.
- Examples 1 to 3 and Comparative Examples 1 and 2 produced as described above were designated as Samples 1 to 5, respectively.
- Vf Each value of Vf is summarized in Table 1. Samples 1 to 5 were all set to a temperature lower than the softening point of the sealing material when setting the maximum temperature in the preliminary firing step.
- each of Examples 1 and 2 and Comparative Example 1 has a configuration in which the same PbO-based glass is used as the sealing material, and MgO is used as the protective layer in the front substrate forming process.
- the sealing atmosphere mixed atmosphere
- the sealing atmosphere was non-oxidizing.
- the effect of reducing the discharge start voltage Vf is clearly exhibited.
- Comparative Example 1 The reason is that in Comparative Example 1, the sealing step was performed in a sealing atmosphere containing only N 2 , so that the organic components in the sealing material paste were in contact with oxygen remaining in a minute amount during the sealing step and burned. In addition, it is considered that impurities such as the generated polymer are adsorbed to the protective layer as a gas, and the protective layer has been altered, leading to an increase in voltage. Meanwhile, since the sealing step in Examples 1 and 2 were carried out in sealed atmosphere of a mixture of reducing gas in N 2, the generation of such polymers is suppressed, while the organic component is a low molecular state exhausting process It is considered that the protective layer has been sufficiently removed and the alteration of the protective layer has been effectively suppressed.
- Examples 1 and 2 it is considered that a good reduction effect of the driving voltage appears by mixing reducing gas with N 2 in a sealed atmosphere.
- Examples 1 and 2 are compared. Then, in Example 2 in which the reducing gas was added at a partial pressure of 3.0%, the discharge was more effective than in Example 1 in which the reducing gas was added at a partial pressure of 0.1% in the sealing atmosphere. The effect of reducing the starting voltage Vf is obtained.
- the results of Examples 1 and 2 show that the above effect can be obtained by adding a reducing gas. However, if the addition amount is about 3% compared to 0.1%, a better effect can be obtained. Appears. Accordingly, the amount of reducing gas added in the sealing atmosphere is preferably in the range of at least a partial pressure of 0.1% to 3%, and more preferably the partial pressure of the reducing gas is set higher in this range. It can be said.
- Example 3 and Comparative Example 2 are compared, both use bismuth (Bi 2 O 3 ) -based glass as the sealing material, and the composition of the protective layer in the front substrate preparation step is MgO with 100 ppm of SiO 2 , the al 2 O 3 are used have been added 500 ppm.
- a sealing atmosphere in which a reducing gas is mixed with a non-oxidizing gas in the sealing process is used.
- Example 3 has a better effect of reducing the discharge start voltage Vf than the sample (Comparative Example 2) using only the non-oxidizing N 2 gas in the sealing atmosphere. .
- the reason why such a result was obtained seems to be the same as the discussion in Examples 1 and 2 and Comparative Example 2.
- the sealing atmosphere is used by mixing a non-oxidizing gas and a reducing gas in a predetermined ratio.
- Examples 1 and 2 and Comparative Example 1 are configured to have fine cells having a cell pitch of 0.10 mm. From the above results, according to the present invention, even if the PDP has a high-definition cell structure with a small cell pitch, it can be expected to reduce the power consumption satisfactorily.
- steps 1 and 2 in the sealing process were performed in an atmosphere using N 2 gas as a non-oxidizing gas and H 2 as a reducing gas. It can be expected that the same effect can be expected even when Ar or Xe gas is used as the reactive gas and NH 3 is used as the reducing gas.
- a panel having the highest effect of the present invention and having a panel resolution of FHD or higher has been described as an example.
- a panel having an ultra-high resolution such as SD, HD, or FHD. Needless to say, the same effect can be obtained.
- the present invention is not limited to the above-described high definition or ultra high definition panel.
- the present invention since a high-speed drive is required even for a large panel (50 inches or more) having a relatively large number of scanning lines, the present invention has a good effect even when applied to such a panel.
- the application of the present invention is not limited to such a high-definition / ultra-high-definition panel or a large-screen panel, but is applied to a PDP having a relatively large discharge cell structure constituted by XGA, SXGA standards, etc. It is also possible to do.
- the present invention is an invention useful for providing a large-screen, high-definition PDP device, and can be said to be extremely highly usable as a public facility, a home-use television, or the like.
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Abstract
Description
(PDP装置の構成)
実施の形態1のPDP装置1000は、PDP1に対し、所定の駆動回路111~113等を接続して構成される。
(その他の回路構成について)
本実施の形態において示した維持パルス発生回路、傾斜波形発生回路等は、単に具体例の一つを示したに過ぎない。同様の駆動電圧波形を発生させることができれば他の回路構成であってもよい。
(その他の表示電極グループについて)
PDP1では表示電極対6を合計2160対形成し、表示電極対グループを2グループに分ける例を説明したが、本発明ではこのグループ化の方法に限定しない。例えば図6のPDP101に示すように、表示電極対を4320対形成するとともに、データ電極D1~Dmを走査電極SC1~SC2160および維持電極SU1~SU2160と交差させ、別のデータ電極Dm+1~D2mを走査電極SC2161~SC4320および維持電極SU2161~SU4320と交差させたパネル構成とすることもできる。このPDP101の構成でもPDP1と同様の動作をさせることが可能である。
ここでは上記構成を有するPDP装置1000の駆動方法について例示する。なお、当該駆動方法の説明については、例えば特願2008-116719号にも記載されている。本実施の形態においては、初期化期間を除き、書込み動作が連続して行われるように、走査パルスおよび書込みパルスのタイミングを設定している。その結果、1フィールド期間内に最大限の数のサブフィールド(S.F.)を設定することができる。本実施の形態においては、n=2160として、パネルを駆動する駆動方法について説明する。
(各グループのサブフィールド時間設定)
まず、N個に分割された各表示電極対グループにおいて、サブフィールドの開始時間などをどのように設定するかについて、図8のタイムチャート例を用いて説明する。
Ts≦Tw×(N-1)/N
(Tsは最も輝度重みの大きいサブフィールドの維持期間に割り当てる時間)
を満たすように設定している。
N≧Tw/(Tw-Ts)
に基づき求めることができる。すなわち、TsはTw(N-1)/Nを超えないことが必要である。
<PDPの製造方法>
図11は、PDP1の製造方法の概略を示すフロー図である。図11に示すように、製造過程では前面基板2を作製するとともに(工程A1~A4)、背面基板9を別途作製する(工程B1~B6)。そして、作製した両基板2、9を所定の位置で重ね合わせる(重ね合わせ工程・位置決め工程)。その後、図14に示す封着工程、排気工程、放電ガス封入工程を順次経て、PDP1を完成する。
(前面基板作製工程)
前面基板ガラス3の一方の主面上に表示電極対6を作製する(工程A2)。ここでは印刷法によって表示電極対6を形成する例を示すが、これ以外にもダイコート法、ブレードコート法等で形成することができる。
(背面基板作製工程)
背面基板ガラス10の一方の主面上に、スクリーン印刷法によりAgを主成分とする導電体材料を一定間隔でストライプ状に塗布し、厚さ数μm(例えば約5μm)のデータ電極11を形成する(工程B2)。データ電極11の電極材料としては、Ag、Al、Ni、Pt、Cr、Cu、Pd等の金属や、各種金属の炭化物や窒化物等の導電性セラミックスなどの材料やこれらの組み合わせ、あるいはそれらを積層して形成される積層電極も必要に応じて使用できる。
・赤色蛍光体;(Y、Gd)BO3:Eu、Y(P、V)O4:Eu
・緑色蛍光体;Zn2SiO4:Mn、MgOあるいはAl2O3がコートされた、Zn2SiO4:Mn、(Y、Gd)BO3:Tb、(Y、Gd)Al3(BO3)4:Tb
・青色蛍光体;BaMgAl10O17:Eu
本発明は当然ながら、これらの組成例に限定するものではないが、高精細セル構造のPDPにおいては、駆動を安定に行うためには蛍光体の帯電状態を均一にすることが必要である。
(封着材塗布・仮焼成工程)
まず、所定の封着材(低融点ガラス等)に樹脂バインダー、溶剤を混合して調整し、封着材ペーストを得る。
これによって、保護層や蛍光体層の劣化を防止するものとしている。
(重ね合わせ(位置決め)工程)
上記作製した前面基板2と背面基板9とを、表示電極対6及びデータ電極11が交差するように対向配置させて重ね合わせる。位置ずれをしないように、両基板をスプリング機構を備えるクリップ(不図示)で挟んで保持する。このとき、隔壁13の頂部が保護層8と対向するように配設する。ここで本発明では、大がかりな減圧装置等を用いなくても当該重ね合わせ工程を大気中で実施することができるので、両基板のハンドリングが容易であり、製造上、極めて有用である。また、これにより製造するPDPのサイズを50インチを超える大型とする場合であっても、比較的低コストで製造することが可能になっている。
(封着工程、排気工程、放電ガス導入工程)
図13及び図14を用いて当該各工程を説明する。図13は、封排用加熱炉220と、排気装置160、ガス導入装置140(図13では封着工程中に非酸化性ガス中に還元性ガスを少量混合(添加)したガスを導入し、一方、放電ガスを導入することもできるものとする)がバルブ180、190、200、210、230を介して所定の配管で接続されたガス流通システム例を示す。両基板内部からの排気及びガス流通、ガス導入は、バルブ180、190、200、210、230のいずれかを所定のタイミングで開閉することで調節される。さらにバルブ190は、封排用加熱炉220の内部の露点と圧力を調整することができる。
両基板の温度が室温まで低下すると、排気工程が終了する。
本発明の製造方法の性能効果を確認するため、実施例のPDP(実施例1~3)と、比較例のPDP(比較例1~2)をそれぞれ作製し、各PDPの放電電圧を測定した。PDPの製造方法は、明示した以外の工程は上記したパネルの製造方法に基づくものとした。
(実施例1)
セルピッチが0.10mmの微細セル構造のPDPとし、前面基板作製工程において、保護層形成用のMgOペレットを用い、EB蒸着装置内にO2を0.1(sccm)流通することによりMgOのみからなる保護層を形成した。
(実施例2)
封着工程は表1に示すようにN2ガスにH2ガスを3.0%の分圧で混合した雰囲気下で行った。上記以外の点は基本的に実施例1と同様に設定した。
(実施例3)
セルピッチが0.15mmのセル構造のPDPとし、前面基板作成工程において、MgOにSiO2を100ppm、Al2O3を500ppmの濃度でそれぞれ添加したペレットを用い、EB蒸着装置内にO2を0.1(sccm)で流通させることで、上記材料が添加されたMgOからなる保護層を得た。
(比較例1)
封着工程中のステップ1及び2を、露点-50℃のN2のみの非酸化雰囲気で実施した。これ以外の条件を実施例1と同様に設定して得たPDPを比較例1とした。
(比較例2)
封着工程中のステップ1及び2を、露点-55℃のN2のみの非酸化雰囲気で実施した。これ以外の条件を実施例3と同様にして得たPDPを比較例2とした。
まず表1に示されるように、実施例1、2、比較例1は、いずれも封着材に同様のPbO系ガラスを用い、前面基板作成工程の保護層にMgOを用いた構成である。この共通構成を前提とし、非酸化性ガスと還元性ガスを混合してなる封着雰囲気(混合雰囲気)で封着工程を行った実施例1、2のサンプルでは、封着雰囲気に非酸化性N2ガスのみを使用した比較例1のサンプルに比べ、明らかに放電開始電圧Vfの低減効果が発揮されているのが確認できる。
次に実施例1と2を比較すると、封着雰囲気中に還元性ガスを0.1%の分圧だけ添加した実施例1よりも、還元性ガスを3.0%の分圧で添加した実施例2で一層効果的に放電開始電圧Vfの低減効果が得られている。この実施例1、2の結果をみると、還元性ガスを添加することで前記効果はそれなりに得られるが、添加量としては0.1%に比べて3%程度添加すれば一層良好な効果が表れる。よって、封着雰囲気中の還元性ガスの添加量としては、少なくとも分圧が0.1%~3%の範囲は好適であり、当該範囲において還元性ガスの分圧を高く設定するほどより好ましいと言える。
上記実施の形態では、本発明の効果が最も奏される、パネルの解像度がFHD以上のパネルを例として説明したが、当然ながら、いわゆる、SD、HD、FHDといった超高精細な解像度を持つパネルに対しても同等の効果が得られるのは言うまでもない。
2 前面基板(フロントパネル)
3 前面基板ガラス
8 保護層
9 背面基板(バックパネル)
10 背面基板ガラス
13 隔壁
16 封着部
31 ガラス管(チップ管)
111 走査電極駆動回路
112 維持電極駆動回路
113 データ(アドレス)電極駆動回路
140 ガス導入装置
160 排気装置
180、190、200、210、230 バルブ
220 封排用加熱炉
260 ヒーター
1000 PDP装置
Claims (17)
- 背面基板又は表面にMgOを含む保護層が形成された前面基板のうち、一方の基板の主面の周囲に封着材を含むペーストを配設し、当該ペーストに含まれるバインダーの消失温度以上かつ封着材の軟化点温度未満の温度を仮焼成最高温度として、前記塗布したペーストを焼成する仮焼成工程と、
前記仮焼成工程後に、前記一方の基板の主面に他方の基板の主面を対向配置させ、前記両基板を重ね合わせる位置決め工程と、
位置決め工程後に、非酸化性ガスと還元性ガスの混合雰囲気下で、所定の封着温度で焼成して前記両基板を封着させる封着工程と、
前記封着工程後に、前記両基板間のガスを排気させる排気工程と、
を備えるプラズマディスプレイパネルの製造方法。 - 前記仮焼成工程では、前記最高温度で焼成を行った後、前記両基板の温度をバインダー消失温度未満且つ室温より高い第一温度まで下降させる第一降温ステップと、第一降温ステップ後に、前記両基板の温度を前記第一温度から室温まで温度降下させる第二降温ステップとを含み、
第一降温ステップは、第二降温ステップよりも短時間で行う
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記第一降温ステップにおける前記第一温度を200℃とし、第一降温ステップに係る時間を20分以上30分以下に設定する
請求項2に記載のプラズマディスプレイパネルの製造方法。 - 前記第二降温ステップの時間を、第一降温ステップの時間よりも5倍以上長時間に設定する
請求項2に記載のプラズマディスプレイパネルの製造方法。 - 前記仮焼成最高温度を、前記軟化点よりも10℃以上低い温度とする
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記仮焼成最高温度を、前記軟化点よりも10℃から50℃低い温度とする
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記仮焼成工程では、前記封着材として低融点ガラスを成分に含む封着材を用い、当該低融点ガラスのガラス転移点以上かつ当該低融点ガラスの軟化点よりも10℃以下の低い温度で焼成を実施する
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記封着工程では、前記封着温度として前記軟化点温度より40℃以上の高い温度に設定する
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 封着工程では、非酸化性ガスとしてN2ガスあるいはArガスを用い、還元性ガスとしてH2ガスを用いる
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記混合雰囲気中における前記H2ガス分圧が0.1%以上3%以下である
請求項9に記載のプラズマディスプレイパネルの製造方法。 - 前記仮焼成工程は、露点が-45℃以下のN2雰囲気下で行う
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記仮焼成工程は、O2を1%以下の分圧で含有するN2雰囲気下で行う
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記封着工程では、前記両基板の温度を室温から前記封着温度まで上昇させる封着温度上昇ステップと、
前記封着温度上昇ステップ後に前記封着温度を一定時間維持する封着温度維持ステップと、
前記封着温度維持ステップ後に、前記両基板の温度を前記封着温度から前記軟化点未満の温度まで下降させる封着温度下降ステップとを、少なくとも含む
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記排気工程では、前記両基板を室温以上、前記軟化点未満の温度で一定時間維持する排気温度維持ステップと、
前記排気温度維持ステップ後に、前記両基板温度を室温まで下降させる排気温度下降ステップとを、順次、それぞれ減圧雰囲気下で行う
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記封着工程前において、背面基板の主面に隣接する隔壁を0.16mm以下のピッチに設定して複数併設するとともに、隣接する前記各隔壁間に蛍光体層を形成し、
前記排気工程後の前記両基板の間に、Xeを15%以上の分圧で含む放電ガスを封入する
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 前記封着工程前において、パネル画素数が横方向に1920個以上で且つ縦方向に1080個以上となるように、背面基板の主面に隣接する隔壁のピッチを設定して複数の隔壁を併設するとともに、隣接隔壁間に蛍光体層を形成し、
排気工程後の前記両基板の間に、Xeを15%以上の分圧で含む放電ガスを封入する
請求項1に記載のプラズマディスプレイパネルの製造方法。 - 請求項1に記載のプラズマディスプレイパネルの製造方法によって作製されたプラズマディスプレイパネルの駆動方法であって、
当該プラズマディスプレイパネルは、走査電極と維持電極とで構成された表示電極対を複数備えるとともに複数のデータ電極を備え、前記表示電極対と前記データ電極とが交差する位置のそれぞれに放電セルを備えており、
前記複数の表示電極対を複数の表示電極対グループに分け、
前記表示電極対グループ毎に、放電セルで書込み放電を発生させる書込み期間と前記放電セルで維持放電を発生させる維持期間とを有する複数のサブフィールドを用いて1フィールド期間を分割し、
前記表示電極対グループの数をN(Nは2以上の整数)、パネル全体の放電セルで1回の書込み動作を行うために必要な時間をTwとするとき、
各表示電極対グループの各サブフィールドの維持期間の時間を、
Tw×(N-1)/N以下に設定して駆動する
プラズマディスプレイパネルの駆動方法。
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WO2013018336A1 (ja) * | 2011-08-02 | 2013-02-07 | パナソニック株式会社 | プラズマディスプレイパネルおよびその製造方法 |
WO2013018335A1 (ja) * | 2011-08-02 | 2013-02-07 | パナソニック株式会社 | プラズマディスプレイパネルおよびその製造方法 |
WO2013018348A1 (ja) * | 2011-08-03 | 2013-02-07 | パナソニック株式会社 | プラズマディスプレイパネルおよびその製造方法 |
WO2013018351A1 (ja) * | 2011-08-03 | 2013-02-07 | パナソニック株式会社 | プラズマディスプレイパネルおよびその製造方法 |
WO2013018355A1 (ja) * | 2011-08-04 | 2013-02-07 | パナソニック株式会社 | プラズマディスプレイパネルおよびその製造方法 |
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US20110165818A1 (en) | 2011-07-07 |
US8317563B2 (en) | 2012-11-27 |
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