WO2010137819A3 - 디램으로 에스램 출력특성을 구현하는 장치 및 방법 - Google Patents

디램으로 에스램 출력특성을 구현하는 장치 및 방법 Download PDF

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Publication number
WO2010137819A3
WO2010137819A3 PCT/KR2010/003151 KR2010003151W WO2010137819A3 WO 2010137819 A3 WO2010137819 A3 WO 2010137819A3 KR 2010003151 W KR2010003151 W KR 2010003151W WO 2010137819 A3 WO2010137819 A3 WO 2010137819A3
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WO
WIPO (PCT)
Prior art keywords
drams
control signal
dram
data
output state
Prior art date
Application number
PCT/KR2010/003151
Other languages
English (en)
French (fr)
Other versions
WO2010137819A2 (ko
Inventor
이성재
Original Assignee
Lee Seong Jae
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lee Seong Jae filed Critical Lee Seong Jae
Priority to JP2011542021A priority Critical patent/JP5943250B2/ja
Priority to CN201080020819.4A priority patent/CN102422359B/zh
Priority to EP10780730A priority patent/EP2437267A4/en
Publication of WO2010137819A2 publication Critical patent/WO2010137819A2/ko
Publication of WO2010137819A3 publication Critical patent/WO2010137819A3/ko
Priority to US13/118,287 priority patent/US8422314B2/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

디램을 이용하여 에스램의 출력특성을 얻을 수 있도록, 복수의 디램을 컨트롤러에 병렬로 배열 연결하고, 외부장치로부터 데이터 판독에 대한 제어신호가 입력되면 컨트롤러에서는 하나의 디램에는 데이터 출력상태의 제어신호를 전송하며 나머지 다른 디램에는 리프레시대기상태의 제어신호를 전송하고, 출력상태의 디램으로부터 데이터를 판독하여 외부장치로 전송하고, 출력상태였던 디램에 리프레시대기상태의 제어신호를 전송하고 다른 하나의 디램에 출력상태의 제어신호를 전송하고, 출력상태의 디램으로부터 데이터를 판독하는 단계와 출력상태를 리프레시대기상태로 변경하는 제어신호를 전송하는 단계를 순차적으로 반복하여 외부장치로 데이터를 출력하는 과정을 포함하는 디램으로 에스램 출력특성을 구현하는 방법을 제공한다.
PCT/KR2010/003151 2009-05-25 2010-05-19 디램으로 에스램 출력특성을 구현하는 장치 및 방법 WO2010137819A2 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2011542021A JP5943250B2 (ja) 2009-05-25 2010-05-19 Ｄｒａｍでｓｒａｍ出力特性を具現する装置及び方法
CN201080020819.4A CN102422359B (zh) 2009-05-25 2010-05-19 通过动态随机存储器体现静态随机存储器输出特性的装置及方法
EP10780730A EP2437267A4 (en) 2009-05-25 2010-05-19 DEVICE AND METHOD FOR DETERMINING SRAM OUTPUT CHARACTERISTICS FROM DRAMS
US13/118,287 US8422314B2 (en) 2009-05-25 2011-05-27 Device and method for achieving SRAM output characteristics from DRAMS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2009-0045298 2009-05-25
KR1020090045298A KR100940868B1 (ko) 2009-05-25 2009-05-25 디램으로 에스램 출력특성을 구현하는 장치 및 방법

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/118,287 Continuation US8422314B2 (en) 2009-05-25 2011-05-27 Device and method for achieving SRAM output characteristics from DRAMS

Publications (2)

Publication Number Publication Date
WO2010137819A2 WO2010137819A2 (ko) 2010-12-02
WO2010137819A3 true WO2010137819A3 (ko) 2011-03-03

Family

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PCT/KR2010/003151 WO2010137819A2 (ko) 2009-05-25 2010-05-19 디램으로 에스램 출력특성을 구현하는 장치 및 방법

Country Status (6)

Country Link
US (1) US8422314B2 (ko)
EP (1) EP2437267A4 (ko)
JP (1) JP5943250B2 (ko)
KR (1) KR100940868B1 (ko)
CN (1) CN102422359B (ko)
WO (1) WO2010137819A2 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5727948B2 (ja) * 2012-01-16 2015-06-03 株式会社東芝 半導体記憶装置
US9916098B2 (en) 2014-01-31 2018-03-13 Hewlett Packard Enterprise Development Lp Reducing read latency of memory modules
KR102373544B1 (ko) 2015-11-06 2022-03-11 삼성전자주식회사 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
US11379306B1 (en) 2021-07-29 2022-07-05 Bae Systems Information And Electronic System Integration Inc. Method for radiation hardening synchronous DRAM
US20240078016A1 (en) * 2022-09-06 2024-03-07 Luminous Computing, Inc. Computer architecture with disaggregated memory and high-bandwidth communication interconnects

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000065602A (ko) * 1999-04-07 2000-11-15 윤종용 데이터 입출력 버스의 전송 데이터율을 향상시키는 반도체 메모리장치 및 이를 구비하는 메모리 모듈
KR20020088652A (ko) * 2001-05-19 2002-11-29 (주)이엠엘에스아이 리프레쉬 동작을 제어할 수 있는 디램 셀을 이용한 에스램호환 메모리 장치
JP2003006041A (ja) * 2001-06-20 2003-01-10 Hitachi Ltd 半導体装置
JP2008257742A (ja) * 2008-05-29 2008-10-23 Renesas Technology Corp 半導体記憶装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586232B2 (ja) * 1977-09-21 1983-02-03 株式会社日立製作所 メモリ装置
JPS5715286A (en) * 1980-06-30 1982-01-26 Toshiba Corp Memory device
JPH05165731A (ja) * 1991-12-13 1993-07-02 Nec Corp 二重化記憶装置
US5926827A (en) * 1996-02-09 1999-07-20 International Business Machines Corp. High density SIMM or DIMM with RAS address re-mapping
JPH1011348A (ja) * 1996-06-24 1998-01-16 Ricoh Co Ltd Ｄｒａｍの制御装置およびそのｄｒａｍ
JPH11149416A (ja) * 1997-11-17 1999-06-02 Tamura Electric Works Ltd データ保証装置
US6046952A (en) * 1998-12-04 2000-04-04 Advanced Micro Devices, Inc. Method and apparatus for optimizing memory performance with opportunistic refreshing
JP4555416B2 (ja) * 1999-09-22 2010-09-29 富士通セミコンダクター株式会社 半導体集積回路およびその制御方法
JP4291476B2 (ja) * 1999-11-15 2009-07-08 Ｏｋｉセミコンダクタ株式会社 マイクロプロセッサ
US6445636B1 (en) 2000-08-17 2002-09-03 Micron Technology, Inc. Method and system for hiding refreshes in a dynamic random access memory
US6938133B2 (en) * 2001-09-28 2005-08-30 Hewlett-Packard Development Company, L.P. Memory latency and bandwidth optimizations
JP4318163B2 (ja) 2002-04-01 2009-08-19 株式会社ルネサステクノロジ 半導体記憶装置及びその制御方法
US7130229B2 (en) * 2002-11-08 2006-10-31 Intel Corporation Interleaved mirrored memory systems
US7194568B2 (en) * 2003-03-21 2007-03-20 Cisco Technology, Inc. System and method for dynamic mirror-bank addressing
US7454555B2 (en) * 2003-06-12 2008-11-18 Rambus Inc. Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device
US20050138276A1 (en) * 2003-12-17 2005-06-23 Intel Corporation Methods and apparatus for high bandwidth random access using dynamic random access memory
US7206245B2 (en) * 2005-04-28 2007-04-17 Infineon Technologies Ag Methods and apparatus for implementing standby mode in a random access memory
US7461216B2 (en) * 2006-02-23 2008-12-02 Hewlett-Packard Development Company, L.P. Memory controller
US7694093B2 (en) * 2007-04-27 2010-04-06 Hewlett-Packard Development Company, L.P. Memory module and method for mirroring data by rank

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000065602A (ko) * 1999-04-07 2000-11-15 윤종용 데이터 입출력 버스의 전송 데이터율을 향상시키는 반도체 메모리장치 및 이를 구비하는 메모리 모듈
KR20020088652A (ko) * 2001-05-19 2002-11-29 (주)이엠엘에스아이 리프레쉬 동작을 제어할 수 있는 디램 셀을 이용한 에스램호환 메모리 장치
JP2003006041A (ja) * 2001-06-20 2003-01-10 Hitachi Ltd 半導体装置
JP2008257742A (ja) * 2008-05-29 2008-10-23 Renesas Technology Corp 半導体記憶装置

Also Published As

Publication number Publication date
EP2437267A4 (en) 2013-01-23
US20110228613A1 (en) 2011-09-22
CN102422359B (zh) 2014-12-24
JP2012512496A (ja) 2012-05-31
EP2437267A2 (en) 2012-04-04
US8422314B2 (en) 2013-04-16
JP5943250B2 (ja) 2016-07-05
WO2010137819A2 (ko) 2010-12-02
CN102422359A (zh) 2012-04-18
KR100940868B1 (ko) 2010-02-09

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