WO2010098076A1 - Transistor du stockage, à grille d'isolation, et à effet de champ - Google Patents

Transistor du stockage, à grille d'isolation, et à effet de champ Download PDF

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WO2010098076A1
WO2010098076A1 PCT/JP2010/001193 JP2010001193W WO2010098076A1 WO 2010098076 A1 WO2010098076 A1 WO 2010098076A1 JP 2010001193 W JP2010001193 W JP 2010001193W WO 2010098076 A1 WO2010098076 A1 WO 2010098076A1
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region
storage
channel
impurity concentration
type
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Japanese (ja)
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沖野泰之
小野瀬秀勝
横山夏樹
大野俊之
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株式会社日立製作所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • the present invention relates to a storage type insulated gate field effect transistor (hereinafter simply referred to as storage type MOSFET).
  • Silicon carbide is a material that can reduce the loss of the FET because the breakdown electric field is about 10 times larger than that of Si, so that the drift layer that maintains the breakdown voltage can be made thin and high in concentration.
  • MOSFET which is one of power semiconductor elements using SiC
  • FIG. 1 This figure schematically shows the structure of the cross-sectional view shown in Patent Document 1 so that the cross-sectional view can be easily understood.
  • reference numeral 1 denotes an n + substrate serving as a drain region
  • 2 denotes an n ⁇ drift layer
  • 3 denotes a p base region
  • 4 denotes a p + contact region
  • 5 denotes an n + source region
  • 6 denotes an n ⁇ storage channel region
  • 7 is a gate insulating film
  • 8 is a gate electrode
  • 9 is an interlayer insulating film for electrically insulating the source / gate
  • 10 is a source electrode
  • 11 is a drain electrode.
  • the storage channel region 6 is depleted by the built-in potential with the p base region 3. As a result, no current flows in the storage channel region 6 and the transistor can be normally off.
  • the electric field strength in the interface vertical direction at the interface between the channel region and the gate insulating film is weaker than that of the MOSFET using the inversion layer. .
  • the force that attracts carriers to the interface is weak and is not easily affected by interface scattering. For this reason, channel mobility can be increased.
  • the on-resistance of the MOSFET is determined by the contact resistance between the source electrode and the source region, the source resistance, the channel resistance, the accumulation resistance, the JFET resistance, the drift resistance, the substrate resistance, and the contact resistance between the substrate and the drain electrode.
  • the proportion of channel resistance in the on-resistance is large, and may occupy more than half. Therefore, reducing the channel resistance leads to a reduction in on-resistance. Since the channel resistance is determined by the channel mobility and the carrier concentration, the on-resistance can be reduced by increasing the channel mobility.
  • the p base region 3 is formed by ion-implanting atoms such as Al into the n ⁇ drift layer 2.
  • SiC has a small diffusion coefficient of impurities, and a thermal diffusion method cannot be applied. For this reason, ion implantation with high energy is required, the crystal is damaged, and the crystallinity is deteriorated.
  • the storage channel region 6 is epitaxially grown on the p base region 3 whose crystallinity has deteriorated, the vicinity of the interface with the p base region 3 becomes an incomplete crystal including many crystal defects, and grows to a complete crystal. In order to achieve this, it is necessary to increase the film thickness.
  • the impurity concentration of the storage channel region 6 is preferably increased in order to increase the carrier concentration.
  • FIG. 11 shows the thickness of the depletion layer spreading to n-SiC when the donor impurity concentration of n-SiC is changed in a pn junction where the acceptor impurity concentration of p-SiC is 1 ⁇ 10 17 cm ⁇ 3. Is shown.
  • FIG. 12 is a graph showing an example of the relationship between the MOSFET breakdown voltage and the impurity concentration of the storage channel region made of SiC.
  • the concentration of the drift layer is 1 ⁇ 10 16 cm ⁇ 3 and the film thickness is 10 ⁇ m.
  • the on-resistance can be reduced by using the storage MOSFET as compared with the inversion MOSFET. However, it is desired to further reduce the on-resistance of the device while maintaining the normally-off characteristic.
  • the present invention has been made in view of the above points, and aims to further reduce the on-resistance while maintaining normally-off characteristics.
  • the present invention has the following basic structure. That is, the basic configuration of the first form is a drain region made of SiC of the first conductivity type, A drift layer made of SiC in contact with the drain region and having a first conductivity type and a lower impurity concentration than the drain region; A base region made of SiC of the second conductivity type provided in the drift layer; A source region made of SiC of a first conductivity type formed in the base region and having a higher impurity concentration than the drift layer; An accumulation channel region made of SiC of the first conductivity type epitaxially grown on the base region, the source region and the drift layer; A gate insulating film provided on the storage channel region; A gate electrode provided on the gate insulating film; A drain electrode connected to the drain region; A source electrode connected to at least the source region, The storage channel region is in contact with the gate insulating film in a region other than the first region, and a first region formed on the surface of each layer of the base region, the source region, and the drift layer
  • the impurity concentration of the second region is higher than the impurity concentration of the first region
  • the second region of the storage channel is depleted by a depletion layer extending from the base region and a depletion layer extending from the gate insulating film in a state where no voltage is applied to the gate electrode.
  • the storage channel region may be provided in a plurality of configurations.
  • a second mode according to the present invention is a mode in which the storage channel region is formed on a semiconductor substrate on which a semiconductor layer is epitaxially grown.
  • a drift layer, a base region, a source region, and the like are formed in advance on the semiconductor substrate.
  • the semiconductor substrate surface on which the drift layer, the base region, the source region, and the like are formed is basically a flat plate, and it is relatively easy to form the storage channel region and the like formed on the semiconductor substrate surface. is there.
  • the third form is a form in which the accumulation type channel region forms a groove on the surface of the semiconductor substrate, and is also formed on the surface of the groove. Since the groove surface is also used to form the storage channel region, it is useful for high integration.
  • the fourth form is a form in which the storage channel region is formed on the surface portion in the semiconductor substrate. Since the surface of the storage channel region is at the same position (level) as the surface of the semiconductor substrate for crystal growth, it is easy to form a gate insulating film formed on this surface.
  • the fifth form is a modification of the third form.
  • the storage channel region is formed in the semiconductor substrate, and the source region is formed so as to cover the surface in the thickness direction of the film constituting the storage channel region along the side wall of the groove.
  • An accumulation type channel region along the source region and the trench side wall is formed in the semiconductor substrate for crystal growth.
  • a gate insulating film can be formed along the semiconductor substrate surface.
  • the sixth mode includes a semiconductor region having the same conductivity type as these layers, including a part of the storage channel region and the drift layer, and a higher impurity concentration.
  • This semiconductor region having a high impurity concentration serves as a so-called accumulation region, and exhibits a low on-resistance as compared to the case without this region.
  • the storage channel second region has a depletion layer extending from the base region in a state where no voltage is applied to the gate electrode, Needless to say, the depletion layer extending from the gate insulating film is important. It should be noted that this depletion is sufficient to be set in accordance with the usual technical idea regarding the extension of the depletion layer in the field of semiconductor devices so far.
  • FIG. 1 is a cross-sectional view schematically showing a storage MOSFET according to a first embodiment of the present invention.
  • FIG. 2A is a cross-sectional view of the device showing the storage MOSFET according to the first embodiment of the present invention in the order of the manufacturing process.
  • FIG. 2B is a cross-sectional view of the device illustrating the storage MOSFET according to the first embodiment of the present invention in the order of the manufacturing process.
  • FIG. 2C is a cross-sectional view of the device illustrating the storage MOSFET according to the first embodiment of the present invention in the order of the manufacturing process.
  • FIG. 2D is a cross-sectional view of the device illustrating the storage MOSFET according to the first embodiment of the present invention in the order of the manufacturing process.
  • FIG. 2A is a cross-sectional view of the device showing the storage MOSFET according to the first embodiment of the present invention in the order of the manufacturing process.
  • FIG. 2B is a cross-sectional view of the device illustrating the
  • FIG. 2E is a cross-sectional view of the device illustrating the storage MOSFET according to the first embodiment of the present invention in the order of the manufacturing process.
  • FIG. 2F is a cross-sectional view of the device illustrating the storage MOSFET according to the first embodiment of the present invention in the order of the manufacturing process.
  • FIG. 3 is a sectional view schematically showing a storage MOSFET according to the second embodiment of the present invention.
  • FIG. 4A is a cross-sectional view of an apparatus showing storage MOSFETs according to Embodiment 2 of the present invention in the order of manufacturing steps.
  • FIG. 4B is a sectional view of the device showing the storage MOSFET according to the second embodiment of the present invention in the order of the manufacturing process.
  • FIG. 4C is a cross-sectional view of the device illustrating the storage MOSFET according to the second embodiment of the present invention in the order of the manufacturing process.
  • FIG. 4D is a cross-sectional view of the device illustrating the storage MOSFET according to the second embodiment of the present invention in the order of the manufacturing process.
  • FIG. 4E is a cross-sectional view of the device illustrating the storage MOSFET according to the second embodiment of the present invention in the order of the manufacturing process.
  • FIG. 4F is a cross-sectional view of the device illustrating the storage MOSFET according to the second embodiment of the present invention in the order of the manufacturing process.
  • FIG. 5 is a cross-sectional view schematically showing a storage MOSFET according to a third embodiment of the present invention.
  • FIG. 6A is a cross-sectional view of an apparatus showing storage MOSFETs according to Embodiment 3 of the present invention in the order of manufacturing steps.
  • FIG. 6B is a sectional view of the device showing the storage MOSFET according to the third embodiment of the present invention in the order of the manufacturing process.
  • FIG. 6C is a cross-sectional view of the device illustrating the storage MOSFET according to the third embodiment of the present invention in the order of the manufacturing process.
  • FIG. 6D is a cross-sectional view of the device illustrating the storage MOSFET according to the third embodiment of the present invention in the order of the manufacturing process.
  • FIG. 7 is a cross-sectional view schematically showing a storage MOSFET according to Embodiment 4 of the present invention.
  • FIG. 8A is a cross-sectional view of an apparatus showing storage type MOSFETs according to Embodiment 4 of the present invention in the order of manufacturing steps.
  • FIG. 8B is a cross-sectional view of an apparatus showing storage MOSFETs according to Embodiment 4 of the present invention in the order of manufacturing steps.
  • FIG. 8C is a cross-sectional view of an apparatus showing storage MOSFETs according to Embodiment 4 of the present invention in the order of manufacturing steps.
  • FIG. 8D is a cross-sectional view of the device illustrating the storage MOSFET according to the fourth embodiment of the present invention in the order of the manufacturing process.
  • FIG. 9 is a sectional view schematically showing a storage MOSFET according to the fifth embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing a method for manufacturing a storage MOSFET according to Embodiment 5 of the present invention.
  • FIG. 11 is a diagram showing the relationship between the donor impurity concentration and the depletion layer thickness in the SiC pn junction.
  • FIG. 12 is a graph showing the relationship between the impurity concentration of the channel region and the breakdown voltage in the conventional storage MOSFET.
  • FIG. 13 is a diagram showing a reference example of the film configuration of the storage channel region of the present invention and the film configuration of the conventional storage channel region.
  • FIG. 14 shows the electric field strength at the interface between the gate insulating film and the storage channel region when an electric field of 3 MV / cm is applied to the gate insulating film with respect to the film configurations of A, B, C, and D in FIG.
  • FIG. 15 is a cross-sectional view schematically showing a conventional storage MOSFET.
  • channel resistance there are two aspects to consider in order to reduce device resistance, that is, channel resistance, carrier concentration and carrier mobility.
  • carrier mobility there are a side surface of the electric field strength at the interface and a side surface of the crystallinity of the channel region. Therefore, when the electronic effect which is the object of the present invention is taken into consideration, (1) the carrier concentration is increased by increasing the impurity concentration in the region where carriers travel, and (2) the interface between the channel region and the gate insulating film.
  • the carrier concentration is increased by increasing the impurity concentration in the region where carriers travel
  • the interface between the channel region and the gate insulating film Consider three measures to increase the carrier mobility by weakening the electric field strength in the direction perpendicular to the interface, and (3) increasing the channel mobility by increasing the film thickness of the channel region. It is effective.
  • the storage MOSFET according to the present invention has a storage channel channel second in which the impurity concentration of the storage channel region is low in the storage channel first region on the base region side and carriers on the gate insulating film side travel. High density was set in the area.
  • the channel resistance can be reduced by any one of the three methods for reducing the channel resistance or by the appearance of a plurality of effects therein. . The details will be described below.
  • FIG. 13 shows an example of the film configuration in the storage channel region formed so that the threshold voltages of the storage MOSFETs are approximately the same. It is a comparative example for directly comparing the effects of the present invention.
  • Examples A and B and Examples C and D respectively illustrate an example of a basic storage channel region and a mode in which a second region is added thereto.
  • the film can take many configurations other than those shown here.
  • FIG. 13 is the distance from the interface between the gate oxide film and the channel region, and indicates the thickness of the channel region.
  • the region near the interface of Examples B and D is the second region.
  • the channel region is SiC, and typical examples of the dopant are nitrogen or phosphorus.
  • the figure shows the impurity concentration in each region. In the lower part of FIG. 13, examples of the thicknesses of the first and second regions in each example are shown.
  • the impurity concentration on the interface side of the channel region is increased.
  • Example A is a conventional example in which a channel region is formed at a single concentration
  • Example B is an example of the present invention.
  • the impurity concentration in the region where carriers travel that is, in the vicinity of the interface between the channel region and the gate insulating film, is higher in B than in A, and the carrier concentration in B is higher. That is, in Examples A and B in which the storage channel region is formed so that the threshold voltages are approximately the same, as in the example according to the present invention, the impurity concentration on the gate insulating film side of the storage channel region is increased. , The on-resistance can be further reduced.
  • the present invention is useful even when the storage channel region is thick.
  • a comparison of these examples is shown in film configuration examples C and D in FIG. In this case as well, both are examples in which the threshold voltages are approximately the same.
  • the film thickness is made thicker than the film configuration examples A and B at a single concentration.
  • a film that can further reduce the channel resistance can be realized as in the film configuration example D, for example.
  • FIG. 14 shows an example of the electric field intensity distribution in the direction perpendicular to the interface at the interface between the channel region and the gate insulating film when an electric field of 3 MV / cm is applied to the gate insulating film with respect to Examples A to D in FIG. Shown in The horizontal axis represents the distance from the interface between the storage channel region and the gate insulating film, and the vertical axis represents the electric field strength at this interface. Compared to Example A, Example B has a weaker electric field strength at the interface. Also in the comparison between Examples C and D, the electric field strength at the interface is weak.
  • the film thickness of the entire channel region is thick, the effect appears less than the comparison between Examples A and B.
  • the electric field strength at the interface between the storage channel region and the gate insulating film can be reduced when the same threshold voltage is used.
  • the film of Example B compared to Example A can provide a device having a lower channel resistance, that is, an on-resistance.
  • (1) the carrier concentration is increased by increasing the impurity concentration in the region where the carrier travels, and (2) the interface vertical direction at the interface between the channel region and the gate insulating film. It is possible to satisfy the conditions of increasing the channel mobility by reducing the electric field strength of the film and (3) increasing the channel mobility by increasing the film thickness of the channel region. Is shown.
  • the film thickness of the storage channel second region is 10 nm or more. Since the epitaxial growth rate of SiC is usually several ⁇ m / hour, the channel region can be formed with good controllability when the film thickness is 10 nm or more.
  • the premise is that the storage MOSFET realizes a normally-off state.
  • the depletion layer thickness spreading to the storage channel second region is not thicker than the film thickness of the storage channel second region, Cannot be normally off. From the relationship between the impurity concentration and the depletion layer thickness shown in FIG. 11, when the impurity concentration of the storage channel second region is 1 ⁇ 10 18 cm ⁇ 3 or less, the depletion layer thickness spreading to the storage channel second region Can be 10 nm or more, and there is an effect that normally-off can be maintained.
  • the storage channel layer configuration is preferably set within the following range for practical use. That is, the thickness of the storage channel layer is usually set in the range of 110 nm to 710 nm. For the purposes of the present invention, the film thickness is preferably in the range of 200 nm to 500 nm, practically.
  • the storage channel is formed by being divided into the first region and the second region. Each of these areas is formed with the following settings.
  • the first region of the storage channel (that is, the region farther from the interface between the semiconductor layer and the gate insulating film) has a film thickness of typically 100 nm to 700 nm and an impurity concentration of typically 5 ⁇ 10 14 cm ⁇ 3 to 5 ⁇ 10. It is set in the range of 16 cm ⁇ 3 .
  • the thickness is preferably 100 nm to 500 nm, and the impurity concentration is preferably in the range of 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 16 cm ⁇ 3 in terms of practical use.
  • the second region of the storage channel typically has a film thickness of 10 nm to 100 nm, and the impurity concentration is typically 1 ⁇ 10 16 cm ⁇ 3 to 2 It is set in the range of ⁇ 10 17 cm ⁇ 3 .
  • the impurity concentration is preferably in the range of 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 from a practical standpoint.
  • the difference in impurity concentration between the first and second regions is usually a difference of about 50% or more, preferably a difference of about one digit or more.
  • the channel length is in the range of about 0.5 ⁇ m to 2 ⁇ m. Nitrogen, phosphorus, or the like can be used as the impurity.
  • the depletion layer thickness spreading to the storage channel second region must be larger than the film thickness of the storage channel second region. That is, it is important that the second region of the storage channel is depleted by a depletion layer extending from the base region and a depletion layer extending from the gate insulating film in a state where no voltage is applied to the gate electrode. is there.
  • the first and second regions of the storage channel are set in consideration of the breakdown voltage of the device, the on-resistance, the extension of the depletion layer to be the storage type, and the like.
  • a drain region which is the main part of the present invention, has been described in detail, other parts related to the MOSFET may be configured according to the conventional storage MOSFET technology.
  • a drain region, a drift layer, a base layer, a base electrode, a source layer, a source electrode, a gate insulating film, and a gate electrode formed on a SiC substrate are set corresponding to the characteristics required for the MOSFET.
  • FIG. 1 is a cross-sectional view of the main part showing a first embodiment of a storage MOSFET of the present invention.
  • the main configuration of this example is as follows.
  • An n ⁇ type drift layer 2 (hereinafter abbreviated as “n ⁇ drift layer 2”) is laminated on an n + type ⁇ SiC substrate 1 (hereinafter abbreviated as “SiC substrate 1”).
  • a p-type base region 3 (hereinafter abbreviated as p-base region 3) is formed in a predetermined region in the surface layer portion of the n ⁇ drift layer 2, and an n + -type source region 5 (hereinafter referred to as “p-type base region 3”) is formed in the p-base region 3.
  • p + source region 5 a p + -type contact region 4 (hereinafter abbreviated as “p + contact region 4”) is formed in contact with the n + source region 5.
  • p + contact region 4 is formed in contact with the n + source
  • the surface portion including the p base region 3, the n + source region 5 and the n ⁇ drift layer 2 has an n ⁇ -type storage channel first region (hereinafter, abbreviated as n ⁇ storage type channel first region). 6) and an n-type storage channel second region (hereinafter abbreviated as an n-storage channel second region) 12 are formed.
  • a gate electrode 8 is disposed on the n storage channel second region 12 via a gate insulating film 7, and the gate electrode 8 is covered with an interlayer insulating film 9.
  • a source electrode 10 is formed so as to contact the p + contact region 4 and the n + source region 5, and a drain electrode 11 is formed on the lower surface of the n + -SiC substrate 1.
  • the most important feature of the structure of the present embodiment is that the impurity concentration of the n - storage channel second region 12 is higher than the impurity concentration of the n - storage channel first region 6.
  • a typical configuration of the storage channel region in this example is that the n - storage channel first region 6 has an impurity concentration of 3 ⁇ 10 15 cm ⁇ 3 , a film thickness of 200 nm, and an n-type storage channel first region.
  • the two regions 12 have an impurity concentration of 5 ⁇ 10 16 cm ⁇ 3 and a film thickness of 50 nm.
  • the planar configuration is a structure in which the p base regions 3 are repeatedly arranged as stripes or squares.
  • the operation of the storage MOSFET of this embodiment will be described.
  • a positive voltage is applied to the gate electrode 8 in a state where a voltage is applied between the drain electrode 11 and the source electrode 10
  • an electron accumulation layer is formed on the surface layer of the n accumulation channel second region 12.
  • a current flows through the source electrode 10 through the region 6 and the source region 5.
  • the n ⁇ type first region 6 of the storage channel has a lower resistance than the n type second region of the storage channel because the impurity concentration is lower.
  • the ratio of the channel resistance to the surface layer of the n-type second region 12 of the storage channel is large. For this reason, the on-resistance of the entire device can be reduced by adjusting the channel resistance of the n-type second region 12 of the storage channel.
  • the second region of the storage channel is set to be depleted by a depletion layer extending from the base region and a depletion layer extending from the gate insulating film in a state where no voltage is applied to the gate electrode. Therefore, when the voltage applied to the gate electrode 8 is removed, the second region 12 of the storage channel is completely depleted by the depletion layer extending from the base region 3, and the drain electrode 11 and the source electrode 10 are electrically connected. Isolated and exhibits a switching function.
  • the storage channel region is formed by two channel regions of the first region 6 and the second region 12, so that (1) the channel region is compared with the case where the channel region is formed at a single concentration.
  • the channel resistance can be reduced by three effects: (2) the electric field strength at the interface between the channel region and the gate insulating film is weak, and (3) the channel region is thick. Indicates on-resistance.
  • FIG. 2A to 2F are schematic cross-sectional views for explaining a process for forming the storage MOSFET according to the first embodiment.
  • a substrate on which an n ⁇ drift layer 2 is laminated on an SiC substrate 1 is prepared.
  • an ion implantation mask material 20 is patterned into the n ⁇ drift layer 2 formed on the SiC substrate 1, and Al21 is ion-implanted to form the p-type base region 3 (step a: FIG. 2A).
  • the ion implantation conditions at this time are a dose of 3 ⁇ 10 13 cm ⁇ 2 .
  • the p-type base region 3 is formed with a doping concentration of about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and a thickness of about 0.5 to 3.0 ⁇ m.
  • the ion implantation mask material 22 is patterned on the surfaces of the n ⁇ drift layer 2 and the p-type base region 3, and Al 23 is ionized to form the p + contact region 4. Inject (step b: FIG. 2B).
  • n + source region 5 In order to form the n + source region 5 by patterning the ion implantation mask material 24 on the surfaces of the n ⁇ layer 2, the p-type base region 3 and the p + contact region 4 after removing the ion implantation mask material 22. Nitrogen 25 is ion-implanted (step c: FIG. 2C).
  • the n ⁇ -type first region of the storage channel is formed on the surface layer portions of the n ⁇ drift layer 2, the p base region 3, the p + contact region 4 and the n + source region 5 by LPCVD (Low Pressure Chemical Vapor Deposition). 6 and the n-type second region 12 of the storage channel are epitaxially grown.
  • the growth temperature is 1600 ° C.
  • hydrogen is used as the carrier gas
  • monosilane and propane are used as the source gas
  • nitrogen is used as the dopant gas.
  • the growth pressure is 12 kPa
  • the hydrogen flow rate is 40 slm
  • the monosilane flow rate is 6.67 sccm
  • the propane flow rate is 3.33 sccm.
  • the nitrogen flow rate after the start of growth was set to 0.07 sccm, and after 200 seconds had elapsed, the nitrogen flow rate was set to 2 sccm and grown for another 50 seconds, so that an impurity concentration of 3 ⁇ 10 15 cm ⁇ 3 and a film thickness of 200 nm was obtained.
  • the n ⁇ -type first region 6 and the storage channel n-type second region 12 having an impurity concentration of 5 ⁇ 10 16 cm ⁇ 3 and a film thickness of 50 nm can be formed continuously (step d: FIG. 2D). ).
  • the structure of the storage channel region is as shown by the film structure B in FIG.
  • the gate insulating film 7 is formed by thermal oxidation at about 1200 ° C., and the gate electrode 8 is formed from polycrystalline silicon. Thereafter, an insulating interlayer 9 is formed on the surface of the gate electrode 8 (step e: FIG. 2E).
  • the etching mask material 26 is patterned on the interlayer insulating film 9, and the interlayer insulating film 9, the gate insulating film 7, the storage channel n-type second region 12 and the storage channel n - type first region 6 are dry-etched.
  • the drain electrode 11 is formed on the surface of the n + substrate 1 after removing the mask material 26.
  • the source electrode 10 is formed in a predetermined contact window from which the p + contact region 4 and the n + source region 5 are exposed, whereby the storage type MOSFET shown in FIG. 1 is completed.
  • the film thickness range of the first region in the above-mentioned storage channel 100 nm to 700 nm, and the impurity concentration range of 5 ⁇ 10 14 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the main example is the film configuration example of the storage channel shown in Table 1.
  • FIG. 3 is a cross-sectional view of the main part showing a second embodiment of the storage MOSFET of the present invention.
  • This example is an example of a trench type storage MOSFET.
  • the first embodiment is a planar MOSFET, the trench type is effective for increasing the degree of integration and reducing the on-resistance.
  • the main configuration of this example is as follows.
  • An n ⁇ drift layer 2 is stacked on the n + SiC substrate 1.
  • a p base region 3 is formed in a predetermined region in the surface layer portion of the n ⁇ drift layer 2, and a p + contact region 4 and an n + source region 5 are formed in the p base region 3.
  • the p ⁇ base region 3 and the n + source region 5 are in contact with the side wall, and the n ⁇ drift layer 2 has a depth such that the lower end reaches a region other than the p base region 3 and the n + source region 5.
  • a groove 13 is formed.
  • an n ⁇ storage channel first region 6 and an n storage channel second region 12 are formed on the surface portion of the trench 13 so as to be connected to the n + source region 5.
  • the second region of the storage channel is set to be depleted by a depletion layer extending from the base region and a depletion layer extending from the gate insulating film in a state where no voltage is applied to the gate electrode. Needless to say.
  • a gate electrode 8 is disposed on the surface portion of the n-type second region 12 of the storage channel via the gate insulating film 7.
  • the gate electrode 8 is covered with an interlayer insulating film 9.
  • a source electrode 10 is formed so as to be in contact with the p + contact region 4 and the n + source region 5, and a drain electrode 11 is formed on the lower surface of the n + -SiC substrate 1.
  • the same part as FIG. 1 was shown with the same code
  • the channel region is formed along the groove 13 perpendicular to the SiC substrate surface. Therefore, the unit cell can be made smaller as compared with the first embodiment in which the channel region is formed in parallel to the substrate surface. For this reason, as compared with the example of the first embodiment, the degree of integration of the semiconductor device is increased, and the low unit resistance is exhibited due to the small unit cell.
  • the storage channel second region 12 is completely depleted by the depletion layer extending from the base region 3, and the drain electrode 11 and the source electrode 10 are electrically insulated, and switching is performed. Indicates function.
  • FIG. 4A to 4F are schematic cross-sectional views for explaining a process for forming the storage MOSFET according to the second embodiment.
  • a substrate in which an n ⁇ drift layer 2 is laminated on an n + type SiC substrate 1 (hereinafter abbreviated as SiC substrate 1) is prepared.
  • SiC substrate 1 n + type SiC substrate 1
  • Al27 is ion-implanted (step a: FIG. 4A).
  • the ion implantation conditions at this time are a dose of 3 ⁇ 10 13 cm ⁇ 2 .
  • the p base region 3 is formed with a doping concentration of about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and a thickness of about 0.5 to 3.0 ⁇ m.
  • the ion implantation mask material 28 is patterned in the p base region 3 and Al 29 is ion implanted to form the p + contact region 4 (step b: FIG. 4B).
  • the ion implantation mask material 30 is patterned in the p + contact region 4, and nitrogen 31 is ion implanted to form the n + source region 5 (step c: FIG. 4C).
  • step d After removing the ion implantation mask material 30, heat treatment is performed at 1700 ° C. in order to activate the implanted Al and nitrogen. After the heat treatment, the etching mask material 32 is patterned on the p + contact region 4 and the n + source region 5, and the trench 13 is formed by dry etching (step d: FIG. 4D).
  • the specification of the trench is set in consideration of the degree of device integration. Usually, a width of several ⁇ m is frequently used as the width of the trench.
  • the depth of the trench is of course set in consideration of the thickness of the semiconductor layer to be laminated, etc., but most are about 1 ⁇ m to 2 ⁇ m.
  • n ⁇ storage channel first region 6 and n storage channel second region 12 are formed on the surface layers of n ⁇ layer 2, p base region 3, p + contact region 4 and n + source region 5 by LPCVD. Epitaxially grow.
  • the growth temperature is 1600 ° C.
  • hydrogen is used as the carrier gas
  • monosilane and propane are used as the source gas
  • nitrogen is used as the dopant gas.
  • the growth pressure is 12 kPa
  • the hydrogen flow rate is 40 slm
  • the monosilane flow rate is 6.67 sccm
  • the propane flow rate is 3.33 sccm.
  • the nitrogen flow rate after the start of growth was set to 0.07 sccm, and after 200 seconds, the nitrogen flow rate was set to 2 sccm, and the growth was further performed for 50 seconds, so that the concentration shown in the film configuration B of FIG. 13 was 3 ⁇ 10 15 cm ⁇ 3 ,
  • the n - storage channel first region 6 having a film thickness of 200 nm and the n - storage channel second region 12 having a concentration of 5 ⁇ 10 16 cm ⁇ 3 and a film thickness of 50 nm can be continuously formed (step e). : FIG. 4E).
  • the gate insulating film 7 is formed by thermal oxidation at about 1200 ° C., and the gate electrode 8 is formed from polycrystalline silicon. Thereafter, an insulating interlayer 9 is formed on the surface of the gate electrode 8 (step f: FIG. 4F). Subsequent steps are the same as step f of the first embodiment, and a contact window in which the p + contact region 4 and the n + source region 5 are exposed is opened. Thereafter, the drain electrode 11 is formed on the surface of the n + substrate 1. Then, by forming the source electrode 10 in a predetermined contact window where the p + contact region 4 and the n + source region 5 are exposed, the storage type MOSFET of Example 2 shown in FIG. 3 is completed.
  • the film thickness range of the first region in the above-mentioned storage channel 100 nm to 700 nm, and the impurity concentration range, 5 ⁇ 10 14 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the breakdown voltage of the device and the on-state of the second region in the storage channel are within a range of 10 nm to 100 nm and an impurity concentration range of 1 ⁇ 10 16 cm ⁇ 3 to 2 ⁇ 10 17 cm ⁇ 3. It is set in consideration of resistance, elongation of a depletion layer to be a storage type, and the same characteristics as described above can be obtained. By applying the storage channel film configuration example shown in Table 1, the same characteristics can be obtained.
  • FIG. 5 is a cross-sectional view of the main part showing a third embodiment of the storage MOSFET of the present invention.
  • the manufacturing process in the first and second embodiments is simplified.
  • the same parts as those in the previous examples are indicated by the same reference numerals.
  • Example 1 and Example 2 after the heat treatment at 1700 ° C. for activating the impurity, the n ⁇ storage channel first region 6 and the n storage channel second region 12 were epitaxially grown. Therefore, the p + contact region 4 and the n + source region 5 must be formed first. Therefore, when the contact window is opened on the p + contact region 4 and the n + source region 5, it is necessary to dry-etch the n - storage channel first region 6 and the n storage channel second region 12. However, in this process, the end point of dry etching cannot be determined, so that there is a problem that it takes time to set conditions.
  • the step of opening a contact window on the p + contact region 4 and the n + source region 5 is a step of dry etching the insulating film on SiC.
  • This process has an advantage that the process can be simplified because the end point can be easily determined because of the dry etching of the insulating layer.
  • FIG. 6A to 6D are schematic cross-sectional views for explaining a process for forming the storage MOSFET of the third embodiment.
  • the p base region 3 is formed in the n ⁇ drift layer 2 formed on the SiC semiconductor substrate.
  • the n ⁇ storage channel first region 6 and the n storage channel second region 12 are epitaxially grown on the surface portions of the n ⁇ layer 2 and the p base region 3 by LPCVD.
  • the growth temperature is 1600 ° C.
  • hydrogen is used as the carrier gas
  • monosilane and propane are used as the source gas
  • nitrogen is used as the dopant gas.
  • the growth pressure is 12 kPa
  • the hydrogen flow rate is 40 slm
  • the monosilane flow rate is 6.67 sccm
  • the propane flow rate is 3.33 sccm.
  • the nitrogen flow rate after the start of growth was set to 0.07 sccm, and after 200 seconds, the nitrogen flow rate was set to 2 sccm, and the growth was further performed for 50 seconds, so that the concentration shown in the film configuration B of FIG. 13 was 3 ⁇ 10 15 cm ⁇ 3
  • the n - storage type channel first region 6 having a film thickness of 200 nm and the n - storage type channel second region 12 having a concentration of 5 ⁇ 10 16 cm ⁇ 3 and a film thickness of 50 nm can be continuously formed (step a). : FIG. 6A).
  • the ion implantation mask material 33 is patterned in the n-storage channel second region 12, and Al 34 is ion-implanted to form the p + contact region 4 (step b: FIG. 6B).
  • Step c FIG. 6C.
  • a gate insulating film 7, a gate electrode 8, and an interlayer insulating film 9 are formed in the same manner as in FIG.
  • an etching mask material 37 is patterned on the interlayer insulating film 9. Using this pattern, the interlayer insulating film 9 and the gate insulating film 7 are processed by dry etching to form a contact window in which the p + contact region 4 and the n + source region 5 are exposed.
  • the contact window can be opened only by the dry etching of the insulating film, the end point of the dry etching can be determined, and the process is easy (process d: FIG. 6D).
  • the subsequent steps are not shown in the figure, but are ordinary steps. That is, the drain electrode 11 is formed on the surface of the n + substrate 1, and the source electrode 10 is formed in a predetermined contact window from which the p + contact region 4 and the n + source region 5 are exposed, as shown in FIG.
  • the storage MOSFET of Example 3 is completed.
  • the film thickness range of the first region in the above-mentioned storage channel 100 nm to 700 nm, and the impurity concentration range, 5 ⁇ 10 14 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the breakdown voltage of the device and the on-state of the second region in the storage channel are within a range of 10 nm to 100 nm and an impurity concentration range of 1 ⁇ 10 16 cm ⁇ 3 to 2 ⁇ 10 17 cm ⁇ 3. It is set in consideration of resistance, elongation of a depletion layer to be a storage type, and the same characteristics as described above can be obtained.
  • the storage channel film configuration example shown in Table 1 the same characteristics can be obtained.
  • FIG. 7 is a cross-sectional view of the main part showing a fourth embodiment of the storage type MOSFET of the present invention. This simplifies the process for the trench type storage MOSFET.
  • the step of forming the p + contact region 4 and the n + source region 5 after epitaxially growing the n ⁇ storage channel first region 6 and the n storage channel second region 12 in the same manner as in the third embodiment is a trench type storage type. Applies to MOSFET. Similar to the third embodiment, the process of opening the contact window on the p + contact region 4 and the n + source region 5 is a process of dry etching the insulating film on the SiC, so that the end point can be determined. There is an effect that the process can be simplified as compared with the second embodiment which cannot. Further, since the present embodiment is a trench type, the degree of integration of unit cells is increased and the on-resistance of the device can be reduced as compared with the planar type of the third embodiment.
  • the other configuration and manufacturing method are the same as those in the previous examples.
  • the specification of the trench is the same as that in the above-described example, and is set in consideration of the degree of device integration. Usually, a width of several ⁇ m is frequently used as the width of the trench.
  • the depth of the trench is of course set in consideration of the thickness of the semiconductor layer to be laminated, etc., but most are about 1 ⁇ m to 2 ⁇ m.
  • FIG. 8A to 8D are schematic processes for forming the storage MOSFET of the fourth embodiment.
  • an etching mask material 38 is patterned on the p base region 3, and the trench 13 is formed by dry etching (step a: FIG. 8A). ).
  • the n ⁇ storage type channel first region 6 and the n storage type channel second region 12 are epitaxially grown on the surface portions of the n ⁇ layer 2 and the p base region 3 by LPCVD.
  • the growth temperature is 1600 ° C.
  • hydrogen is used as the carrier gas
  • monosilane and propane are used as the source gas
  • nitrogen is used as the dopant gas.
  • the growth pressure is 12 kPa
  • the hydrogen flow rate is 40 slm
  • the monosilane flow rate is 6.67 sccm
  • the propane flow rate is 3.33 sccm.
  • the nitrogen flow rate after the start of growth was set to 0.07 sccm, and after 200 seconds, the nitrogen flow rate was set to 2 sccm, and the growth was further performed for 50 seconds, so that the concentration shown in the film configuration B of FIG. 13 was 3 ⁇ 10 15 cm ⁇ 3 ,
  • the n - storage channel first region 6 having a film thickness of 200 nm and the n - storage channel second region 12 having a concentration of 5 ⁇ 10 16 cm ⁇ 3 and a film thickness of 50 nm can be continuously formed (step b). : FIG. 8B).
  • the ion implantation mask material 39 is patterned in the n-storage channel second region 12, and Al 40 is ion-implanted to form the p + contact region 4 (step c: FIG. 8C).
  • the ion implantation mask material 41 is patterned in the p + contact region 4 and the n storage channel second region 12, and nitrogen 42 is ion implanted to form the n + source region 5 (process) d: FIG. 8D).
  • heat treatment is performed at 1700 ° C. in order to activate the implanted Al and nitrogen.
  • a gate insulating film 7, a gate electrode 8, and an interlayer insulating film 9 are formed in the same manner as in FIG. Then, the interlayer insulating film 9 and the gate insulating film 7 are processed by dry etching to form a contact window in which the p + contact region 4 and the n + source region 5 are exposed. Since the contact window can be opened only by dry etching of the insulating film, the process is easy. Thereafter, the drain electrode 11 is formed on the surface of the n + substrate 1, and the source electrode 10 is formed in a predetermined contact window where the p + contact region 4 and the n + source region 5 are exposed, as shown in FIG. The storage MOSFET of Example 4 is completed.
  • the film thickness range of the first region in the above-mentioned storage channel 100 nm to 700 nm, and the impurity concentration range, 5 ⁇ 10 14 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the breakdown voltage of the device and the on-state of the second region in the storage channel are within a range of 10 nm to 100 nm and an impurity concentration range of 1 ⁇ 10 16 cm ⁇ 3 to 2 ⁇ 10 17 cm ⁇ 3.
  • the characteristics equivalent to the above can be obtained in a setting that takes into account the resistance and the elongation of the depletion layer that should be the storage type. The same characteristics can be obtained by applying the storage channel film configuration example shown in Table 1 above.
  • FIG. 9 is a cross-sectional view of the main part showing a fifth embodiment of the storage type MOSFET of the present invention.
  • This example is a configuration example in which the on-resistance of the device can be further reduced as compared with the previous examples.
  • this example is a form in which the accumulation resistance and thus the on-resistance are further reduced by making the impurity concentration of the accumulation region higher than that of the drift layer or the storage channel region. That is, in the first and third embodiments, the accumulation resistance increases because the accumulation channel has the n ⁇ -type first region 6 in the accumulation region. However, in this embodiment, for example, nitrogen is ion-implanted into the accumulation region to increase the impurity concentration, thereby suppressing an increase in the accumulation resistance and further reducing the on-resistance.
  • FIG. 10 is a cross-sectional view showing a schematic process for forming the storage MOSFET of the fifth embodiment. 6A and 6B shown in the third embodiment, the p base region 3, the storage channel n - type first region 6, the storage channel n-type second region 12 and the p + contact region 4 are formed. Form. At the same time when the n + source region 5 is formed, the n + type accumulation region 45 is formed. Therefore, the ion implantation mask material 43 is patterned in the p + contact region 4 and the storage channel n-type second region 12, and nitrogen 44 is ion-implanted (step a: FIG. 10).
  • the n + source region 5 and the n + type accumulation region 45 are formed at the same time, this can be realized with the same number of steps as in the third embodiment.
  • the n + -type accumulation region typically uses a depth of about 300 nm to 500 nm, but is set in consideration of the breakdown voltage of the device.
  • the number of processes for forming the accumulation region 45 does not increase, and an on-resistance lower than that of the third embodiment can be realized with the same number of processes as the third embodiment.
  • the breakdown voltage and on-resistance of the device are basically determined in the range of the first region in the storage channel and the range of the impurity concentration, and further in the range of the second region in the film thickness and impurity concentration.
  • the setting is made in consideration of the elongation of the depletion layer to be the storage type, and the same characteristics as described above can be obtained.
  • a drain region made of SiC of the first conductivity type A drift layer made of SiC in contact with the drain region and having a first conductivity type and a lower impurity concentration than the drain region; A base region made of SiC of the second conductivity type provided in the drift layer; A source region made of SiC of a first conductivity type formed in the base region and having a higher impurity concentration than the drift layer; An accumulation channel region made of SiC of the first conductivity type epitaxially grown on the base region, the source region and the drift layer; A gate insulating film provided on the storage channel region; A gate electrode provided on the gate insulating film; A drain electrode connected to the drain region; A source electrode connected to at least the source region, The storage channel region is in contact with the gate insulating film in a region other than the first region, and a first region formed on the surface of each layer of the base region, the source region, and the drift layer or a part of the surface.
  • the impurity concentration of the second region is higher than the impurity concentration of the first region
  • the second region of the storage channel is depleted by a depletion layer extending from the base region and a depletion layer extending from the gate insulating film in a state where no voltage is applied to the gate electrode.
  • a drain region made of SiC of the first conductivity type (2) a drain region made of SiC of the first conductivity type; A drift layer made of SiC in contact with the drain region and having a first conductivity type and a lower impurity concentration than the drain region; A base region made of SiC of the second conductivity type provided in the drift layer; A storage channel region epitaxially grown on the base region and the drift layer and made of first conductivity type SiC; A source region made of SiC having a first conductivity type and a higher impurity concentration than the drift layer formed in the base region in contact with a side surface of the storage channel region; A gate insulating film provided on the storage channel region; A gate electrode provided on the gate insulating film; A drain electrode connected to the drain region; A source electrode connected to at least the source region,
  • the storage channel region has a first region formed on the base region and the drift layer, and a second region in contact with the gate insulating film in a region other than the first region, The impurity concentration of the second region is
  • a drain region made of SiC of the first conductivity type A drift layer made of SiC in contact with the drain region and having a first conductivity type and a lower impurity concentration than the drain region; A base region made of SiC of the second conductivity type provided in the drift layer; A source region made of SiC having a first conductivity type and a higher impurity concentration than the drift layer provided on the base region; A groove provided in the drift layer so as to be in contact with the side walls of the base region and the source region and have a lower end reaching a semiconductor region other than the base region and the source region; A storage channel region epitaxially grown at least on the surface of the groove and made of first conductivity type SiC; A gate insulating film provided in contact with the storage channel region; A gate electrode provided in contact with the gate insulating film; A drain electrode connected to the drain region; A source electrode connected to at least the source region,
  • the storage channel region includes a first region formed on the surface of the groove, and a second region that is a region other than the first
  • the groove is provided in the drift layer so as to be in contact with the side wall of the base region and have a lower end reaching a region other than the base region.
  • a storage channel region epitaxially grown on the surface of the groove and made of first conductivity type SiC;
  • the source region is configured as a SiC region having a higher impurity concentration than the drift layer formed on the side surface of the storage channel region and the upper surface of the base region,
  • the storage type insulated gate field effect transistor, wherein the gate insulating film is formed on the surface of the storage type channel region and the side surface of the source region.
  • a storage type insulated gate field effect transistor according to (2) A part or all of the first region and the second region of the storage channel other than the base region have a higher impurity concentration than the second region of the first channel and the storage channel.
  • n + type SiC substrate 1: n + type SiC substrate, 2: n ⁇ type drift layer, 3: p type base region, 4: p + type contact region, 5: n + type source region, 6: n ⁇ type first of accumulation type channel Region 7: Gate insulating film 8: Gate electrode 10: Source electrode 11: Drain electrode 12: Storage channel n-type second region 45: n + -type accumulation region

Abstract

La présente invention concerne un transistor MOSFET du type à stockage dans lequel une résistance à l'état passant peut être réduite davantage que dans des résistances à l'état passant classiques tout en assurant le maintien des caractéristiques à l'état bloqué. Le transistor MOSFET du type à stockage comporte une zone de drain SiC de type n+; une couche de dérive SiC de type n- en contact avec la zone de drain de type n+; une zone de base SiC de type p dans la dans la couche de mobilité de type n- ; et une couche de source SiC de type n+ dans la zone de base de type p ; et une zone de canal de stockage SiC de type n- formée sur des parties de couche superficielle de la région de base de type p, de la zone de source de type n+, et de la couche de mobilité de type n-. Un film d'isolation de grille est prévu sur la zone de canal de type à stockage. La zone de canal de stockage comporte une première zone qui est prévue sur la zone de base de type p et présente une épaisseur prédéterminée, et une seconde zone qui la région distincte de la première zone. La concentration d'impuretés de la seconde zone est supérieure à celle de la première zone.
PCT/JP2010/001193 2009-02-24 2010-02-23 Transistor du stockage, à grille d'isolation, et à effet de champ WO2010098076A1 (fr)

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JP4796667B2 (ja) * 2009-11-17 2011-10-19 パナソニック株式会社 半導体素子及びその製造方法
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JP2012134492A (ja) * 2010-12-17 2012-07-12 General Electric Co <Ge> 半導体デバイスおよびその製造方法
US8847238B2 (en) 2012-11-09 2014-09-30 Panasonic Corporation Semiconductor device which can withstand high voltage or high current and method for fabricating the same
JP5526291B1 (ja) * 2012-11-09 2014-06-18 パナソニック株式会社 半導体装置及びその製造方法
WO2014073127A1 (fr) * 2012-11-09 2014-05-15 パナソニック株式会社 Dispositif à semi-conducteurs et son procédé de fabrication
EP2835833A3 (fr) * 2013-08-05 2015-04-15 Seoul Semiconductor Co., Ltd. Transistor à effet de champ à base de nitrure et son procédé de fabrication
EP2843708A1 (fr) * 2013-08-28 2015-03-04 Seoul Semiconductor Co., Ltd. Transistors à base de nitrure et procédés de fabrication de celui-ci
WO2019125600A1 (fr) * 2017-12-21 2019-06-27 Cree, Inc. Dispositifs mosfet de puissance au carbure de silicium et procédés associés
US10424660B2 (en) 2017-12-21 2019-09-24 Cree, Inc. Power silicon carbide based MOSFET transistors with improved short circuit capabilities and methods of making such devices
JP2021507531A (ja) * 2017-12-21 2021-02-22 クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． パワー・シリコン・カーバイドｍｏｓｆｅｔデバイス及び関連する方法
US11164967B2 (en) 2017-12-21 2021-11-02 Cree, Inc. Power silicon carbide based MOSFET transistors with improved short circuit capabilities and methods of making such devices
JP7254083B2 (ja) 2017-12-21 2023-04-07 ウルフスピード インコーポレイテッド パワー・シリコン・カーバイドｍｏｓｆｅｔデバイス及び関連する方法

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