WO2010097830A1 - 半導体スタック、および、それを用いた電力変換装置 - Google Patents

半導体スタック、および、それを用いた電力変換装置 Download PDF

Info

Publication number
WO2010097830A1
WO2010097830A1 PCT/JP2009/000779 JP2009000779W WO2010097830A1 WO 2010097830 A1 WO2010097830 A1 WO 2010097830A1 JP 2009000779 W JP2009000779 W JP 2009000779W WO 2010097830 A1 WO2010097830 A1 WO 2010097830A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
multilayer substrate
electrolytic capacitors
semiconductor
semiconductor modules
Prior art date
Application number
PCT/JP2009/000779
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
龍田利樹
木下雅博
Original Assignee
東芝三菱電機産業システム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東芝三菱電機産業システム株式会社 filed Critical 東芝三菱電機産業システム株式会社
Priority to PCT/JP2009/000779 priority Critical patent/WO2010097830A1/ja
Priority to MX2011008610A priority patent/MX2011008610A/es
Priority to KR1020117018084A priority patent/KR101189017B1/ko
Priority to CN200980157677.3A priority patent/CN102326326B/zh
Priority to JP2011501344A priority patent/JP5438752B2/ja
Priority to CA2751034A priority patent/CA2751034C/en
Publication of WO2010097830A1 publication Critical patent/WO2010097830A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to a semiconductor stack and a power converter for a three-phase rotating electrical machine using the same.
  • a semiconductor stack used in a conventional power converter is composed of a multilayer substrate, a plurality of switching elements, and an electrolytic capacitor (see, for example, Patent Document 1).
  • the laminated substrate is configured by laminating a positive-side conductor plate and a negative-side conductor plate via an insulating plate.
  • the positive electrode side terminal and the negative electrode side terminal of each switching element are connected to the positive electrode side conductor plate and the negative electrode side conductor plate of the multilayer substrate, respectively.
  • the positive electrode side terminal and the negative electrode side terminal of the electrolytic capacitor are connected to the positive electrode side conductor plate and the negative electrode side conductor plate of the multilayer substrate, respectively.
  • the plurality of switching elements are mounted in rows in the vertical direction on the surface of the multilayer substrate. Further, the electrolytic capacitor is disposed on an extension of the row of the plurality of switching elements.
  • the electrolytic capacitors are arranged on the extension of the row of the plurality of switching elements, the distance between each switching element and the electrolytic capacitor is not uniform. Therefore, a large current flows through the switching element close to the electrolytic capacitor, and the current between the switching elements becomes unbalanced.
  • the semiconductor stack according to the present invention is insulated from the first conductor plate, the second conductor plate, and the third conductor plate on which the first electrode, the second electrode, and the third electrode are respectively formed.
  • a plurality of semiconductor modules arranged in a row on one surface of the multilayer substrate and connected to the first electrode, the second electrode, and the third electrode;
  • a plurality of first electrolytic capacitors arranged on the one surface of the multilayer substrate in a row parallel to the rows of the plurality of semiconductor modules and connected to the first electrode and the second electrode;
  • the power converter device using the three-phase rotary electric machine which concerns on this invention is the 1st conductor board in which the 1st electrode, the 2nd electrode, and the 3rd electrode were each formed, 2nd A laminated substrate in which a conductor plate and a third conductor plate overlap with each other via an insulating plate, and are arranged in a row on one surface of the laminated substrate, and the first electrode, the second electrode, and the third electrode A plurality of semiconductor modules connected to each other, and arranged on the one surface of the multilayer substrate in a row parallel to the row of the plurality of semiconductor modules, and connected to the first electrode and the second electrode A plurality of first electrolytic capacitors and a plurality of first electrolytic capacitors disposed on the one surface of the multilayer substrate in the same row as the plurality of first electrolytic capacitors and connected to the second electrode and the third electrode; 2 electrolytic capacitor and the above laminated Disposed on the other surface of the plate, the first electrode, and a plurality of
  • the semiconductor stack according to the present invention can improve the current balance between the semiconductor modules.
  • 1 is a front perspective view of a semiconductor stack according to a first embodiment of the present invention.
  • 1 is an exploded perspective view of a stacked substrate of a semiconductor stack according to a first embodiment of the present invention.
  • 1 is a perspective view of a stacked substrate of a semiconductor stack according to a first embodiment of the present invention. It is a figure which shows a part of circuit structure of the semiconductor stack concerning the 1st Embodiment of this invention.
  • SYMBOLS 1 ... Semiconductor stack, 2 ... Laminated substrate, 3 ... Semiconductor module, 4 ... Electrolytic capacitor, 5 ... Fuse, 6 ... Cooling fin, 7 ... DC side electrode, 21 ... 1st conductor plate, 22 ... 2nd conductor plate, 23: Third conductor plate, 24: Insulating plate, 25: Connection hole, 26: Longitudinal direction of the laminated conductor, 27: Short direction of the laminated conductor
  • FIG. 1 is a front perspective view of a semiconductor stack according to the present embodiment.
  • FIG. 2 is an exploded perspective view of the stacked substrate of the semiconductor stack according to the present embodiment.
  • FIG. 3 is a perspective view of the laminated substrate of the semiconductor stack according to the present embodiment.
  • FIG. 4 is a diagram showing a part of the circuit configuration of the semiconductor stack according to the present embodiment.
  • the semiconductor stack 1 is configured by mounting a semiconductor module 3, an electrolytic capacitor 4, a fuse 5, and a cooling fin 6 on the surface of a multilayer substrate 2.
  • the circuit of the semiconductor stack 1 includes eight semiconductor modules 3a to 3h, twelve electrolytic capacitors 4a to 4m, twelve fuses 5a to 5m, and three DC-side electrodes 7 (P-phase electrode 7a and C-phase electrode). 7b and N-phase electrode 7c).
  • the semiconductor modules 3a and 3b are connected to the P-phase electrode 7a, the C-phase electrode 7b, and the N-phase electrode 7c.
  • the semiconductor modules 3a and 3b are connected in parallel to each other.
  • Electrolytic capacitors 4a-4c are connected to P-phase electrode 7a and C-phase electrode 7b, and are connected in parallel to each other.
  • Electrolytic capacitors 4d-4f are connected to C-phase electrode 7b and N-phase electrode 7c, and are connected in parallel to each other.
  • the fuse 5a is connected in series to the P-phase electrode 7a, and the fuse 5b is connected in series to the N-phase electrode 7c.
  • the fuses 5a and 5b are provided to protect the semiconductor modules 3a and 3b.
  • the fuses 5c and 5d are connected in series to the C-phase electrode 7b and connected in parallel to each other.
  • the fuses 5c and 5d are provided to protect the electrolytic capacitors 4d to 4f.
  • the circuit constituted by the semiconductor modules 3c, 3d and the fuses 5e, 5f is the same as the circuit constituted by the semiconductor modules 3a, 3b and the fuses 5c, 5d, and both circuits are connected in parallel to each other.
  • Semiconductor modules 3c, 3d and fuses 5e, 5f and semiconductor modules 3a, 3b and fuses 5c, 5d share electrolytic capacitors 4a-4f and fuses 5a, 5b.
  • the circuit constituted by the semiconductor modules 3a to 3d, the electrolytic capacitors 4a to 4f and the fuses 5a to 5f is the same as the circuit constituted by the semiconductor modules 3a to 3d, the electrolytic capacitors 4a to 4f and the fuses 5a to 5f.
  • the circuits are connected in parallel with each other.
  • the semiconductor modules 3a to 3h convert the direct current from the P-phase electrode 7a, the C-phase electrode 7b, and the N-phase electrode 7c into a three-phase alternating current and output it.
  • the multilayer substrate 2 includes a first conductor plate (P-phase conductor plate) 21 on which the first electrode (P-phase electrode 7a) is formed, and a second conductor plate (C-phase) on which the second electrode (C-phase electrode 7b) is formed.
  • the laminated substrate 2 has a plate shape, and the shape of the plate surface is formed in a substantially rectangular shape.
  • connection holes 25 are formed by drilling at predetermined positions of the conductor plates 21 to 23 and the insulating plates 24a to 24d, and connection bolts (not shown) are inserted into the plurality of connection holes. Yes.
  • the electrodes 7a to 7c are electrically connected to each other by the connecting bolt.
  • the semiconductor modules 3a to 3h have a substantially rectangular plate shape.
  • the semiconductor modules 3a to 3h have a P-phase side terminal, a C-phase side terminal, an N-phase side terminal, and an AC (alternating current) side terminal on one side in the longitudinal direction.
  • the semiconductor modules 3a to 3d and the semiconductor modules 3e to 3h are disposed on the surface of the multilayer substrate 2 on the insulating plate 24a side (hereinafter referred to as “the back surface of the multilayer substrate 2”).
  • the semiconductor modules 3a to 3d are arranged in a line in order along the longitudinal direction of the multilayer substrate 2 so that only the side portion on which the terminal is provided overlaps one side portion of the back surface of the multilayer substrate 2 in the short direction. It is placed in.
  • the side portion on which the terminals are provided is on the other side portion in the short side direction of the back surface of the multilayer substrate 2 (the side portion opposite to the side portion on which the semiconductor modules 3a to 3h are disposed). They are placed in a line in order along the longitudinal direction of the laminated substrate 2 so as to overlap.
  • a plurality of connection holes 25 are formed by dish drawing at positions corresponding to the terminals of the semiconductor modules 3a to 3h on the lateral side of the multilayer substrate 2, and the P phase side of the semiconductor modules 3a to 3h.
  • the terminal and the P-phase electrode 7a, the C-phase side terminal and the C-phase electrode 7b, and the N-phase side terminal and the N-phase electrode 7c are connected.
  • the front surface of the semiconductor module 3 the surface opposite to the surface (hereinafter referred to as “the front surface of the semiconductor module 3”) of the semiconductor modules 3a to 3h (hereinafter referred to as “the front surface of the semiconductor module 3”). 6a to 6d are provided.
  • the cooling fins 6a to 6d are installed so that the direction of the cooling air passing through the cooling fins 6a to 6d is in a direction perpendicular to the row of the semiconductor modules 3 (short direction of the multilayer substrate 2).
  • the electrolytic capacitors 4a to 4m have a cylindrical portion 41 and two terminals provided at one end thereof. Electrolytic capacitors 4a-4c and electrolytic capacitors 4g-4i have a P-phase side terminal and a C-phase side terminal, respectively. On the other hand, electrolytic capacitors 4d-4f and electrolytic capacitors 4j-4m each have a C-phase side terminal and an N-phase side terminal.
  • the electrolytic capacitors 4a to 4f and the electrolytic capacitors 4g to 4m are arranged to face each other and stand on the back surface of the multilayer substrate 2.
  • the electrolytic capacitors 4a to 4f and the electrolytic capacitors 4g to 4m are placed in two rows in the center in the short direction of the multilayer substrate 2 in order along the longitudinal direction of the multilayer substrate 2.
  • Electrolytic capacitors 4a to 4f and semiconductor modules 3a to 3d are adjacent to each other, and electrolytic capacitors 4g to 4m and semiconductor modules 3e to 3h are adjacent to each other.
  • a plurality of connection holes 25 by dish drawing are provided at positions corresponding to the terminals of the electrolytic capacitors 4a to 4c and the electrolytic capacitors 4g to 4i at the center in the short direction of the multilayer substrate 2, and the electrolytic capacitor 4a To 4c and electrolytic capacitors 4g to 4i are connected to P-phase side terminal and P-phase electrode 7a, and to C-phase side terminal and C-phase electrode 7b.
  • connection hole 25 is provided at a position corresponding to the terminals of the electrolytic capacitors 4d to 4f and the electrolytic capacitors 4j to 4m at the center portion in the short direction of the multilayer substrate 2, and the electrolytic capacitors 4d to 4f and the electrolytic capacitors are provided.
  • the N-phase side terminals 4j to 4m and the N-phase electrode 7c and the C-phase side terminal and the C-phase electrode 7b are connected.
  • the fuses 5a to 5m have a substantially rectangular parallelepiped shape and have two terminals.
  • Each of fuses 5a and 5g has two P-phase side terminals
  • each of fuses 5b and 5h has two P-phase side terminals.
  • the fuses 5c to 5f and the fuses 5i to 5m each have two C-phase side terminals.
  • the fuses 5a to 5f and the fuses 5g to 5m are arranged on a surface opposite to the back surface of the multilayer substrate 2 (hereinafter, “front surface of the multilayer substrate 2”) so as to face each other.
  • the fuses 5a, 5c to 5f, 5b are arranged in a row in front of the multilayer substrate 2 so as to be disposed between the semiconductor modules 3a to 3d and the electrolytic capacitors 4a to 4f along the longitudinal direction of the multilayer substrate 2. Are placed side by side.
  • the fuses 5g, 5i to 5m, 5h are arranged in front of the multilayer substrate 2 in order so as to be arranged between the semiconductor modules 3e to 3h and the electrolytic capacitors 4g to 4m along the longitudinal direction of the multilayer substrate 2. They are placed side by side in a row.
  • connection holes 25 are provided at positions corresponding to the terminals of the fuses 5a to 5m of the multilayer substrate 2 and are brazed.
  • the P-phase terminals of the fuses 5a and 5g are connected to the P-phase side electrode 7a, and the N-phase terminals of the fuses 5b and 5h are connected to the N-phase side electrode 7c.
  • the C-phase terminals of the fuses 5c to 5f and the fuses 5i to 5m are connected to the C-phase side electrode 7b.
  • the semiconductor stack 1 is used, for example, in a power conversion device (not shown) for a three-phase rotating electrical machine.
  • the semiconductor stack 1 is installed in the casing of the power conversion device.
  • the semiconductor stack 1 is installed such that the front surface of the multilayer substrate 2 faces the front side of the casing of the power conversion device.
  • the wiring distance between the semiconductor modules 3a to 3d and the electrolytic capacitors 4a to 4f is made substantially uniform. Can do.
  • the wiring distance between the semiconductor modules 3e to 3h and the electrolytic capacitors 4g to 4m can be made substantially uniform. As a result, the current balance between the semiconductor modules 3a to 3h is good.
  • the conductors 7a to 7c connecting the semiconductor module 3 and the electrolytic capacitor 4 are laminated, the distance between the conductors 7a to 7c is minimized. As a result, the wiring inductance of each of the conductors 7a to 7c can be minimized, and the surge voltage of the semiconductor module 3 can be suppressed.
  • the semiconductor module 3, the electrolytic capacitor 4 and the fuse 5 are mounted on the surface of the planar laminated conductor 2, the semiconductor module 3, the electrolytic capacitor 4 and the fuse 5 having a high damage frequency are mounted. Maintenance replacement becomes easy.
  • the plate-like semiconductor module 3 is placed so that only the side portion on which the terminal is provided overlaps the laminated substrate 2. Therefore, the heat dissipation efficiency of the semiconductor module 3 is improved. Further, the direction of the cooling air passing through the cooling fins 6 is the short direction of the multilayer substrate 2. Therefore, the electrolytic capacitor 3 can be cooled simultaneously with the cooling of the semiconductor module 3.
  • the number of semiconductor modules 3, electrolytic capacitors 4, and fuses 5 is not limited to the above embodiment.
  • the order of stacking the first conductor plate 21, the second conductor plate 22, and the third conductor plate 23 is not limited to the above embodiment.
  • the electrical connection between the electrodes 7a to 7c and the electrical connection between the electrodes 7a to 7c and the semiconductor module 3 and the like are not limited to the connection bolts, but are copper wires, solder and brazing. Etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
PCT/JP2009/000779 2009-02-24 2009-02-24 半導体スタック、および、それを用いた電力変換装置 WO2010097830A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
PCT/JP2009/000779 WO2010097830A1 (ja) 2009-02-24 2009-02-24 半導体スタック、および、それを用いた電力変換装置
MX2011008610A MX2011008610A (es) 2009-02-24 2009-02-24 Estante de semiconductores y convertidor de energia que utiliza el mismo.
KR1020117018084A KR101189017B1 (ko) 2009-02-24 2009-02-24 반도체 스택 및 그것을 이용한 전력 변환 장치
CN200980157677.3A CN102326326B (zh) 2009-02-24 2009-02-24 半导体堆叠体及利用半导体堆叠体的功率转换装置
JP2011501344A JP5438752B2 (ja) 2009-02-24 2009-02-24 半導体スタック、および、それを用いた電力変換装置
CA2751034A CA2751034C (en) 2009-02-24 2009-02-24 Semiconductor stack and power converter using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2009/000779 WO2010097830A1 (ja) 2009-02-24 2009-02-24 半導体スタック、および、それを用いた電力変換装置

Publications (1)

Publication Number Publication Date
WO2010097830A1 true WO2010097830A1 (ja) 2010-09-02

Family

ID=42665061

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/000779 WO2010097830A1 (ja) 2009-02-24 2009-02-24 半導体スタック、および、それを用いた電力変換装置

Country Status (6)

Country Link
JP (1) JP5438752B2 (zh)
KR (1) KR101189017B1 (zh)
CN (1) CN102326326B (zh)
CA (1) CA2751034C (zh)
MX (1) MX2011008610A (zh)
WO (1) WO2010097830A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5894321B1 (ja) * 2015-07-09 2016-03-30 株式会社日立製作所 電力変換ユニットおよび電力変換装置
WO2016047164A1 (ja) * 2014-09-25 2016-03-31 株式会社日立製作所 電力変換ユニットおよび電力変換装置
JP2017060311A (ja) * 2015-09-16 2017-03-23 株式会社デンソー 電力変換装置
JP2017184387A (ja) * 2016-03-29 2017-10-05 東芝三菱電機産業システム株式会社 セルインバータユニット
US10141861B2 (en) 2014-03-27 2018-11-27 Hitachi, Ltd. Power conversion unit, power converter and method of manufacturing power converter
JP2019004582A (ja) * 2017-06-14 2019-01-10 三菱電機株式会社 開閉モジュール用のコンデンサ基板ユニット、開閉モジュール、およびモータ駆動装置
JP7500508B2 (ja) 2021-07-27 2024-06-17 株式会社Tmeic 電力変換装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2014057622A1 (ja) * 2012-10-09 2016-08-25 富士電機株式会社 電力変換装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07245951A (ja) * 1994-03-07 1995-09-19 Toshiba Corp 半導体スタック
JPH1127930A (ja) * 1997-07-07 1999-01-29 Toshiba Corp 電力変換装置及び電力変換システム
JP2001168278A (ja) * 1999-12-09 2001-06-22 Toshiba Corp パワー半導体モジュール及び電力変換装置
JP2006087212A (ja) * 2004-09-16 2006-03-30 Toshiba Mitsubishi-Electric Industrial System Corp 電力変換装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07245951A (ja) * 1994-03-07 1995-09-19 Toshiba Corp 半導体スタック
JPH1127930A (ja) * 1997-07-07 1999-01-29 Toshiba Corp 電力変換装置及び電力変換システム
JP2001168278A (ja) * 1999-12-09 2001-06-22 Toshiba Corp パワー半導体モジュール及び電力変換装置
JP2006087212A (ja) * 2004-09-16 2006-03-30 Toshiba Mitsubishi-Electric Industrial System Corp 電力変換装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10141861B2 (en) 2014-03-27 2018-11-27 Hitachi, Ltd. Power conversion unit, power converter and method of manufacturing power converter
WO2016047164A1 (ja) * 2014-09-25 2016-03-31 株式会社日立製作所 電力変換ユニットおよび電力変換装置
US9906154B2 (en) 2014-09-25 2018-02-27 Hitachi, Ltd. Power conversion unit and power conversion device
JP5894321B1 (ja) * 2015-07-09 2016-03-30 株式会社日立製作所 電力変換ユニットおよび電力変換装置
JP2017060311A (ja) * 2015-09-16 2017-03-23 株式会社デンソー 電力変換装置
JP2017184387A (ja) * 2016-03-29 2017-10-05 東芝三菱電機産業システム株式会社 セルインバータユニット
JP2019004582A (ja) * 2017-06-14 2019-01-10 三菱電機株式会社 開閉モジュール用のコンデンサ基板ユニット、開閉モジュール、およびモータ駆動装置
JP7500508B2 (ja) 2021-07-27 2024-06-17 株式会社Tmeic 電力変換装置

Also Published As

Publication number Publication date
JP5438752B2 (ja) 2014-03-12
JPWO2010097830A1 (ja) 2012-08-30
CA2751034A1 (en) 2010-09-02
CN102326326B (zh) 2014-03-26
CA2751034C (en) 2015-02-17
KR20110111459A (ko) 2011-10-11
KR101189017B1 (ko) 2012-10-08
MX2011008610A (es) 2011-09-09
CN102326326A (zh) 2012-01-18

Similar Documents

Publication Publication Date Title
JP5438752B2 (ja) 半導体スタック、および、それを用いた電力変換装置
JP4920677B2 (ja) 電力変換装置およびその組み立て方法
US11246244B2 (en) Power electronics assembly
US10153708B2 (en) Three-level power converter
JP5132175B2 (ja) 電力変換装置
KR101691707B1 (ko) 스위칭소자 유닛
JP2018107858A (ja) 電力変換装置
US11087924B2 (en) Capacitor, particularly intermediate circuit capacitor for a multiphase system
JP2014029944A (ja) スイッチング素子ユニット
JP2001168278A (ja) パワー半導体モジュール及び電力変換装置
US11778746B2 (en) Assembly structure of transformer and circuit board as well as assembly method thereof
JP5941064B2 (ja) コンデンサ装置及びコンデンサ装置を収納する電気機器
JP3015663B2 (ja) 半導体電力変換装置
CN114496955A (zh) 电力变换装置
JP5869207B2 (ja) 回路部品実装構造ならびにその実装基板
JP7500508B2 (ja) 電力変換装置
JPH06327266A (ja) 半導体電力変換装置
JP7294289B2 (ja) 電力変換装置
JP4823591B2 (ja) 電力変換装置
JP2021061692A (ja) 電力変換装置
JP2016139702A (ja) コンデンサの取付構造及び電力変換装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200980157677.3

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09840686

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2011501344

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2751034

Country of ref document: CA

ENP Entry into the national phase

Ref document number: 20117018084

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: MX/A/2011/008610

Country of ref document: MX

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09840686

Country of ref document: EP

Kind code of ref document: A1