WO2010067997A2 - Transistor en couches minces, et procédé de fabrication correspondant - Google Patents

Transistor en couches minces, et procédé de fabrication correspondant Download PDF

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WO2010067997A2
WO2010067997A2 PCT/KR2009/007269 KR2009007269W WO2010067997A2 WO 2010067997 A2 WO2010067997 A2 WO 2010067997A2 KR 2009007269 W KR2009007269 W KR 2009007269W WO 2010067997 A2 WO2010067997 A2 WO 2010067997A2
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region
semiconductor layer
layer
source
gate electrode
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PCT/KR2009/007269
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Korean (ko)
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WO2010067997A3 (fr
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노재상
홍원의
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주식회사 엔씰텍
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Publication of WO2010067997A3 publication Critical patent/WO2010067997A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Definitions

  • the present invention relates to a thin film transistor and a method for manufacturing the same, wherein the semiconductor layer of the thin film transistor is formed from a polycrystalline silicon layer crystallized by high heat generated by Joule heating by applying an electric field to a gate electrode material.
  • the semiconductor layer of the thin film transistor is formed from a polycrystalline silicon layer crystallized by high heat generated by Joule heating by applying an electric field to a gate electrode material.
  • a conductive type doping process is performed in the source / drain regions of the semiconductor layer, thereby eliminating the need for a separate mask for doping.
  • Thin-film transistors can reduce costs and simplify the process And it relates to a method of manufacturing the same.
  • amorphous silicon In general, amorphous silicon (a-Si) has disadvantages of low mobility and opening ratio of electrons, which are charge carriers, and incompatibility with CMOS processes.
  • a-Si amorphous silicon
  • the poly-silicon thin film device it is possible to configure a driving circuit on the substrate like the pixel TFT-array, which is necessary for writing an image signal to the pixel, which was not possible in the amorphous silicon TFT (a-Si TFT). . Therefore, in the polycrystalline silicon thin film element, the connection between the plurality of terminals and the driver IC becomes unnecessary, so that the productivity and reliability can be increased and the thickness of the panel can be reduced.
  • the microfabrication technology of silicon LSI can be used as it is, a microstructure can be formed in wiring etc. Therefore, since there is no pitch constraint on the TAB mounting of the driver IC seen in the amorphous silicon TFT, pixel reduction is easy and a large number of pixels can be realized with a small field of view.
  • the thin film transistor using polycrystalline silicon in the active layer has a high switching capability and the channel position of the active layer is determined by self-matching, compared with the thin film transistor using amorphous silicon, so that device miniaturization and CMOS are possible. For this reason, polycrystalline silicon thin film transistors are used as pixel switch elements in active matrix type flat panel displays (e.g., liquid crystal displays, organic ELs), and the like. It is emerging as a major device.
  • the inventors of the present invention as a method of crystallizing an amorphous silicon layer into a polycrystalline silicon layer in Korean Patent Application No. 2004-74493, forming an insulating layer on the amorphous silicon layer, and then forming a conductive layer on the insulating layer By applying an electric field to the conductive layer to induce Joule heating to generate high heat, such a high temperature at a lower temperature than conventionally, preferably at room temperature, very short time without damaging the substrate A method for better crystallization and dopant activation, thermal oxide process, and crystal lattice defect healing was proposed.
  • a portion of the insulating layer is removed by removing a portion of the insulating layer in a method for preventing arc generation due to dielectric breakdown of the insulating layer due to a potential difference between the amorphous silicon layer and the conductive layer. And a method of directly contacting the conductive layer.
  • a gate electrode material may be used as the conductive layer and a gate insulating film may be used as the insulating layer.
  • a part of the gate insulating film may be removed to prevent arc generation. It is desirable to bring the electrode material directly into contact with the amorphous silicon layer.
  • a separate mask is required.
  • the present invention is to solve the above-mentioned problems of the prior art, in forming a semiconductor layer of a thin film transistor with a polycrystalline silicon layer crystallized by the high heat generated by the joule heating by applying an electric field to the gate electrode material, By connecting the gate electrode material and the amorphous silicon layer through a contact hole included in the thin film transistor, an arc may be generated during crystallization without introducing a separate mask for removing a certain region of the gate insulating film. By using the gate insulating film and the gate electrode on which the contact hole is formed as a mask, a conductive impurity doping process is performed on the source / drain regions of the semiconductor layer, thereby eliminating the need for a separate mask for doping. Thin-film transistors can reduce costs and simplify processes Master and to their preparation.
  • the present invention is a substrate; A semiconductor layer on the substrate, the semiconductor layer including a channel region and a source / drain region including first and second regions; A gate insulating layer on the semiconductor layer; A gate electrode on the gate insulating layer; An interlayer insulating layer on the gate electrode; And electrically connected to the source and drain regions of the semiconductor layer through contact holes disposed on the interlayer insulating layer and exposing partial regions of the source and drain regions of the semiconductor layer formed in the gate insulating layer and the interlayer insulating layer. And source and drain electrodes, wherein the source and drain regions include conductive impurity ions, and projecting ranges of the conductive impurity ions included in the first and second regions in the source and drain regions. Provided are thin film transistors characterized by different Rp.
  • the present invention also provides a substrate, an amorphous silicon layer is formed on the substrate, the amorphous silicon layer is patterned, a gate insulating film is formed over the substrate, a contact hole is formed in the gate insulating film, and the gate Forming a gate electrode material on an insulating film, applying an electric field to the gate electrode material to form the patterned amorphous silicon layer into a semiconductor layer made of a polycrystalline silicon layer crystallized by Joule heating, and patterning the gate electrode material A first region having a gate electrode and a gate insulating film on which the gate electrode and the contact hole are formed as a mask, and doping the semiconductor layer with conductive impurity ions to form a first electrode having different concentrations of the doped conductive impurity ions; Forming a source and a drain region including a second region, wherein the gate An interlayer insulating film is formed on the entire surface of the substrate on which the electrode is formed, and a predetermined region of the interlayer insulating film is etched
  • the contact hole included in the thin film transistor is used to form the semiconductor layer.
  • the gate electrode material and the amorphous silicon layer it is possible to prevent arc generation that may occur during crystallization without introducing a separate mask for removing a certain region of the gate insulating film, the gate in which the contact hole is formed
  • a separate mask for doping is not required, thereby reducing manufacturing costs and simplifying the process.
  • 1 to 5 are cross-sectional views illustrating a process of manufacturing a thin film transistor according to an embodiment of the present invention.
  • FIG. 6 and 7 illustrate a concentration profile of boron ions and an oxygen concentration profile according to depths in the gate insulating film, the semiconductor layer, and the buffer layer in the thin film transistor according to Experimental Example 1.
  • FIG. 6 and 7 illustrate a concentration profile of boron ions and an oxygen concentration profile according to depths in the gate insulating film, the semiconductor layer, and the buffer layer in the thin film transistor according to Experimental Example 1.
  • FIG. 8 and 9 illustrate a concentration profile of boron ions and a concentration profile of oxygen according to depths in a gate insulating film, a semiconductor layer, and a buffer layer in the thin film transistor according to Experimental Example 2.
  • FIG. 8 and 9 illustrate a concentration profile of boron ions and a concentration profile of oxygen according to depths in a gate insulating film, a semiconductor layer, and a buffer layer in the thin film transistor according to Experimental Example 2.
  • FIG. 10 is a cross-sectional view of an organic light emitting display device including a thin film transistor according to an embodiment of the present invention.
  • 1 to 5 are cross-sectional views illustrating a process of manufacturing a thin film transistor according to an embodiment of the present invention.
  • a buffer layer 101 is formed on a substrate 100 such as glass or plastic.
  • the buffer layer 101 is formed as a single layer or a plurality of layers thereof by using an insulating film such as a silicon oxide film or a silicon nitride film by using a chemical vapor deposition method or a physical vapor deposition method.
  • the buffer layer 101 serves to prevent the diffusion of moisture or impurities generated in the substrate 100, or to control the heat transfer rate during crystallization, so that the amorphous silicon layer can be crystallized well.
  • the buffer layer 101 may be formed to a thickness of 2000 to 5000 ⁇ .
  • an amorphous silicon layer 102 is formed on the substrate 100 on which the buffer layer 101 is formed.
  • the amorphous silicon layer 102 may be formed by, for example, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation, or the like. PECVD method is used.
  • the amorphous silicon layer 102 may be formed to a thickness of 500 to 2000 ⁇ .
  • the amorphous silicon layer 102 is patterned such that the amorphous silicon layer 102 has a semiconductor layer shape of a thin film transistor.
  • a gate insulating layer 104 is formed on the patterned amorphous silicon layer 103.
  • the gate insulating layer 104 serves to insulate the gate electrode and the semiconductor layer, and the patterned amorphous silicon layer 103 is contaminated by the gate electrode material during crystallization of the patterned amorphous silicon layer 103 by Joule heating. It can play a role in preventing it.
  • the gate insulating film 104 may be formed of a silicon oxide film or a silicon nitride film, and may be formed to a thickness of 500 to 2000 ⁇ .
  • a predetermined region of the gate insulating layer 104 is etched to expose a predetermined region of the patterned amorphous silicon layer 103 to be formed as a source / drain region of the semiconductor layer, thereby forming a contact hole in the gate insulating layer 104.
  • a gate electrode material 106 is formed on the entire surface of the substrate 100 on which the gate insulating layer 104 is formed.
  • the gate electrode material 106 is preferably formed using a metal or alloy having a melting point of 1300 ° C. or more.
  • the melting point of 1300 ° C. or more includes molybdenum (Mo), titanium (Ti), chromium (Cr), or molybdenum (MoW).
  • the crystallization process by Joule heating by applying an electric field to the gate electrode material 106 to form the patterned amorphous silicon layer 103 as a polycrystalline silicon layer through Joule heating, in this case 1300
  • the crystallization may not be completed by one electric field application, in which case the electric field application process should be repeated several times.
  • the electric field application process should be repeated several times.
  • the total process time for crystallization can then be several minutes.
  • crystallization when the crystallization is performed at a high temperature of 1300 ° C. or higher, crystallization may be completed by one electric field application, and the time required for one electric field application is very short, such as several hundreds of microseconds. Therefore, when the crystallization is performed at a high temperature of 1300 ° C. or more, the total process time for crystallization can be significantly reduced. In addition, crystallization may also be enhanced by crystallizing a single electric field in a short process time at a high temperature.
  • the gate electrode material 106 may be formed by a method such as sputtering or evaporation, and may be formed to a thickness of 500 to 3000 m 3.
  • the substrate 100 may be preheated to an appropriate temperature range.
  • the appropriate temperature range refers to a temperature range in which the substrate 100 is not damaged throughout the process, and is preferably a range lower than the heat deformation temperature of the substrate 100.
  • the preheating method is not particularly limited, and for example, a method of putting in a general heat treatment furnace, a method of irradiating radiant heat such as a lamp, or the like may be used.
  • the application of the electric field to the gate electrode material 106 is accomplished by applying energy of power density that can generate by Joule heating a high heat sufficient to induce crystallization of the patterned amorphous silicon layer 103. All. As described above, when energy of a power density capable of generating high heat of 1300 ° C. or more is applied, the process time can be shortened.
  • the applied current may be direct current or alternating current.
  • One application time of the electric field may be 1 / 1,000,000 to 100 seconds, preferably 1 / 1,000,000 to 10 seconds, more preferably 1 / 1,000,000 to 1 second.
  • the application of this electric field can be repeated several times in regular or irregular units.
  • the total heat treatment time may be greater than the above electric field application time, but this is at least a very short time compared to conventional crystallization methods.
  • the patterned amorphous silicon layer 103 is applied to the gate electrode material 106 with the gate insulating film 104 interposed on the patterned amorphous silicon layer 103 by Joule heating.
  • the polycrystalline silicon layer may exhibit conductivity at a high temperature.
  • the polycrystalline silicon layer and the gate electrode material 106 and the gate insulating film 104 interposed therebetween form a capacitor, and the potential difference generated at this time exceeds the dielectric breakdown voltage of the gate insulating film 104.
  • an electric current may flow through the gate insulating layer 104 to generate an arc.
  • arc generation can be prevented by allowing the gate electrode material 106 to directly contact the polycrystalline silicon layer through the contact hole 105 formed in the gate insulating film 104 during electric field application.
  • the gate hole material 106 and the patterned amorphous silicon are prevented by generating arc by using the contact hole 105 for electrical connection between the source / drain electrode and the semiconductor layer. Since a separate mask for removing a certain region of the gate insulating layer 104 is not required to directly contact the layer 103, manufacturing cost may be reduced and the process may be simplified.
  • the gate electrode material 106 is patterned to form a gate electrode 107 positioned corresponding to a region to be defined as a channel region of the semiconductor layer 108.
  • a predetermined amount of conductive impurity ions are implanted into the semiconductor layer 108 by using the gate insulating film 104 and the gate electrode 107 having the contact holes 105 formed thereon as masks.
  • Source regions, drain regions 109 and 110, and channel regions 111 are formed therein.
  • the source and drain regions 109 and 110 are formed in the semiconductor layer 108 by using the gate insulating film 104 and the gate electrode 107 having the contact hole 105 as a mask.
  • the conductive impurity ions may form a thin film transistor using p-type impurities or n-type impurities.
  • the p-type impurities may include boron (B), aluminum (Al), gallium (Ga), and indium (In).
  • the n-type impurity may be selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), and the like.
  • a predetermined region of the source and drain regions 109 and 110 of the semiconductor layer 108 may be formed in the contact hole 105 when the conductive type impurity ion is implanted. Is exposed by the gate insulating film 104 in the upper portion.
  • the impurity ions of the conductive type are implanted into the semiconductor layer 108 under such conditions, the first region exposed by the contact hole 105 also in the source and drain regions 109 and 110 of the semiconductor layer 108.
  • the projection ranges Rp of the impurity ions implanted into the semiconductor layer 108 may be different from each other in the second and second regions 114 and 115 except for the first and second regions 112 and 113.
  • the projection range Rp of the impurity ions is a vertical direction from the top surface of the gate insulating film 104 to the point where the maximum value of the concentration profile of the impurity ions is located in the direction of the substrate 100. Means the range.
  • the projection ranges Rp of the conductive impurity ions in the second regions 114 and 115 are different from each other, and the projection ranges of the first regions 112 and 113 may be the second region 114. It is located deeper in the direction of the substrate 100 from the top surface of the gate insulating film 104 than the projection range of 115. For example, when the projection range of the first regions 112 and 113 is located in the semiconductor layer 108, the projection range of the second regions 114 and 115 may be located in the gate insulating layer 104.
  • the projection range of the first regions 112 and 113 may be located in the buffer layer 101. .
  • the projection ranges of the first regions 112 and 113 and the second regions 114 and 115 are located in the same layer, the projection ranges of the first regions 112 and 113 are the second regions ( It may be located deeper in the direction of the substrate 100 from the top surface of the gate insulating film 104 than the projection range of the 114, 115.
  • the conductive impurity ions may be implanted at a dose of 1 * E 14 / cm 2 to 1 * E 16 / cm 2, and may be implanted at an acceleration voltage of 5 to 25 keV.
  • the first and second regions 112 and 113 and 114 and 115 which are source / drain regions, are electrically connected to the source / drain electrodes.
  • a predetermined amount or more of impurity ions are implanted to provide resistance values. It is desirable to lower.
  • the amount of the impurity ions of the conductive type implanted into the first region 112 and 113 and the second region 114 and 115, respectively, is formed to be 1 * E 14 / cm 2 or more.
  • the semiconductor layer 108 is not damaged by ion implantation.
  • the semiconductor layer 108 may be formed to be implanted with an appropriate amount of ions so as to have a desirable resistance value.
  • the first regions 112 and 113 and the first region 112 and 113 may be formed after the dopant ion doping process of the conductive type.
  • Oxygen concentrations located on the upper surface of the semiconductor layer 108 in the second regions 114 and 115 are different from each other.
  • energy due to the implantation of the conductive type impurity ion is applied to the semiconductor layer 108 in a state where the gate insulating layer 104 is not removed.
  • a portion of oxygen present in the gate insulating layer 104 at the interface between the semiconductor layer 108 and the semiconductor layer 108 is recoiled to the semiconductor layer 108.
  • the oxygen concentration present on the upper surface of the semiconductor layer 108 in the second regions 114 and 115 is the oxygen concentration present on the upper surface of the semiconductor layer 108 in the first regions 112 and 113. Formed higher.
  • an interlayer insulating layer 116 is formed over the entire surface of the substrate 100 including the gate electrode 107.
  • the interlayer insulating layer 116 may be a silicon nitride film, a silicon oxide film, or a multilayer thereof.
  • a predetermined region of the interlayer insulating layer 116 is etched so that the contact hole 105 formed in the gate insulating layer 104 extends in the interlayer insulating layer 116.
  • 117 and 118 are formed.
  • the source / drain electrodes 117 and 118 may include molybdenum (Mo), chromium (Cr), tungsten (W), aluminum-neodymium (Al-Nd), titanium (Ti), molybdenum tungsten (MoW), and aluminum ( Al) may be formed of any one selected from. This completes the thin film transistor according to the embodiment of the present invention.
  • a silicon oxide film was deposited to a thickness of 4000 kPa on the organic substrate to form a buffer layer. After depositing an amorphous silicon layer on the buffer layer to a thickness of 500 kHz, the amorphous silicon layer was patterned to have a shape of a semiconductor layer. Subsequently, a silicon oxide film was deposited to a thickness of 1000 ⁇ on the patterned amorphous silicon layer to form a gate insulating film. Subsequently, a contact hole was formed in the gate insulating layer to expose a predetermined region of the patterned amorphous silicon layer to be formed as a source / drain region of the semiconductor layer.
  • Molybdenum is formed to a thickness of 1000 ⁇ with a gate electrode material on the entire surface of the substrate on which the contact hole is formed, and the patterned amorphous silicon layer is crystallized into a polycrystalline silicon layer by applying an electric field to the molybdenum to crystallize by Joule heating. Formed into layers. During the crystallization, the molybdenum and the polycrystalline silicon layer were directly contacted through the contact hole, thereby preventing arc generation.
  • the molybdenum which is a gate electrode material, was then patterned to form a gate electrode. Subsequently, the semiconductor layer was doped with boron ions, which are p-type impurity ions, at a dose of 1 * E 15 / cm 2 and an acceleration voltage of 7 keV, using the gate insulating film having the gate electrode and the contact hole as a mask.
  • FIGS. 8 and 9 illustrate a concentration profile of boron ions and an oxygen concentration profile according to depths in a gate insulating film, a semiconductor layer, and a buffer layer in the thin film transistor according to Experimental Example 1.
  • FIGS. 8 and 9 According to Experimental Example 2 above. 6 and 8 are measured in the first area exposed by the contact hole, and FIGS. 7 and 9 are measured in the second area not exposed by the contact hole. (1) is a gate insulating film region, (2) is a semiconductor layer region, and (3) is a buffer layer region.
  • the projection range of boron ions in the first region is located in the semiconductor layer region 2
  • the projection range of boron ions in the second region may include a gate insulating film ( It can be confirmed that it is located in 1).
  • the concentration of oxygen cannot be confirmed on the surface of the semiconductor layer 2
  • the semiconductor is formed in the second region. It can be seen that the oxygen concentration is higher at the interface between the layer 2 and the gate insulating film 1 as compared to the first region.
  • FIG. 10 is a cross-sectional view of an organic light emitting display device including a thin film transistor according to an embodiment of the present invention.
  • an insulating film 400 is formed on the entire surface of the substrate 100 including the thin film transistor according to the exemplary embodiment of FIG. 5.
  • the insulating film 400 may be any one selected from an inorganic film, a silicon oxide film, a silicon nitride film, or a spin on glass film, or an organic film, polyimide, benzocyclobutene series resin, or acrylate. It may be formed of any one selected from.
  • the inorganic film and the organic film may be formed in a laminated structure.
  • the insulating layer 400 is etched to form via holes exposing the source or drain electrodes 117 and 118.
  • a first electrode 401 connected to any one of the source or drain electrodes 117 and 118 is formed through the via hole.
  • the first electrode 401 may be formed as an anode or a cathode.
  • the anode may be formed of a transparent conductive film made of any one of ITO, IZO, or ITZO, and in the case of a cathode, the cathode may be Mg, Ca, Al, Ag, Ba, or these. It can be formed using an alloy of.
  • a pixel definition layer 402 having an opening exposing a part of the surface of the first electrode 401 is formed on the first electrode 401, and a light emitting layer is formed on the exposed first electrode 401.
  • An organic film layer 403 is formed.
  • the organic layer 403 may further include one or a plurality of layers selected from the group consisting of a hole injection layer, a hole transport layer, a hole suppression layer, an electron suppression layer, an electron injection layer, and an electron transport layer.
  • a second electrode 404 is formed on the organic layer 403.
  • the second electrode 404 may be formed of an anode or a cathode.
  • the second electrode 404 may be formed of a transparent conductive film made of any one of ITO, IZO, or ITZO.
  • ITO indium gallium
  • IZO indium gallium
  • ITZO indium gallium
  • Mg, Ca, Al, Ag may be used.
  • Ba or alloys thereof This completes the organic light emitting display device according to the embodiment of the present invention.
  • the gate electrode material through the contact hole included in the thin film transistor.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Recrystallisation Techniques (AREA)

Abstract

La présente invention concerne un transistor en couches minces et un procédé pour l'élaborer. En l'occurrence, on applique à une substance d'électrode grille un champ électrique de façon qu'une couche de silicium polycristallin cristallisé à haute température par la chaleur de l'effet Joule serve à former la couche de semi-conducteur d'un transistor en couches minces. En outre, ladite substance d'électrode grille est connectée à une couche de silicium amorphe par l'intermédiaire d'un trou de contact contenu dans ledit transistor en couches minces de façon à empêcher une éventuelle formation d'arc suivie de cristallisation sans qu'il soit nécessaire d'introduire de masque particulier pour l'enlèvement d'une certaine région d'une couche diélectrique de grille. Enfin, la couche diélectrique de grille sur laquelle est formé ledit trou de contact et une électrode grille sont utilisées comme masques pour exécuter le traitement de dopage destiné aux ions des impuretés conductrices dans la région source/collecteur de la couche de semi-conducteur de façon qu'il n'y ait pas besoin de masque spécifique pour le dopage, ce qui permet de réduire les coûts de fabrication et de simplifier le procédé. L'invention concerne également un transistor en couches minces comprenant un substrat, une couche de semi-conducteur située sur ledit substrat et comportant une région canal et une région source/collecteur incluant une première région et une seconde région, une couche diélectrique de grille située sur ladite couche de semi-conducteur, une électrode grille située sur ladite couche diélectrique de grille, une couche diélectrique intercalaire située sur ladite électrode grille, et des électrodes source et collecteur qui sont situées sur ladite couche diélectrique intercalaire et sont connectées chacune aux régions source et collecteur de ladite couche de semi-conducteur par l'intermédiaire d'un trou de contact qui laisse apparaître une partie des régions source et collecteur de ladite couche de semi-conducteur formée dans ladite couche diélectrique de grille et la couche diélectrique intercalaire. Par ailleurs, lesdites régions source et collecteur contiennent des ions d'impuretés conductrices, et les distances des projections (Rp) des ions d'impuretés conductrices contenus dans ladite première région et la dite seconde région desdites régions source et collecteur sont différentes les unes des autres. Enfin, l'invention concerne aussi un procédé d'élaboration correspondant.
PCT/KR2009/007269 2008-12-08 2009-12-07 Transistor en couches minces, et procédé de fabrication correspondant WO2010067997A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2008-0124141 2008-12-08
KR1020080124141A KR101043785B1 (ko) 2008-12-08 2008-12-08 박막트랜지스터 및 그의 제조방법

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WO2010067997A2 true WO2010067997A2 (fr) 2010-06-17
WO2010067997A3 WO2010067997A3 (fr) 2010-09-10

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TW (1) TW201027756A (fr)
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669804B1 (ko) * 2004-12-06 2007-01-16 삼성에스디아이 주식회사 에어갭을 구비한 박막 트랜지스터 및 그의 제조방법
KR100685848B1 (ko) * 2005-12-16 2007-02-22 삼성에스디아이 주식회사 박막트랜지스터의 제조방법
KR100731756B1 (ko) * 2006-06-07 2007-06-22 삼성에스디아이 주식회사 박막트랜지스터의 제조방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100579188B1 (ko) * 2004-02-12 2006-05-11 삼성에스디아이 주식회사 엘디디 구조를 갖는 박막트랜지스터
KR100786498B1 (ko) * 2005-09-27 2007-12-17 삼성에스디아이 주식회사 투명박막 트랜지스터 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669804B1 (ko) * 2004-12-06 2007-01-16 삼성에스디아이 주식회사 에어갭을 구비한 박막 트랜지스터 및 그의 제조방법
KR100685848B1 (ko) * 2005-12-16 2007-02-22 삼성에스디아이 주식회사 박막트랜지스터의 제조방법
KR100731756B1 (ko) * 2006-06-07 2007-06-22 삼성에스디아이 주식회사 박막트랜지스터의 제조방법

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TW201027756A (en) 2010-07-16
WO2010067997A3 (fr) 2010-09-10
KR101043785B1 (ko) 2011-06-22
KR20100065680A (ko) 2010-06-17

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