TW201027756A - Thin film transistor and fabricating method of the same - Google Patents

Abstract

Provided are a thin film transistor (TFT) and a method of fabricating the same, which include applying an electrical field to a gate electrode material to generate high heat through Joule heating so that an a-Si layer can be crystallized into a poly-Si layer and a semiconductor layer of the TFT can be formed using the poly-Si layer. The gate electrode material may be connected to the a-Si layer using a contact hole included in the TFT so that occurrence of arcs may be prevented during a crystallization process without adopting an additional mask for removing a predetermined region of a gate insulating layer, and a conductive ion doping process may be performed on source and drain regions of the semiconductor layer using the gate insulating layer having a contact hole and the gate electrode as a mask. Thus, fabrication cost may be reduced, and the entire process may be simplified. The TFT includes a substrate, a semiconductor layer disposed on the substrate and including a channel region and source and drain regions, each of the source and drain regions having a first region and a second region, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer, the source and drain electrodes electrically connected to the source and drain regions of the semiconductor substrate through contact holes formed in the gate insulating layer and the interlayer insulating layer to expose predetermined regions of the source and drain regions of the semiconductor layer. In this case, the source and drain regions contain conductive impurity ions, and a projection range of conductive impurity ions contained in the first region is different from a projection range of conductive impurity ions contained in the second region.

Description

201027756 VI. Description of the Invention: [Technology of the Invention] [0001] The present invention relates to a thin film transistor (TFT) and a method of fabricating the same, and, more particularly, to a TFT and a method of fabricating the same, The method includes applying an electric field to a gate electrode material to generate high heat through a Joule heating effect, thereby allowing an amorphous silicon layer (a-Si) to be crystallized into a polycrystalline germanium. (poiy-si 'polycrystalline silicon) layer, after which the polycrystalline germanium layer can be utilized to form a semiconductor beta layer of the TFT. In the TFT and the manufacturer thereof, the material of the gate electrode can utilize a hole included in the TFT and the surface of the amorphous layer can be used. Therefore, a predetermined region for use can be used. - The amount of:: avoiding the occurrence of an arc during the case of the outer mask, and by using the gate insulating layer having a contact hole and the gate electrode as a mask, a conducting ion doping program can be Execution 耷 let the semiconductor layer above the il_iackei domain. Therefore, the manufacturing cost can be reduced or simplified.

参C^)frirP Ψ · , , - « ill [previous [0002] In general, a-Si, asymmetrical si 1 icon in the electron mobility as an electro-optic carrier and aperture ratio (aperture ratio ) is low and is not compatible with a complementary metal oxide semiconductor (CMOS 'complementary metal oxide semiconductor). In contrast, unlike an amorphous germanium TFT, a poly-Si thin film device can be used to write an image signal (for example, a pixel ^·!' array) on a substrate. The required one drive 098141764 actuator integrated circuit (1C) is formed. Accordingly, since the polycrystalline silicon film package form number A0101 page 5/31 page 0993047690-0 201027756 does not need to connect a plurality of terminals to the driver ic, the yield and reliability can be improved, and the same Time, the thickness of a panel can also be reduced. Furthermore, since the execution of a polysilicon TFT program can utilize a large scale integrated circuit (LSI) program in the original manner, a fine interconnection structure can be formed. Therefore, since the driver 1C (unlike in the amorphous TFT) can be mounted by tape automated bonding (TAB) regardless of the pitch limitation, it will contribute to The pixels are downscaled, and a plurality of pixels can also be implemented with a narrow viewing angle. Compared with a TFT having an amorphous germanium activation layer, a TFT having a poly germanium has a good switching characteristic, and can also determine a channel position of the active layer by self-pairing 1 fa; "But this allows r to be degraded and can be applied to a CMOS program. For the above reasons, the polysilicon TFT has been used for active-matrix (active-mat-^ _ 豢:: rix) flat panel displays (FPDs,; Ho Chi iftCJMCliisplays) (for example, liquid crystal display organic light The pixel cut of the diode (0LED) display device has also been highlighted as expanding and enabling the use of driver-embedded glass-on-glass (COG 'chip-〇n-glass) products. The necessary equipment. According to Korean Patent Application No. 2004-74493, the inventor of the present invention has proposed a method of crystallizing an amorphous layer into a polycrystalline layer, comprising forming an insulating layer on the amorphous layer. A conductive layer is formed on the insulating layer, and an electric field is applied to the conductive layer to generate high heat through Joule heating. Thus 098141764

Form nickname A010I Page 6 of 31 0993047690-0 201027756 • It is possible to prevent the substrate with amorphous enamel layer from being damaged by high heat and crystallization Φ, and, compared with the conventional conditions, the dopant activity The thermal oxidation, as well as the curing of the lattice defects, can be performed more efficiently at low temperatures (preferably at room temperature) and in a short period of time. According to Korean Patent Application No. 2005-62186, in order to avoid an arc occurring due to damage of the insulating layer when utilizing the potential difference between the amorphous germanium layer and the conductive layer, the insulating layer is partially removed, thereby making The amorphous germanium layer can be in direct contact with the conductive layer. When a crystallization process is used to fabricate a TFT, a gate insulating layer can also be used as the insulating layer while a gate electrode material is used as the conductive layer. In this case, in order to avoid the occurrence of an arc, the gate insulating layer may be partially removed, thereby allowing the gate electrode material to directly contact the amorphous germanium layer, however, when it is to be from a contact hole When the gate insulation is partially removed, an additional mask is required. The invention relates to a thin film transistor (TFT) and a method of fabricating the same, which method comprises applying an electric field to a gate electrode material to transmit a Joule heating effect ( Joule heating generates high heat, so that an amorphous germanium (a-Si) layer can be crystallized into a poly-Si layer, and the poly germanium layer can be utilized to form a semiconductor layer of the TFT. Connecting the gate electrode material to the amorphous germanium layer by a contact hole included in the TFT, an additional mask for removing a predetermined region of a gate insulating layer may be used In this case, the occurrence of an arc is avoided during a crystallization procedure, and by using the gate insulating layer having a contact hole of 098141764 and the gate electrode as a mask form number A0101, page 7 / total 31 pages 0993047690- 0 201027756 hood, a conducted ion doping procedure can be performed on the source of the semiconductor layer above the drain and region. Therefore, the manufacturing cost can be reduced, and the entire program can be simplified. Provided in accordance with the teachings of the present invention is a thin film transistor (TFT) comprising: a germanium substrate; a semiconductor layer disposed over the substrate and including a channel warm region and a source and drain region Wherein each of the source and the NMOS regions has a first region and a second region; a gate insulating layer disposed over the semiconductor layer; a gate electrode disposed at the gate Above the pole insulating layer; an intermediate layer of insulating layer disposed over the gate electrode; and a drain electrode and a rotating electrode 'on the upper layer of the interlayer layer' and the nightmare _ and 汲靛The electrode is electrically connected to the light-emitting region of the conductive conductor substrate through the gate insulating layer and the middle-dark/slaughtering contact hole, thereby exposing the source and the germanium of the semiconductor layer A predetermined area of the polar region. The source and drain regions contain conductive impurity ions, and the conductive "not] turtle contained in the first region - the line + J + projection range is not... r. A projection range of the ions in the second region. DN'^e ❹ Provided is a method of fabricating a thin film transistor (TFT) according to another aspect of the present invention, comprising: providing a substrate; forming an amorphous germanium (a-Si) layer on the substrate Forming the amorphous germanium layer; forming a gate insulating layer on the entire surface of the substrate; forming a contact hole on the gate insulating layer; forming a gate electrode material on the gate insulating layer; applying a An electric field is applied to the gate electrode material material to transmit the patterned amorphous crystal into a poly-Si layer by a Joule heating effect to form a semiconductor layer; the gate electrode material is patterned Form 098141764 Form No. A0101 0993047690-0 8th Bing / Bing 31 page 201027756 into a gate electrode, using the gate electrode and the Langji insulating layer with the contact hole as a mask to conduct conductive impurities Doping into the semiconductor layer to form a source and a non-polar region, wherein each of the source and drain regions includes a -first region and a second region having different dopant concentrations; The gate electrode Forming an intermediate layer of insulating layer on the entire surface of the substrate; etching a predetermined region of the interlayer insulating layer to extend the contact hole of the gate insulating layer into the interlayer insulating layer; and insulating layer in the intermediate layer The upper shape & is electrically connected to the source and drain electrodes of the source and the non-polar region of the semiconductor layer, respectively. [Embodiment] ·, ¥ [闺 Next, the present invention_description is described in more detail. However, the present invention does not limit the exemplary examples of the defamation, and the 备 can implement a variety of types. Accordingly, the exemplary embodiments of the present invention are intended to provide a complete disclosure of the present invention, as well as a thorough understanding of the present invention. A section of the ggg tfi of 帛1A to 1E illustrates a procedure for forming a crystal (TFT) according to an exemplary embodiment of the present invention. Referring to FIG. 1A, a buffer layer 101 is formed on a substrate 1A. Above the 'for example, a glass substrate, or a plastic substrate, the buffer layer 〇1 may be a single layer formed by chemical vapor deposition (CVD), or physical vapor deposition (PVD), or a plurality of layers of yttrium oxide. Layer, or tantalum nitride layer ' Therefore, in this case, the buffer layer 101 can prevent the diffusion of moisture or impurity ions generated in the substrate 100, or can control heat transfer during a crystallization process. The rate, in turn, helps to make a non-098141764 form number A0101 page 9 of 31 0993047690-0 201027756 Crystallization of the wafer (a-Si) layer. The buffer layer ι〇1 may be formed to have a thickness of about 2,000 to 5,000 Å. Thereafter, an amorphous germanium layer 102 is formed over the substrate 100 having the buffer layer ιοί. For example, the formation of the amorphous germanium layer 1 2 can be achieved by low pressure CVD, atmospheric pressure CVD, plasma assisted CVD (PECVD), sputtering, or vacuum evaporation. Preferably, the amorphous germanium layer 102 can be formed by PECVD. The amorphous germanium layer 102 may be formed to have a thickness of about 500 to 2000 Å. Referring to Fig. 1B, the amorphous germanium layer 1 〇 2 is patterned to form a semiconductor shape of a TFT. © After 'a gate insulating layer 104 is formed in the _ has been. Over the surface of the amorphous layer 103. The gate insulating layer: 1 〇 4 functions to insulate a gate electrode from a semiconductor layer. Further, the interpolar insulating layer 104 may prevent the patterned amorphous germanium layer 1 〇 3 from being contaminated by a gate electrode material during the period in which the patterned amorphous germanium layer 103 is crystallized by the Joule heating effect. The gate insulating layer 104 may be formed by a germanium layer or a layer of nitride layer, and may have a thickness; after about, a predetermined region of the front insulating layer is etched, to expose the patterned amorphous A predetermined region of the germanium layer 103, that is, a source and a drain region of a semiconductor layer are formed in the future, thereby forming a contact hole 105 in the gate insulating layer 104. Referring to Fig. 1C, a gate electrode material 106 is formed over the entire surface of the substrate 1 having the gate insulating layer 104. The gate electrode material 106 may be formed of a metal or alloy having a melting point of about 1300 ° C or higher, for example, molybdenum (Mo), titanium (Ti), chromium (Cr), or tungsten molybdenum (MoW). ). 098141764 Form No. A0101 Page 10 of 31 0993047690-0 201027756 According to an exemplary embodiment of the present invention, during the crystallization using Joule heating, an electric field is applied to the gate electrode material, and Joule is utilized. Reducing the "patterned (4) crystal rhyme (10) crystalline polycrystalline stone (P〇ly,) layer. In this case, when the patterned non-曰2〇3 is crystallized at a high temperature of - or higher: - The program will not end the application of the material only once. Therefore, the v application procedure should be repeated several times 4 and when the electric field application procedure is repeated several times, 'every-times electric field application should be between several seconds (four)

The next lower electric field is applied, and (4) the accumulation is unacceptable and the uneven sentence is generated. And (4), the total program time required for the crystallization process can be as long as several minutes.

However, when the crystallization is carried out at a high temperature of about 1 眞 or higher, the "4th-order ageing electric field is over" and the time required for the application of the τ electric field is a very short time. Seconds (MS); therefore, the total program time when the crystallization procedure is performed at a high temperature of about 13 、, or higher is significantly reduced. "In addition, when the external sequence is applied only at a high temperature, an electric field is applied. Crystal 'if^t^f^aiiinity) will also be improved. The gate electrode material 106 can be formed to have a thickness of about 500 to 3000 A by a sputtering process or an evaporation process. After that, an electric field is applied to the gate electrode material 1〇6. Therefore, the The patterned amorphous germanium layer 103 is crystallized into a polycrystalline germanium layer to form a semiconductor layer which is crystallized by the Joule heating effect (1〇8 of FIG. 1D). An electric field is applied to the gate electrode material. Prior to 6, the substrate 1 can be preheated to a suitable temperature range. Here, 098141764 Form No. A0101 Page 11 of 31 0993047690-0 201027756 This suitable temperature range refers to a temperature range in which the substrate 100 is not damaged throughout the manufacturing process. Preferably, the appropriate temperature range is lower than a temperature at which the substrate 1 is thermally deformed. The method of preheating is not particularly limited and may include, for example, a method of placing the substrate 1 into an ordinary tempering furnace or applying a light heat of a lamp to the substrate 100. method. Regarding the application of the electric field to the gate electrode material 106, the power density of the applied energy should be sufficient to generate heat to guide the # 圊 amorphous layer 103 to pass through the Joule heating effect. ^ τ , , '0 day as in the aforementioned 'when the energy is applied: the heat generated by the power density can reach a high temperature of about 1300 ° C, or higher, called dance. Can be double shortened. Since the application of the electric field is f < For example, the gate is electrically extinguished _ remaining 106. The electric power, *^%^, and > ^^^ Therefore, it is difficult to specifically regulate the application of the electric field. of. The applied current can be a direct current (DC) or an alternating current (AC). And the time required for an electric field application program is 〇00, 〇()() 〇〇〇, 〇〇〇 to 1〇 1 171,

In the range of up to 100 seconds, between the second and the second, and the advantage is * ’ between i/〗 ’000, 000 to 1 second. The electric field application procedure can be repeated several times at regular or irregular intervals. Thus, although the total tempering time will be longer than the time the electric field is applied, the total tempering time will be at least much shorter than the time required in conventional crystallization methods. In the embodiment of the present invention, the gate electrode material 106 deposited on the patterned amorphous germanium layer 103 sandwiching the gate insulating layer 104 is applied with an electric field to cause the patterned non- The germanium layer 103 can be crystallized into a polycrystalline layer by the Joule heating effect, and the polycrystalline layer is 098141764. Form No. A0101 12th/31 pages 201027756 exhibits conductivity at high temperatures. In this case, the polysilicon layer interposed in the middle, the gate electrode material 106, and the gate insulating layer 104 may constitute a capacitor. In this case, when a potential difference generated exceeds a breakdown voltage of the gate insulating layer 104, a current flows through the gate insulating layer 104, thereby causing an arc to occur. However, according to the present invention, since the gate electrode material 106 can directly contact the polysilicon layer through the contact hole 105 formed in the gate insulating layer 104 during the electric field application process, arc generation can be avoided. . In the present invention, fabricating a TFT may include forming the contact hole 105 electrically connecting the source 汲 and the drain electrode to a semiconductor layer to prevent - the book 3: arbitrarily: a: 'arc happened. As a result, since it is no longer necessary to directly contact the gate electrode material 106 with the patterned amorphous germanium layer 103 through an additional mask for removing a predetermined region of the gate insulating layer 104, Manufacturing costs can be reduced and the program can be simplified. Next, referring to FIG. 1D, the gate electrode material 106 is patterned to thereby form a blue electrode 1 at a position, and this position corresponds to a channel to be defined as the semiconductor layer. An area of the area © . a predetermined amount of conductive impurity ions is doped into the semiconductor layer 108 by using the gate insulating layer 104 having the contact hole 105 and the gate electrode 107 as a mask. Source and drain regions 109, 110 and a channel region 111 are formed in the semiconductor layer 108. In accordance with the present invention, a conductive ion doping process for forming the source and drain regions 109, 110 in the semiconductor layer 108 can utilize the gate insulating layer 104 having the contact hole 105 and the gate The electrode 107 is performed as a mask. Therefore, the conductive ion doping 098141764 Form No. Α0101 Page 13 of 31 0993047690-0 201027756 Miscellaneous programs do not need - additional masks, thus reducing manufacturing costs and simplifying the overall program. The formation of a TFT can use p-type ' or n-type impurity ions as the conductivity; f pure ion. What? The pure ion can be selected from the following groups, including: shed (8) 'Ming (A1), gallium ((4), and indium (in), in addition, the η pure ion can be selected from the following groups, Including: phosphorus (Ρ) 'arsenic (As)' and bismuth (Sb). Please refer to FIG. 1D, in accordance with an exemplary embodiment of the present invention, in the conductive ion impurity program, in the semiconductor layer The child's area of the pole and the bungee region 109'11〇 will be exposed due to the contact hole 1〇5, while the remaining area is covered by the % bar release layer 1〇4. When these shirts are covered When the pure material is incorporated into the semiconductor layer 108, the * is exposed, and is located at the source of the semiconductor layer 108 and the first region 112 and the Π3 of the drain region 1 〇9, 11 ,, which are doped The second region of the first region 112 and 113, which is formed by the impurity ions entering the semiconductor layer, is in the second region of the first region 112 and 113. In the specification of the present invention, the wood Wei The object of the 'pregnant' edge is a vertical range, and the vertical range is from the top surface of the gate insulating layer 104 to the impurity ions. The position at which the concentration change in the direction of the substrate 100 reaches a maximum value will be described in further detail below. Among the source and drain regions 109 and 110 of the semiconductor layer 108, the contact holes 105 The projected range Rp of the impurity ions in the exposed first regions 112 and 113 may be different from the second regions 114 and 115 other than the first regions 112 and 113. The first regions 112 098141764 The projection range Rp of Form No. A0101, page 14 of 31, 201027756, and 113, will be located deeper than the projection range Rp of the second regions ii4 and 115 (from the gate insulating layer 1〇4)

The direction of the top surface toward the substrate 100), for example, when the projection range Rp of the first regions 112 and 113 is in the semiconductor layer, the projection range RP of the second regions 114 and 115 It will be located in the gate insulating layer 104. Alternatively, when the projection range Rp of the second regions 114 and 115 is in the semiconductor layer 108, the projection range RP of the first regions 112 and 113 is located in the buffer layer 101. in. Or the projection range Rp of the first regions 112 and 113 may be in the same layer as the projection range Rp of the second regions 114 and 115 'only in the 拽. The axe and the U5 The position of the projection range Rp is deeper; the top surface of the @1 〇4 faces the substrate 1: the direction of the )). · Ί _ The doping dose of these conductive impurities may be approximately l*E14/ciH2 to l*E16/cm2, and the accelerated mold pressure may be approximately 5 to 25 keV. Since the source and the first regions 112 and 113 of the frost iillflllO and the regions f|y and 115 are electrically connected to the source and the drain electrode, a predetermined dose is applied. , or more doping of conductive impurities to reduce electrical resistance. In addition, in order to obtain a desired resistance, the dose of the conductive impurity ions doped into the first regions 112 and 113 and each of the second regions 114 and 115 may be l>icE14/ Cm2, or more. When the conductive impurity ions are doped by controlling the dose and the acceleration voltage within the above range, the doping is an appropriate dose of impurity ions, and therefore, the semiconductor layer 108 will not Damaged' but still provides a required resistance. 098141764 Form No. A0101, page i5, page 31, 0993047690-0, 201027756 During the manufacture of a TFT according to an exemplary embodiment of the present invention, when the gate insulating layer ι4 is formed of a hafnium oxide layer, The oxygen concentration contained in a top surface of the first region 112 of the semiconductor layer 118 after the conductive ion doping procedure becomes different from that contained in a top surface of the second region 113. The concentration of cesium. Applying energy caused by the conductive ion exchange program to the second regions 114 and 115 of the semiconductor layer 108 from which the gate insulating layer 1〇4 has not been removed is included in the gate insulating layer Oxygen is partially bounced back to the semiconductor layer 108 at an interface between the gate insulating layer 1〇4 and the semiconductor layer 108. Thus being encased in the second regions of the semiconducting layer 108

The gas in the top surface of 114 and 115 and the gas in the top surface of 113 are included in the first layer, an intermediate layer.

A region 112 is formed over the entire surface of the substrate 100 having the gate electrode 107. The interlayer insulating layer 116 may be a layer of enamel, a layer of ruthenium oxide, or a plurality of layers described above. Thereafter, the interlayer of the intermediate layer is insulated by seven pings so as to be formed in the gate insulating layer, and the contact hole 5 extends into the interlayer insulating layer 116. 098 098141764 Then, through the contact hole 105 formed in the gate insulating layer 1 () 4 and the interlayer insulating layer 116, source and electrodeless electrodes 117 and 118 may be formed and connected to the semiconductor layer The source and the non-polar region m of (10) and the source and the electrodeless electrodes 117 and 118 may be composed of Mo, Cr, crane (W), money (A1_Nd), Ti, Mow, and A1. The selected members of the group are formed. Therefore, it can be completed according to an exemplary embodiment. Form No. A0101 Page 16 of 31 0993047690-0 201027756 An experimental example according to the present invention will be described next, although the following experimental examples are stated in a concise manner, but the present invention is not limited thereby . EXPERIMENTAL EXAMPLE 1 A niobium oxide layer was deposited on an organic substrate to a thickness of about 4000 Å to form a buffer layer. An amorphous germanium layer having a thickness of about 500 Å is further deposited on the buffer layer and patterned to form a semiconductor layer. Thereafter, a layer of germanium oxide is deposited on the patterned amorphous germanium layer to a thickness of about 1 000 A to form a gate insulating layer, and a contact hole is formed in the gate insulating layer. Exposing a predetermined region of the patterned amorphous germanium layer to the source and the drain region of the semiconductor layer, and then, on the surface of the substrate of the substrate having the contact holes, molybdenum is formed as a gate The electrode material has a thickness of about 1000 A. Thereafter, an electric field is applied to the molybdenum to crystallize the patterned amorphous germanium layer into a polycrystalline germanium layer, thereby forming a half of the crystallized through the Joule heating effect. And a conductor layer, and directly contacting the polysilicon layer during the quasi-crystallization process through the scales, thereby preventing arcing. Thereafter, the molybdenum as the gate electrode material 1 is patterned to form a gate electrode, and then the gate electrode and the gate insulating layer having the contact holes are used as a mask. The ions can be doped as p-type impurity ions and doped to the semiconductor layer at a dose of l*E15/cm2 and an acceleration voltage of about 7 keV. Experimental Example 2 The fabrication of a TFT was carried out under the same conditions as Experimental Example 1, except that B ions were doped as p-type impurity ions and doped into the semiconductor layer at an acceleration voltage of about 20 keV. 098141764 Form No. A0101 Page 3 of 31 0993047690-0 201027756 FIGS. 2A and 2B are diagrams showing changes in B ions and oxygen concentration with respect to the gate insulating layer in the TFT manufactured according to Experimental Example 1, a graph of the depth of the semiconductor layer and the buffer layer, and FIGS. 3A and 3B are diagrams showing changes in B ions and oxygen concentration with respect to the gate insulating layer in the TFT manufactured according to Experimental Example 2. a graph of the depth of the semiconductor layer and the buffer layer. FIGS. 2A and 3A show measurements obtained in the first region exposed by the contact holes, and FIGS. 2B and 3B are displayed in the second region not exposed by the contact holes. The measurements obtained. In Figs. 2A to 3B, (1) indicates a region of the gate insulating layer, (2) indicates a region of the semiconductor layer, and (3) indicates a region of the buffer layer. Referring to FIG. 2A and FIG. 2B, it can be confirmed that the B ion is in a range of . . . in the first region and is in the region (2) of the semiconductor layer, and at the same time, A projection range of B ions in the second region is in the region (1) of the gate insulating layer. Further, referring to Fig. 2A, the oxygen concentration of the bovine on the surface of the first region of the semiconductor layer 2 cannot be confirmed. In contrast, referring to the second kitchen, it can be confirmed that at an interface between the semiconductor layer 2 and the gate insulating layer 1, the oxygen concentration in the second region is higher than the first region. Higher in the middle. Therefore, it can be seen that when the energy caused by the ion doping process is applied to the second region where the gate insulating layer has not been removed, at an interface between the gate insulating layer and the semiconductor layer The oxygen contained in the gate insulating layer is bounced to the top surface of the semiconductor layer. Meanwhile, referring to FIG. 3A and FIG. 3B, it can be confirmed that the projection range of B ions in the first region falls in the buffer layer 3, and at the same time, B ions are in the second region. The projection range will fall on 098141764 Form No. A0101 Page 18 / Total 31 Page 0993047690-0 201027756 〇 This semiconductor layer 2. In addition, it can be seen that the concentration of oxygen contained in the top surface of the second region of the semiconductor layer 2 is higher than the concentration of oxygen contained in the top surface of the first region. 4 is a cross-sectional view of an OLED display device including a TFT in accordance with an exemplary embodiment of the present invention. Referring to FIG. 4, an insulating layer 400 may be formed over the entire surface of the substrate 100, and the TFT 100 includes the TFT of FIG. The insulating layer 400 may be an inorganic layer or an organic layer. The inorganic layer is selected from the group consisting of a ruthenium oxide layer, a tantalum nitride layer, and a spin-on-glass (SOG) layer. The organic layer may be formed of a group selected from the group consisting of a polyimide, a benzocyclubutene series resin, and an acrylate, or the insulating layer 400 may be It is a stack structure of an inorganic layer and an organic layer. The insulating layer 400 is etched to thereby form a via hole to expose the source electrode 117, or the electrodeless electrode 1 = 18. A first squirrel 401 can be formed through the through hole: and connected to the source and the drain electrodes 117 and 118. The first electrode 401 can be implemented as a An anode, or a cathode. When the first electrode 401 is an anode, the anode may be a transparent conductive layer, which is made of indium tin oxide (ITO), indium zinc oxide (IZ0), and A selected group of indium tin zinc oxide (ITZ0, indium tin zinc oxide) is formed. When the first electrode 401 is a cathode, the cathode may be made of magnesium (Mg), about (Ca), Ming, silver (Ag), barium (Ba), or an alloy thereof. 098141764 Form No. A0101 Page 19 of 31 0993047690-0 201027756 Thereafter, a pixel defining layer 402 having an opening is formed over the first electrode 401 to partially expose the surface of the first electrode 401. Also, an organic layer 403 including an emission layer (EML) is formed on the exposed surface of the first electrode 401. The organic layer 403 further includes a hole injection layer, a hole transport layer, a hole Mocking layer, an electron blocking layer, and a hole injection layer. The selector of the group of electron injection layers and an electron transport layer. Thereafter, a second electrode 404 is formed over the organic layer 403. The second electrode 404 can be implemented as an anode or a cathode. When the second electrode 404 is an anode, the anode may be formed using a transparent conductive layer formed by a selected group of IT0, IZ0, and ITZ0. Further, when the first electrode 401 is a cathode, the cathode may be made of Mg, Ca, Al, Ag, Ba, or an alloy thereof. Therefore, an 0 LED display device according to an exemplary embodiment of the present invention can be completed. Accordingly, when an electric field is applied to a gate electrode material to generate high heat by the Joule heating effect, and an amorphous germanium layer is crystallized into a polysilicon layer to form a semiconductor layer of a TFT by using the polysilicon layer. The gate electrode material can be connected to the amorphous germanium layer by a contact hole included in the TFT, and therefore, an additional mask for removing a predetermined region of a gate insulating layer is not required. In the case of a cover, arcing can still be prevented during a crystallization process, and by using the gate insulating layer having a contact hole and the gate electrode as a mask, a conductive ion doping program can It is executed over the source and drain regions of the semiconductor layer, so the manufacturing cost can be reduced by 098141764 Form No. A0101 Page 20 / Total 31 Page 0993047690-0 201027756 • Low, and the overall program can be simplified. The present invention has been shown and described with reference to certain exemplary embodiments, and it will be understood by those of ordinary skill in the art that the spirit of the invention is defined by the scope of the appended claims. As well as the scope of the category, there are various changes in form and detail. As described above, the present invention provides a thin film transistor (TFT) and a method of fabricating the same, which comprise applying an electric field to a gate electrode material* to generate south heat through a Joule heating effect, thereby making an amorphous The tantalum layer may be crystallized into a polysilicon layer, and the polysilicon layer may be utilized to form a semiconductor layer of the TFT. By connecting the gate electrode material to the amorphous germanium layer by using a contact hole included in the TFT, an additional mask for removing a predetermined region of a gate insulating layer can be used. In the case of a cover, it is still possible to prevent the occurrence of an arc during a crystallization process, and by using the gate electrode having a hole and the gate electrode and the gate electrode A conductive ion doping program can be performed on the 'pole and drain regions of the semiconductor layer source. Therefore, the manufacturing cost can be reduced, and the overall program can be simplified. [0005] [Simple diagram] 1A to 1E are cross-sectional views of a method of fabricating a thin film transistor (TFT) according to an exemplary embodiment of the present invention, 098141764f, 2A, and 2B, which are shown in accordance with Curve of the variation of boron (B) ions and oxygen concentration with respect to the depth of a gate insulating layer, a semiconductor layer, and a buffer layer in a TFT fabricated in Experimental Example 1 Form No. A0101 Page 21 of 31 0993047690-0 201027 756; FIG. 3A and FIG. 3B are diagrams showing boron (B) ions and oxygen concentration changes with respect to a gate insulating layer, a semiconductor layer, and a TFT fabricated in Experimental Example 2. A graph of the depth of the buffer layer; and FIG. 4 is a cross-sectional view of an organic light emitting diode (OLED) display device including a TFT according to an exemplary embodiment of the present invention. 100 substrate 101 buffer layer 104 gate insulating layer 105 contact hole 107 gate electrode 108 semiconductor layer 109, 110 drain region 111 channel region 112, 113 first region 114, 115 second region 116 intermediate layer insulating layer 117 118 source and drain electrode 400 insulating layer 401 first electrode 402 pixel defining layer 403 organic layer 404 second electrode 098141764 Form No. A0101 Page 22 of 31 0993047690-0

Claims (1)

201027756 VII. Patent application scope: 1. A thin film transistor (TFT) comprising: a substrate; a semiconductor layer disposed on the substrate and including a channel region and a source and drain region, wherein the source Each of the pole and the drain regions has a first region and a second region; a gate insulating layer disposed over the semiconductor layer; a gate electrode disposed over the gate insulating layer; An intermediate insulating layer disposed on the gate electrode; and a source and a drain electrode disposed on the interlayer insulating layer and formed through the gate insulating layer and the interlayer insulating layer a contact hole electrically connected to the source and drain regions of the semiconductor substrate to expose a predetermined region of the source and drain regions of the semiconductor layer, wherein the source and drain regions comprise conductivity Impurity ions, and a projection range of the conductive impurity ions contained in the first region is different from a projection range of the #pure ion contained in the axe of the second region. 2. The TFT of claim 1, wherein the first region is an area exposed by the contact holes, and the second region is an area that is not exposed by the contact holes. 3. The TFT of claim 1, wherein the projection range of the first region is in a direction from the top surface of the gate insulating layer toward the substrate, which is in the second region. A position that projects a deeper range. 4. The TFT of claim 1, wherein the projection range of the first region is set to be different from the projection range of the second region. 0993047690-0 098141764 Form No. A0101 Page 23 / A total of 31 pages of 201027756 layers. 5. The TFT of claim 1, wherein the projection range of the first region is set in a layer that is the same as the projection range of the second region. Such as the scope of patent application! The TFT according to the item, wherein the dose of the conductive impurity ions doped into each of the first and second regions is 1*E14/cm2' or more. 7. The TFT of claim 1, wherein the gate insulating layer comprises a hafnium oxide layer. 8. The TFi of claim 7, wherein the rear hole included in the top surface of the first region of the semiconductor layer is included in a top surface of the second region Oxygen Concentration 9. The oxygen concentration in the top surface of the second region of the semiconductor layer is higher than that of the first region of the first region as described in the patent application The oxygen concentration contained. 10 · The gate electrode as described in item 1 of the patent application is made of alloy or alloy. to make. The TFT according to claim 10, wherein the metal or alloy having a melting point of about 13 Å < t or higher comprises molybdenum (Mo), chin (Ti), chromium (Cr), or tungsten molybdenum (Mow). 12. The temper according to claim 1, wherein the semiconductor layer is made of a polycrystalline dream (P〇ly-Si) layer crystallized by a Joule heating effect. 13. A method of fabricating a thin film transistor (TFT) comprising the steps of: providing a substrate; 098141764 Form No. A0101 Page 24 of 31 0993047690-0 201027756 Forming an amorphous germanium on the substrate (a- a Si-layer layer; patterning the amorphous germanium layer; forming a gate insulating layer on the entire surface of the substrate; forming a contact hole on the gate insulating layer; forming a gate electrode material on the gate insulating layer Applying an electric field to the gate electrode material, and crystallizing the patterned amorphous germanium layer into a poly-Si layer by a Joule heating effect to form a semiconductor layer; patterning the gate electrode material, Forming a gate electrode: Ο using the gate electrode and the gate insulating layer having the contact hole as a mask to dope impurity impurities into the semiconductor layer to form a source and a drain region Wherein each of the source and drain regions includes a first region having a different dopant concentration and a second region; an overall surface of the substrate having the gate electrode Forming an intermediate layer of insulating layer; etching a predetermined region of the interlayer insulating layer, the contact hole of the gate insulating layer extending into the intermediate layer; and forming a difference on the interlayer insulating layer The source and the polarity of the source and the pole electrode are electrically connected to the semiconductor layer. The method of claim 13, wherein a projection range of the conductive impurity ions doped into the first region of each of the source and drain regions is different from being doped into a projection range of the conductive impurity ions of the second region. The method of claim 13, wherein a projection range of the first region is in a direction from the top surface of the gate insulating layer toward the substrate, and is in a projection range from the second region. A deeper position. The method of claim 13, wherein the method is doped into the source and the drain region of the semiconductor layer, wherein the method is the same as the method of claim 13 of the invention. The dose of such conductive impurity ions is 1*E14/cin2 or more. 17. The method of claim 16, wherein the conductive impurity ions are doped at a dose of about BE!4/to 丨"(10)2, and, - the acceleration voltage is about 5 to 25 keV. 18. The method of claim 13 further comprising preheating the substrate prior to applying the electric field to the gate electrode material. 19. The method of claim 13, Where an electric field is applied to the The step of the material of the closed electrode includes applying a power density to generate a thermal energy β of a temperature of about 1300 ° C or higher. 098141764 Form number Α0101 Page 26 of 31 0993047690-0