KR100731756B1 - Fabricating method of thin film transistor - Google Patents

Abstract

A method for manufacturing a thin film transistor is provided to prevent a leakage current, to improve distribution characteristic of the leakage current, and to reduce driving voltage by implanting impurities of a certain range into source/drain regions of a semiconductor layer. A substrate(101) is prepared. An amorphous silicon layer is formed on the substrate. A capping layer is formed on the amorphous silicon layer. Metal catalysts are deposited on the capping layer. Heat treatment is performed on the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. The capping layer is removed. The polycrystalline silicon layer is patterned to form a semiconductor layer(110) having source/drain regions(112,116) and a channel region(114). A gate dielectric(120) and a gate electrode(130) are formed on the semiconductor layer. Impurities of 3*e14/cm^2 to 1*e15/cm^2 are implanted into the source/drain regions.

Description

Fabrication Method of Thin Film Transistor

1A-1D are cross-sectional views of the crystallization process according to the invention.

2A and 2B are cross-sectional views of a process of manufacturing a thin film transistor using a polycrystalline silicon layer manufactured according to the present invention.

3 is a cross-sectional view of a process of forming a source / drain region and a channel region in a semiconductor layer according to the present invention.

4A is a graph showing the relationship between the sheet resistance and the off current of the polycrystalline silicon layer.

Figure 4b is a graph showing the electron mobility characteristics according to the doping amount of the impurity according to the present invention.

5 is a cross-sectional view of a process of manufacturing a thin film transistor using a semiconductor layer manufactured according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101. Substrate 102. Buffer layer

103. Amorphous Silicon Layer 105. Capping Layer

106. Metal catalyst layers 106a, 106b. Metal catalyst

107. First Heat Treatment 108. Second Heat Treatment

109. Polycrystalline silicon layer 110. Semiconductor layer

112. Source region 114. Channel region

116. Drain region 120. Gate insulating film

130. Gate Electrode 132. Doping

135, 137. Contact hole 140. Interlayer insulating film

142. Source electrode 144. Drain electrode

The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to form a semiconductor layer by crystallizing an amorphous silicon layer into a polycrystalline silicon layer by the SGS crystallization method and implanting impurities into the source / drain regions of the semiconductor layer When forming the transistor, by adjusting the doping amount of the impurity to be implanted to a certain range, it is possible to improve the problem of leakage current generated when forming a semiconductor layer by the conventional SGS crystallization method and the distribution characteristics of the leakage current The present invention relates to a method of manufacturing a thin film transistor.

In general, the polycrystalline silicon layer is widely used as a semiconductor layer for a thin film transistor because it has the advantage of being applicable to high field effect mobility, high speed operation circuit, and CMOS circuit configuration. The thin film transistor using the polycrystalline silicon layer is mainly used in the active element of the active matrix liquid crystal display device (AMLCD) and the switching element and the driving element of the organic light emitting element (OLED).

The method of crystallizing the amorphous silicon layer into a polycrystalline silicon layer includes solid phase crystallization, excimer laser crystallization, metal induced crystallization, and metal induced side crystallization. Lateral Crystallization), in which the amorphous silicon layer is annealed for several hours to several tens of hours at a temperature of about 700 ° C. or less, which is a deformation temperature of glass, which is a material for forming a substrate of a display device using a thin film transistor. The excimer laser crystallization method is a method of injecting an excimer laser into the amorphous silicon layer and heating it to a locally high temperature for a very short time to crystallize. The metal-induced crystallization method amorphous metals such as nickel, palladium, gold, aluminum, etc. Contact with or inject the silicon layer into the metal The amorphous silicon layer is a method of inducing a phase change to the polycrystalline silicon layer, and the metal-induced lateral crystallization method induces crystallization of the amorphous silicon layer sequentially as the silicide generated by the reaction between the metal and silicon continues to propagate to the side. It is a crystallization method using the method.

However, the above-mentioned solid-phase crystallization method has a disadvantage that not only the process time is too long but also the substrate is easily deformed by heat treatment at a high temperature for a long time, and the excimer laser crystallization method requires not only an expensive laser device but also There is a disadvantage in that the interfacial property between the semiconductor layer and the gate insulating film is poor due to protrusion, and when crystallized by the metal induced crystallization method or the metal induced side crystallization method, a polycrystalline silicon layer in which a large amount of metal catalyst is crystallized There is a disadvantage that the leakage current of the semiconductor layer of the thin film transistor is increased.

Currently, the method of crystallizing the amorphous silicon layer using a metal catalyst has been studied a lot because it has the advantage that can be crystallized at a lower time than the solid phase crystallization (Solid Phase Crystallization) in a short time. Crystallization using metal is divided into Metal Induced Crystallization (MIC) and Metal Induced Lateral Crystallization (MILC). However, the method using the metal catalyst has a problem in that the device characteristics of the thin film transistor are degraded due to contamination by the metal catalyst remaining in the polycrystalline silicon layer after crystallization.

In order to solve the contamination problem of the metal catalyst as described above, a method of manufacturing a polycrystalline silicon layer by a crystallization method using a cover layer (published patent 2003-0060403) has been developed. In the above method, an amorphous silicon layer and a cover layer are deposited on a substrate, a metal catalyst layer is formed thereon, and then the substrate is heat-treated or heat-treated using a laser to diffuse the metal catalyst into the amorphous silicon layer through the cover layer. After forming a seed (seed), it is a method of obtaining a polycrystalline silicon layer using this. The method has an advantage of preventing metal contamination more than necessary because the metal catalyst is diffused through the cover layer, but there is still a problem of leakage current due to the large amount of metal catalyst in the polycrystalline silicon layer.

The present invention is a problem of the SGS (Super Grain Silicon) crystallization method, which is a method of obtaining a polycrystalline silicon layer by forming a seed by diffusing the metal catalyst of the prior art to the amorphous silicon layer through the cover layer, In order to solve the problem, when the amorphous silicon layer is crystallized into a polycrystalline silicon layer by the SGS crystallization method to form a semiconductor layer, and when implanting impurities into the source / drain regions of the semiconductor layer to form a thin film transistor, By controlling the doping amount of the impurities, it is possible to manufacture a thin film transistor which can improve the problem of the leakage current (leakage current) generated when the semiconductor layer is formed by the conventional SGS crystallization method and the dispersion characteristics of the leakage current. There is a purpose.

In order to achieve the above object, a thin film transistor according to the present invention,

Board;

A semiconductor layer on the substrate, the semiconductor layer having a source / drain region and a channel region formed by SGS crystallization;

A gate insulating layer, a gate electrode, and a source / drain electrode on the semiconductor layer;

The source / drain region is achieved by a thin film transistor, wherein impurities of 3 * e ¹⁴ / cm ² to 1 * e ¹⁵ / cm ² are implanted.

In addition, the method of manufacturing a thin film transistor according to the present invention in order to achieve the above object,

Preparing a substrate;

Forming an amorphous silicon layer on the substrate;

Forming a capping layer on the amorphous silicon layer;

Depositing a metal catalyst on the capping layer;

Heat treating the substrate to crystallize an amorphous silicon layer into a polycrystalline silicon layer;

Removing the capping layer;

Patterning the polycrystalline silicon layer to form a semiconductor layer having a source / drain region and a channel region; And

Forming a gate insulating film and a gate electrode on the semiconductor layer,

The source / drain region is also achieved by a method of manufacturing a thin film transistor, characterized in that the impurity is injected into 3 * e ¹⁴ / cm ² to 1 * e ¹⁵ / cm ² .

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the figures, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. BRIEF DESCRIPTION OF THE DRAWINGS The drawings depicting preferred embodiments of the invention may be exaggerated for clarity, and like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail.

(Example)

1A to 1D are cross-sectional views of the crystallization process according to the present invention.

First, as shown in FIG. 1A, an insulating film such as a silicon oxide film or a silicon nitride film is used on a substrate 101 such as glass or plastic by using chemical vapor deposition or physical vapor deposition. The buffer layer 102 is formed in a single layer or multiple layers. In this case, the buffer layer 102 may prevent diffusion of moisture or impurities generated from the substrate 101 or adjust heat transfer rate during crystallization, so that the amorphous silicon layer to be formed in the following process may be well formed. Play a role.

Subsequently, an amorphous silicon layer 103 is formed on the buffer layer 102. In this case, the amorphous silicon layer 103 may use a chemical vapor deposition method or a physical vapor deposition method. In addition, when the amorphous silicon layer 103 is formed or after the formation of the dehydrogenation process may be carried out to lower the concentration of hydrogen.

1B is a cross-sectional view of a process of forming a capping layer and a metal catalyst layer on the amorphous silicon layer.

Referring to FIG. 1B, a capping layer 105 is formed on the amorphous silicon 103. In this case, the capping layer 105 is preferably formed of a silicon nitride film which can be diffused through a metal catalyst through a heat treatment process, and may use a multilayer of a silicon nitride film and a silicon oxide film, such as chemical vapor deposition or physical vapor deposition. To form. At this time, the thickness of the capping layer 105 is formed to 1 to 2000Å.

Subsequently, a metal catalyst is deposited on the capping layer 105 to form a metal catalyst layer 106. At this time, the metal catalyst uses any one or more selected from the group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt, Preferably nickel (Ni) is used.

In this case, the metal induced crystallization method or the metal side induced crystallization method generally requires careful control of the thickness or density of the metal catalyst, which increases the leakage current of the thin film transistor after crystallization by remaining on the surface of the polycrystalline silicon layer. This is because it causes a problem such as. However, in the present invention, the metal catalyst layer may be formed thick without precisely controlling the thickness or density. This filters the metal catalyst diffused by the capping layer 105 so that only a small amount of the metal catalyst contributes to the crystallization, and most of the metal catalyst diffuses hardly through the capping layer 105 and thus does not contribute to the crystallization. Because.

FIG. 1C is a cross-sectional view of a process of firstly heat treating the substrate to diffuse a metal catalyst through the capping layer to move to the interface of an amorphous silicon layer.

Referring to FIG. 1C, the substrate 101 on which the buffer layer 102, the amorphous silicon layer 103, the capping layer 105, and the metal catalyst layer 106 are formed may be subjected to a first heat treatment 107 of the metal catalyst layer 106. Some of the metal catalyst is moved to the surface of the amorphous silicon layer 103. That is, only the trace amount of the metal catalysts 106b among the metal catalysts 106a and 106b diffused through the capping layer 105 by the first heat treatment 107 diffuses to the surface of the amorphous silicon layer 103. Most of the metal catalysts 106a do not reach the amorphous silicon layer 103 or pass through the capping layer 105. Accordingly, the amount of the metal catalyst reaching the surface of the amorphous silicon layer 103 is determined by the diffusion blocking ability of the capping layer 105, and the diffusion blocking ability of the capping layer 105 is determined by the capping layer 105. ) Is closely related to the thickness. That is, as the thickness of the capping layer 105 becomes thicker, the amount of diffusion becomes smaller and the size of the crystal grains increases, and as the thickness becomes thinner, the amount of diffusion increases and the size of the crystal grains becomes smaller.

In this case, the first heat treatment 107 process is performed for several seconds to several hours in the temperature range of 200 ℃ to 800 ℃ to diffuse the metal catalyst (106a, 106b), the first heat treatment 107 process One or more of a furnace process, a rapid thermal annealing (RTA) process, a UV process, or a laser process may be used.

1D is a cross-sectional view of a process of crystallizing an amorphous silicon layer into a polycrystalline silicon layer by a metal catalyst diffused by second heat treatment of the substrate.

Referring to FIG. 1D, the amorphous silicon layer is formed by the metal catalysts 106b that pass through the capping layer 105 by the second heat treatment process 108 and diffuse onto the surface of the amorphous silicon layer 103 (FIG. 1C). This polycrystalline silicon layer 109 is crystallized. That is, the metal catalyst 106b of the metal catalyst layer 106 combines with the silicon of the amorphous silicon layer to form metal silicide, and the metal silicide acts as a seed which is the nucleus of crystallization to induce crystallization of the amorphous silicon layer. Done.

In this case, in the crystallization method according to the present invention, a single or double capping layer is formed on an amorphous silicon layer, a metal catalyst layer is formed on the capping layer, and a first heat treatment process and a second heat treatment process are performed to form a metal catalyst. Diffusion, a method in which an amorphous silicon layer is crystallized into a polycrystalline silicon layer by the diffused metal catalyst, which is called SGS (Super Grain Silicon) crystallization method.

Therefore, by controlling the amount of the metal silicide that is the nucleus of the crystallization, it is possible to adjust the grain size of the polycrystalline silicon layer 109, and furthermore, the adjustment of the grain size is determined by the metal catalyst 106b contributing to the crystallization, The grain size of the polycrystalline silicon layer 106b may be adjusted by adjusting the diffusion blocking ability of the capping layer 105. That is, the grain size of the polycrystalline silicon layer 106b may be adjusted by adjusting the thickness of the capping layer 105.

Meanwhile, in FIG. 1D, the second heat treatment 108 is performed without removing the capping layer 105 and the metal catalyst layer 106, but the capping layer 105 and the metal catalyst layer 106 are removed and the second heat treatment ( 108) The process may be performed. After the first heat treatment (107 in FIG. 1C), the metal catalyst layer 106 may be removed and the capping layer 106 may be removed after the second heat treatment 108 is performed. Do. In this case, the second heat treatment 108 may be performed at a temperature range of 400 ° C. to 1300 ° C., and may use any one or more of a furnace process, an RTA process, a UV process, or a laser process.

2A and 2B are cross-sectional views of a process of manufacturing a thin film transistor using the polycrystalline silicon layer manufactured by the present invention.

Referring to FIG. 2A, a semiconductor layer 110 is formed by patterning a polycrystalline silicon layer (109 of FIG. 1D) crystallized by an SGS crystallization method including a capping layer on a substrate 101 on which a buffer layer 102 is formed. At this time, the semiconductor layer 110 has only a small amount of the metal catalyst remaining in the semiconductor layer 110 by the capping layer has excellent leakage current characteristics compared to other crystallization methods.

Subsequently, as shown in FIG. 2B, a gate insulating film 120 is formed on the substrate 101 on which the semiconductor layer 110 is formed. The gate insulating film 120 is formed by stacking a silicon oxide film or a silicon nitride film in a single layer or a plurality of layers. To form.

Subsequently, a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd) on the gate insulating layer 120, or multiple aluminum alloys are laminated on a chromium (Cr) or molybdenum (Mo) alloy. The gate electrode metal layer (not shown) is formed as a layer, and the gate electrode metal layer is etched by a photolithography process to form the gate electrode 130 in a predetermined portion corresponding to the semiconductor layer 110.

3 is a cross-sectional view of a process of forming a source / drain region and a channel region by doping impurities into a semiconductor layer formed by the SGS crystallization method.

First, as shown in FIG. 3, the source / drain regions 112 and 116 are formed by using the gate electrode 130 as a mask as a doping 132 with impurity ions of a conductive type. P-type impurities or n-type impurities may be implanted into the impurity ions, and P, PH _x ⁺ , P ₂ H _x (where X = 1,2,3 ...) may be implanted into the n-type impurities. It is possible to inject elements of Group 5 of the periodic table. In addition, any one or more selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), and indium (In) may be used as the p-type impurity. In the embodiment of the present invention, boron (B) is implanted into the impurity ions, and B ₂ H _x ⁺ , BH _x ⁺ (where X = 1, 2, 3 ...) can be implanted and the Group 3 element on the periodic table. Injection is also possible. In the case of SGS crystallization, the resistance of the source / drain region is preferably about 2kΩ / □ to 4kΩ / □. When the resistance is 2kΩ / □ or less, the leakage current increases, and when it is 4kΩ / □ or more, the thin film transistor is used. The resistance of E increases so that the electron mobility decreases and the on current decreases.

4A is a graph showing the relationship between the sheet resistance and off current of the polycrystalline silicon layer, and FIG. 4B is a graph showing the electron mobility characteristics according to the doping amount according to the present invention.

First, referring to FIG. 4A, when the off current is lowered to 1 × E ^-12 A / μm or less, leakage current may be reduced, and for this, the resistance of the source / drain region of the semiconductor layer formed by SGS crystallization method may be used. About 2 kΩ / □ to 4 kΩ / □ is preferable, and p-type impurities are implanted at 3 * e ¹⁴ / cm ² to 1 * e ¹⁵ / cm ² in the source / drain region in order to show the resistance value.

In the present invention, using boron (B) as a p-type impurity, the doping amount of the boron (B) is injected 3 * e ¹⁴ / cm ² to 1 * e ¹⁵ / cm ² , the doping amount of the boron (B) In the case of injection of 3 * e ¹⁴ / cm ² or less, as shown in FIG. 4B, the resistance of the thin film transistor is increased so that the mobility of electrons is reduced and the on current decreases, and the boron (B) is reduced. the doping amount of) 1 * e ¹⁵ / cm ² In the case of the above injection, the electron mobility property is improved, but the leakage current is increased, thereby degrading the characteristics of the thin film transistor.

  In this case, the region in which the impurities are not doped, located between the source / drain regions 112 and 116, is defined as a channel region 114. However, the doping process may be performed by forming a photoresist before forming the gate electrode 130.

5 is a cross-sectional view of a process of manufacturing a thin film transistor using the semiconductor layer manufactured by the present invention.

Referring to FIG. 5, after forming an interlayer insulating layer 140 protecting a lower structure on the gate electrode 130 on the gate insulating layer 120, a predetermined region of the interlayer insulating layer 140 and the gate insulating layer 120 is formed. Etching forms contact holes 135 and 137 and source / drain electrodes 142 and 144 filling the contact holes 135 and 137 to form a thin film transistor.

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Many variations and modifications will be possible.

As described above, according to the present invention, by injecting a predetermined range of impurities into the source / drain region of the semiconductor layer formed by the SGS crystallization method, the leakage current generated when the semiconductor layer is formed by the SGS crystallization method and the leakage The current dissipation characteristics are improved and the driving voltage is reduced to obtain a thin film transistor with improved device characteristics.

Claims (14)

Board; A semiconductor layer on the substrate, the semiconductor layer having a source / drain region and a channel region formed by SGS crystallization; A gate insulating layer, a gate electrode, and a source / drain electrode on the semiconductor layer; The source / drain region is a thin film transistor, characterized in that the impurity of 3 * e ¹⁴ / cm ² to 1 * e ¹⁵ / cm ² is injected. The method of claim 1, The impurity is a thin film transistor, characterized in that the p-type impurities or n-type impurities. The method of claim 2, The p-type impurity is any one selected from the group consisting of boron (B), B ₂ H _x ⁺ and BH _x ⁺ (where X = 1, 2, 3 ...), the n-type impurity is P, Thin film transistor, characterized in that any one selected from the group consisting of PH _x ⁺ and P ₂ H _x (where, X = 1, ₂ , 3 ...). Preparing a substrate; Forming an amorphous silicon layer on the substrate; Forming a capping layer on the amorphous silicon layer; Depositing a metal catalyst on the capping layer; Heat treating the substrate to crystallize an amorphous silicon layer into a polycrystalline silicon layer; Removing the capping layer; Patterning the polycrystalline silicon layer to form a semiconductor layer having a source / drain region and a channel region; And Forming a gate insulating film and a gate electrode on the semiconductor layer, The method of manufacturing a thin film transistor, characterized in that the impurity is injected into the source / drain region 3 * e ¹⁴ / cm ² to 1 * e ¹⁵ / cm ² . The method of claim 4, wherein The p-type impurity is a method for manufacturing a thin film transistor, characterized in that the Group 3 element on the periodic table. The method of claim 4, wherein The p-type impurity is a thin film transistor, characterized in that any one selected from the group consisting of boron (B), B ₂ H _x ⁺ and BH _x ⁺ (where X = 1, 2, 3 ...) Way. The method of claim 4, wherein The capping layer is a method of manufacturing a thin film transistor, characterized in that formed in a single layer or multiple layers of silicon oxide film or silicon nitride film. The method of claim 4, wherein The capping layer is a method of manufacturing a thin film transistor, characterized in that formed in a thickness of 1 to 2000Å. The method of claim 4, wherein The metal catalyst is a method of manufacturing a thin film transistor, characterized in that the nickel (Ni). The method of claim 4, wherein The heat treatment is a method of manufacturing a thin film transistor, characterized in that consisting of a first heat treatment step and a second heat treatment step. The method of claim 10, The first heat treatment step is a step of diffusing a metal catalyst through the capping layer to move to the interface of the amorphous silicon layer, the method of manufacturing a thin film transistor. The method of claim 10, The second heat treatment step is a step of crystallizing the amorphous silicon layer to a polycrystalline silicon layer by the diffusion metal catalyst. The method of claim 10, The first heat treatment step is a method of manufacturing a thin film transistor, characterized in that performed in a temperature range of 200 ℃ to 800 ℃. The method of claim 10, The second heat treatment step is a method of manufacturing a thin film transistor, characterized in that performed at a temperature range of 400 ℃ to 1300 ℃.

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