KR100742381B1 - Fabricating method of thin film transistor - Google Patents

Abstract

A method for fabricating a thin film transistor is provided to remove a metal catalyst existing in a polycrystalline silicon layer by crystallizing an amorphous silicon layer to a polycrystalline silicon layer by an SGS(super grain silicon) crystallization method and by forming a capping layer on the polycrystalline silicon layer. An amorphous silicon layer is formed on a substrate(100). A first capping layer is formed on the amorphous silicon layer. A metal catalyst is deposited on the first capping layer. A heat treatment is performed on the substrate to crystallize the amorphous silicon layer to a polycrystalline silicon layer. The first capping layer is removed. A second capping layer is formed on the polycrystalline silicon layer. First n-type impurities of 1x10^11/centimeter^2 to 3x10^15/centimeter^2 are implanted into the second capping layer. A heat treatment is performed on the second capping layer to diffuse the metal catalyst remaining in the polycrystalline silicon layer to the second capping layer. The second capping layer is removed. The polycrystalline silicon layer is patterned to form a semiconductor layer(120). A gate insulation layer(125) and a gate electrode(130) are formed on the substrate. Second impurities are implanted into the semiconductor layer. The second capping layer can be made of a silicon nitride layer. The first capping layer can be made of a silicon oxide layer, a silicon nitride layer or a composition layer thereof.

Description

Fabrication Method of Thin Film Transistor

1A-1F are cross-sectional views of the crystallization process according to the present invention.

2A and 2B are cross-sectional views of a process of forming a semiconductor layer using the polycrystalline silicon layer produced by the present invention.

3 is a cross-sectional view of a process of implanting a second impurity to form a source / drain region and a channel region.

4 is a cross-sectional view of a process of manufacturing a thin film transistor using the semiconductor layer manufactured by the present invention.

          <Explanation of symbols for main parts of the drawings>

100. Substrate 101. Buffer Layer

102. Amorphous Silicon Layer 103. First Capping Layer

104. Metal catalyst layers 104a, 104b. Metal catalyst

105. First Heat Treatment 106. Polycrystalline Silicon Layer

107. Second Heat Treatment 108. Second Capping Layer

109. First impurity 110. Third heat treatment

120. Semiconductor layer 122. Source region

124. Channel region 126. Drain region

125. Gate insulating film 130. Gate electrode

132. Second Impurity 140. Interlayer Insulator

142. Source electrode 144. Drain electrode

The present invention relates to a method for manufacturing a thin film transistor, and more particularly, in the SGS crystallization method (Super Grain Silicon), which is a method of crystallizing an amorphous silicon layer into a polycrystalline silicon layer using a metal catalyst, By removing the metal catalyst acting as a nucleation of the crystallization, to minimize the amount of metal catalyst (Ni, etc.) remaining in the channel region of the semiconductor layer to improve the leakage current and improve the device characteristics in a thin film transistor manufacturing method It is about.

In general, the polycrystalline silicon layer is widely used as a semiconductor layer for thin film transistors because of its advantages in that it can be applied to high field effect mobility, high speed operation circuits, and CMOS circuits. The thin film transistor using the polycrystalline silicon layer is mainly used in the active element of the active matrix liquid crystal display device (AMLCD) and the switching element and the driving element of the organic light emitting element (OLED).

The method of crystallizing the amorphous silicon layer into a polycrystalline silicon layer may include solid phase crystallization, solid phase crystallization, excimer laser crystallization, metal induced crystallization, and metal induced side crystallization. Lateral Crystallization), in which the amorphous silicon layer is annealed for several hours to several tens of hours at a temperature of about 700 ° C. or less, which is a deformation temperature of glass, which is a material for forming a substrate of a display device using a thin film transistor. The excimer laser crystallization method is a method of injecting an excimer laser into the amorphous silicon layer and heating it to a locally high temperature for a very short time to crystallize. The metal-induced crystallization method amorphous metals such as nickel, palladium, gold and aluminum Contact with or inject the silicon layer into the metal Solution The amorphous silicon layer uses a phenomenon in which a phase change is induced to the polycrystalline silicon layer, and the metal-induced lateral crystallization method sequentially crystallizes the amorphous silicon layer as the silicide generated by the reaction between the metal and silicon continues to propagate to the side. It is a crystallization method using the induction method.

However, the above-mentioned solid-phase crystallization method has a disadvantage that not only the process time is too long but also the substrate is easily deformed by heat treatment at a high temperature for a long time, and the excimer laser crystallization method requires not only an expensive laser device but also There is a disadvantage that the interfacial property between the semiconductor layer and the gate insulating film is bad due to the protrusion (protrusion), when the crystallization by the metal-induced crystallization method or metal-induced side crystallization method, a large amount of metal catalyst in the crystallized polycrystalline silicon layer There is a disadvantage that the residual current increases the leakage current of the semiconductor layer of the thin film transistor.

Currently, the method of crystallizing an amorphous silicon layer into a polycrystalline silicon layer using a metal catalyst has been studied a lot because it has the advantage of being able to crystallize at a lower temperature at a faster time than the solid phase crystallization method (Solid Phase Crystallization). Crystallization using metal is divided into Metal Induced Crystallization (MIC) and Metal Induced Lateral Crystallization (MILC). However, the method using the metal catalyst has a problem in that the device characteristics of the thin film transistor are degraded due to contamination by the metal catalyst remaining in the polycrystalline silicon layer after crystallization.

In order to solve the problem of contamination of the metal catalyst as described above, a method of manufacturing a polycrystalline silicon layer by a crystallization method using a cover layer (Patent Publication 2003-0060403) has been developed. In the above method, an amorphous silicon layer and a cover layer are deposited on a substrate, a metal catalyst layer is formed thereon, and then the metal catalyst is diffused through the cover layer to the amorphous silicon layer by heat treatment using a laser or a heat treatment process using a laser. After forming a seed (seed), it is a method of obtaining a polycrystalline silicon layer using this.

However, the above-described method has an advantage of preventing metal contamination more than necessary because the metal catalyst is diffused through the cover layer, but there is still a problem that a large amount of the metal catalyst is present inside the polycrystalline silicon layer.

The present invention is to solve the above problems of the prior art, a second method on the polycrystalline silicon layer in the SGS (Super Grain Silicon) crystallization method, which is a method of crystallizing an amorphous silicon layer into a polycrystalline silicon layer using a metal catalyst. Forming a capping layer, doping impurities in the second capping layer and heat treatment to remove the metal catalyst remaining in the polycrystalline silicon layer, to minimize the amount of metal catalyst (Ni, etc.) remaining in the polycrystalline silicon layer leakage current The purpose of the present invention is to manufacture a thin film transistor that can improve the characteristics and device characteristics.

In order to achieve the above object, a thin film transistor according to the present invention,

Preparing a substrate;

Forming an amorphous silicon layer on the substrate;

Forming a first capping layer on the amorphous silicon layer;

Depositing a metal catalyst on the first capping layer;

Heat treating the substrate to crystallize an amorphous silicon layer into a polycrystalline silicon layer;

Removing the first capping layer;

Forming a second capping layer on the polycrystalline silicon layer;

Injecting a first impurity into the second capping layer;

Third heat treating the second capping layer to diffuse the metal catalyst remaining in the polycrystalline silicon layer to the second capping layer;

Removing the second capping layer;

Patterning the polycrystalline silicon layer to form a semiconductor layer;

Forming a gate insulating film and a gate electrode on the substrate; And

Injecting a second impurity into the semiconductor layer;

The first impurity is achieved by a method of manufacturing a thin film transistor, characterized in that the injection of n-type impurities in 1 * e ¹¹ / cm ² to 3 * e ¹⁵ / cm ² .

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the figures, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. BRIEF DESCRIPTION OF THE DRAWINGS The drawings depicting preferred embodiments of the invention may be exaggerated for clarity, and like reference numerals refer to like elements throughout.

Hereinafter, described in more detail with reference to the accompanying drawings, preferred embodiments of the present invention. In the following embodiment of the present invention, a process of forming a semiconductor layer using the SGS crystallization method is illustrated, but is not limited thereto, and the process of forming a semiconductor layer using a metal catalyst such as metal induced crystallization or metal induced side crystallization Can be applied to

1A-1F are cross-sectional views of the crystallization process according to the present invention.

First, as shown in FIG. 1A, a buffer layer 101 may be formed of amorphous silicon on a substrate 100 such as glass or plastic. In this case, the buffer layer 101 may be formed by using chemical vapor deposition (Physical Vapor Deposition) or physical vapor deposition (Physical Vapor Deposition).

Subsequently, an amorphous silicon layer 102 is formed on the buffer layer 101. In this case, the amorphous silicon layer 102 may use a chemical vapor deposition (Physical Vapor Deposition) or a physical vapor deposition (Physical Vapor Deposition). In addition, when the amorphous silicon layer 102 is formed or after the formation thereof, dehydrogenation may be performed to lower the concentration of hydrogen.

1B is a cross-sectional view of a process of forming a first capping layer and a metal catalyst layer on the amorphous silicon layer.

Referring to FIG. 1B, a first capping layer 103 is formed on the amorphous silicon layer 102. In this case, the first capping layer 103 is preferably formed of a silicon nitride film in which a metal catalyst can be diffused through a heat treatment process, and may use a multilayer of a silicon nitride film and a silicon oxide film, and may be a chemical vapor deposition method or a physical vapor deposition method. It is formed in the same manner. At this time, the thickness of the first capping layer 105 is formed to 1 ~ 2000Å.

Subsequently, a metal catalyst is deposited on the first capping layer 103 to form a metal catalyst layer 104. At this time, the metal catalyst is any one or more of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd or Pt, preferably nickel ( Ni) is used.

In this case, in general, in metal induced crystallization or metal induced side crystallization, the thickness or density of the metal catalyst should be carefully controlled. This means that after crystallization, the metal catalyst remains on the surface of the polycrystalline silicon layer to reduce the leakage current of the thin film transistor. This is because it causes problems such as increasing. However, in the present invention, the metal catalyst layer 104 may be formed thick without precisely controlling the thickness or density. This filters the metal catalyst diffused by the first capping layer 103 so that only a small amount of the metal catalyst contributes to the crystallization, and most of the metal catalyst diffuses difficult to pass through the first capping layer 103. Will not contribute.

FIG. 1C is a cross-sectional view illustrating a process of diffusing a metal catalyst through the first capping layer to move the substrate to an interface of an amorphous silicon layer.

Referring to FIG. 1C, the substrate 100 on which the buffer layer 101, the amorphous silicon layer 102, the first capping layer 103, and the metal catalyst layer 104 are formed is subjected to a first heat treatment 105 to provide a metal catalyst layer 104. A part of the metal catalyst of is moved to the surface of the amorphous silicon layer 102. That is, a trace amount of the metal catalyst 104b that diffuses and moves to the first capping layer 103 among the metal catalysts 104a and 104b that diffuses through the first capping layer 103 by the first heat treatment 105. Only these particles diffuse to the surface of the amorphous silicon layer 102, and most of the metal catalysts 104a do not reach the amorphous silicon layer 102 or pass through the first capping layer 103. Therefore, the amount of the metal catalyst reaching the surface of the amorphous silicon layer 102 is determined by the diffusion blocking ability of the first capping layer 103, and the diffusion blocking ability of the first capping layer 103 is There is a close relationship with the thickness of the first capping layer 103. That is, as the thickness of the first capping layer 103 becomes thicker, the amount of diffusion becomes smaller and the size of crystal grains becomes larger, and as the thickness becomes thinner, the amount of diffusion becomes larger and the size of crystal grains becomes smaller.

In this case, the first heat treatment 105 process is performed for several seconds to several hours in the temperature range of 200 to 800 ℃ to diffuse the metal catalyst, the first heat treatment 105 process is a furnace (furnace) process, Any one or more of a rapid thermal annealing (RTA) process, a UV process, or a laser process may be used.

1D is a cross-sectional view of a process of crystallizing an amorphous silicon layer into a polycrystalline silicon layer by a metal catalyst diffused by second heat treatment of the substrate.

Referring to FIG. 1D, the amorphous metal catalysts 104b diffused through the first capping layer 103 by the second heat treatment process 107 onto the surface of the amorphous silicon layer 102 of FIG. 1C. Silicon layer 102 is crystallized into polycrystalline silicon layer 106. That is, the metal catalyst 104b of the metal catalyst layer 104 combines with silicon of the amorphous silicon layer 102 to form a metal silicide, and the metal silicide acts as a seed which is the nucleus of crystallization, thereby crystallizing the amorphous silicon layer. Will lead to.

In this case, in the crystallization method according to the present invention, a first capping layer is formed on an amorphous silicon layer, a metal catalyst layer is formed on the first capping layer, and the first and second heat treatment processes are performed to diffuse the metal catalyst. In addition, an amorphous silicon layer is crystallized into a polycrystalline silicon layer by the diffused metal catalyst, which is called SGS (Super Grain Silicon) crystallization method.

Therefore, by controlling the amount of the metal silicide that is the nucleus of the crystallization, it is possible to control the grain size of the polycrystalline silicon layer 106, and furthermore, the control of the grain size is determined by the metal catalyst 104b contributing to the crystallization, The grain size of the polycrystalline silicon layer 106 may be adjusted by adjusting the diffusion blocking ability of the first capping layer 103. That is, the grain size of the polycrystalline silicon layer 106 may be adjusted by adjusting the thickness of the first capping layer 103.

Meanwhile, in FIG. 1D, the second heat treatment 107 process is performed without removing the first capping layer 103 and the metal catalyst layer 104, but the first capping layer 103 and the metal catalyst layer 104 are removed. The second heat treatment 107 may be performed. After the first heat treatment (105 in FIG. 1C), the metal catalyst layer 104 is removed and the second capping layer 103 is performed after performing the second heat treatment 107. ) May be removed. In this case, the second heat treatment 107 process may be performed for a time of 1 minute or more and 20 hours or less in a temperature range of 400 to 800 ° C, and may use any one or more of a furnace process, an RTA process, a UV process, or a laser process. have.

1E is a cross-sectional view illustrating a process of injecting first impurities by forming a second capping layer on the polycrystalline silicon layer.

Referring to FIG. 1E, a second capping layer 108 is formed on the polycrystalline silicon layer 106 from which the first capping layer 103 of 1d and the metal catalyst layer 104 of FIG. 1D are removed. In this case, the second capping layer 108 is formed of a silicon nitride film using chemical vapor deposition. The second capping layer 108 is formed by selecting the refractive index in the range of 1.94 or less. When the refractive index of the second capping layer 108 is 1.94 or more, the metal catalyst remaining in the polycrystalline silicon layer 106 is difficult to diffuse into the second capping layer 108 during the third heat treatment process to be performed below.

In addition, the second capping layer 108 is formed to have a thickness of 10 to 1000 GPa. When the thickness of the second capping layer 108 is formed to be 10 GPa or less, the metal catalyst remaining in the polycrystalline silicon layer 106 is formed. It is difficult to be diffused and removed to the second capping layer 108, and when formed to be 1000 Å or more, a high temperature and a long time are required to form the second capping layer 108, and the deposition time is also delayed.

Subsequently, a first impurity 109 is injected into the second capping layer 108. The first impurity 109 is a material for gettering to remove the metal catalyst remaining in the polycrystalline silicon layer 106. The first impurity 109 is an n-type impurity. Preferably, any one selected from the group consisting of phosphorus (P), PH _x ⁺ or P ₂ H _x (where X = 1,2,3 ...) can be injected, and a group 5 element on the periodic table is also injected. It is possible. Preferably, phosphorus (P) is used as the first impurity 109 and the doping amount is preferably injected in the range of 1 * e ¹¹ / cm ² to 3 * e ¹⁵ / cm ² . When the first impurity 109 is doped to 1 * e ¹¹ / cm ² or less, the metal catalyst remaining in the polycrystalline silicon layer 106 may be difficult to be sufficiently removed, and may be doped to 3 * e ¹⁵ / cm ² or more. In this case, the first impurity 109 doped into the second capping layer 108 may diffuse into the polycrystalline silicon layer 106 to deteriorate device characteristics.

Subsequently, as shown in FIG. 1F, the entire substrate 100 is subjected to a third heat treatment 110 to remove the metal catalyst (Ni, etc.) remaining in the polycrystalline silicon layer 106. The third heat treatment 110 is performed at a temperature in the range of 500 ° C. to 800 ° C., and is heated for 1 minute to 120 minutes. A small amount of metal catalyst (Ni, etc.) remaining in the polycrystalline silicon layer 106 is removed by the third heat treatment 110. In particular, the semiconductor is formed by patterning the polycrystalline silicon layer 106 to be performed in the following process. A trace amount of the metal catalyst remaining in the channel region of the layer may be removed by the first impurity (109 in FIG. 1E) doped in the second capping layer 108 to form a thin film transistor having excellent electrical characteristics.

2A and 2B are cross-sectional views of a process of forming a semiconductor layer using the polycrystalline silicon layer produced by the present invention.

Referring to FIG. 2A, the semiconductor layer 120 is formed by removing the second capping layer 108 formed on the polycrystalline silicon layer 106 (FIG. 1F) and patterning the polycrystalline silicon layer 106 crystallized by SGS crystallization. ). At this time, the semiconductor layer 120 has only a small amount of a metal catalyst remaining by the first and second capping layers 103 and 108 to have better leakage current characteristics than other crystallization methods.

Subsequently, as shown in FIG. 2B, a gate insulating layer 125 is formed on the substrate 100 on which the semiconductor layer 120 is formed. The gate insulating layer 125 is formed by stacking a silicon oxide film or a silicon nitride film in a single layer or a plurality of layers. To form.

Subsequently, a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd) on the gate insulating layer 125, or multiple aluminum alloys are laminated on a chromium (Cr) or molybdenum (Mo) alloy. A gate electrode metal layer (not shown) is formed as a layer, and the gate electrode metal layer is etched by a photolithography process to form a gate electrode 130 at a predetermined portion corresponding to the semiconductor layer 120.

3 is a cross-sectional view of a process of implanting a second impurity to form a source / drain region and a channel region.

As shown in FIG. 3, the source region 122 and the drain region 126 are formed by predetermined doping of the conductive second impurity 132 using the gate electrode 130 as a mask. P-type thin film transistor is formed using p-type impurity as the second impurity 132, and the p-type impurity is a group consisting of boron (B), aluminum (Al), gallium (Ga), and indium (In). You can choose from.

  In this case, a region disposed between the source region 122 and the drain region 126 where the second impurity 132 is not doped serves as the channel region 124. However, the doping process may be performed by forming a photoresist before forming the gate electrode 130.

4 is a cross-sectional view of a process of manufacturing a thin film transistor using the semiconductor layer manufactured by the present invention.

Referring to FIG. 4, after forming an interlayer insulating layer 140 protecting a lower structure on the gate electrode 130 on the gate insulating layer 125, a predetermined region of the interlayer insulating layer 140 and the gate insulating layer 125 is formed. A semiconductor layer including a source region 122, a drain region 126, and a channel region 124 in which a metal catalyst is removed by forming source / drain electrodes 142 and 144 that form a contact hole by etching and forming a contact hole. A P-type thin film transistor including 120 is completed.

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Many variations and modifications will be possible.

As described above, according to the present invention, after the amorphous silicon layer is crystallized into a polycrystalline silicon layer by the SGS crystallization method, a capping layer is formed on the polycrystalline silicon layer to form a metal catalyst (Ni, etc.) present in the polycrystalline silicon layer. By eliminating this, the leakage current of the thin film transistor can be improved and device characteristics can be improved.

Claims (17)

Preparing a substrate; Forming an amorphous silicon layer on the substrate; Forming a first capping layer on the amorphous silicon layer; Depositing a metal catalyst on the first capping layer; Heat treating the substrate to crystallize an amorphous silicon layer into a polycrystalline silicon layer; Removing the first capping layer; Forming a second capping layer on the polycrystalline silicon layer; Injecting a first impurity into the second capping layer; Third heat treating the second capping layer to diffuse the metal catalyst remaining in the polycrystalline silicon layer to the second capping layer; Removing the second capping layer; Patterning the polycrystalline silicon layer to form a semiconductor layer; Forming a gate insulating film and a gate electrode on the substrate; And Injecting a second impurity into the semiconductor layer; The first impurity is a method of manufacturing a thin film transistor, characterized in that to implant the n-type impurities in 1 * e ¹¹ / cm ² to 3 * e ¹⁵ / cm ² . The method of claim 1, The first impurity is a method of manufacturing a thin film transistor, characterized in that the element of the Group 5 on the periodic table. The method of claim 1. The first impurity is a method of manufacturing a thin film transistor, characterized in that any one selected from the group consisting of phosphorus (P), PH _x ⁺ or P ₂ H _x (where X = 1,2,3 ...). . The method of claim 1, The second capping layer is a method of manufacturing a thin film transistor, characterized in that formed with a silicon nitride film. The method of claim 1, The second capping layer is a thin film transistor manufacturing method, characterized in that formed in a thickness of 10 to 1000 내지. The method of claim 1, The third heat treatment is a method of manufacturing a thin film transistor, characterized in that carried out in a temperature range of 500 ℃ to 800 ℃. The method of claim 1, The third heat treatment is a method of manufacturing a thin film transistor, characterized in that for heating for 1 minute to 120 minutes. The method of claim 1, The second capping layer is a method of manufacturing a thin film transistor, characterized in that the refractive index is 1.94 or less. The method of claim 1, The first capping layer is a method of manufacturing a thin film transistor, characterized in that formed as a single layer or a multilayer of a silicon oxide film or a silicon nitride film. The method of claim 1, The heat treatment is a method of manufacturing a thin film transistor, characterized in that consisting of a first heat treatment step and a second heat treatment step. The method of claim 10, The first heat treatment step is a step of diffusing a metal catalyst through the first capping layer to move to the interface of the amorphous silicon layer, the method of manufacturing a thin film transistor. The method of claim 10, The second heat treatment step is a step of crystallizing the amorphous silicon layer into a polycrystalline silicon layer by the diffusion metal catalyst. The method of claim 12, The second heat treatment step is a method of manufacturing a thin film transistor, characterized in that performed in a temperature range of 400 to 800 ℃. The method of claim 12, The second heat treatment step is a method of manufacturing a thin film transistor, characterized in that performed for more than 1 minute 20 hours. The method of claim 1, The second impurity is a method of manufacturing a thin film transistor, characterized in that any one selected from the group consisting of boron (B), aluminum (Al), gallium (Ga) and indium (In). The method of claim 1, The metal catalyst is Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd or Pt manufacturing method of a thin film transistor, characterized in that at least one. The method of claim 1, The first capping layer is a thin film transistor manufacturing method, characterized in that formed in a thickness of 1Å to 2000Å.

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