KR100685848B1 - Fabricating method for thin film transistor - Google Patents

Abstract

A method for manufacturing a thin film transistor is provided to control an amount of a metal catalyst and to minimize the amount of the metal catalyst remaining on a multi crystal silicon layer by using a capping layer controlling diffusion of the metal catalyst. An amorphous silicon layer(120) is formed on a substrate(100). A capping layer(123) is formed on the amorphous silicon layer. A metal catalyst(126) is deposited on the capping layer. The metal catalyst is diffused through the capping layer by performing a first thermal process on the substrate to be moved to an interface of the amorphous silicon layer. A second thermal process is performed on the substrate to crystallize the amorphous silicon layer into a multi crystal silicon layer by the diffused metal catalyst. The capping layer is removed. The multi crystal silicon layer is patterned to form a semiconductor layer. The semiconductor layer is doped with a p-type dopant. N-type impurities are implanted into the semiconductor layer where the p-type dopants are doped and a third thermal process is performed. The n-type impurities are implanted by 1*e11/cm^2 to 3*e15/cm^2.

Description

Fabrication method for thin film transistor {Fabricating method for thin film transistor}

1 is a cross-sectional view of a crystallization process according to the present invention.

2A to 2H are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor according to the present invention.

3 is a graph showing the resistance value characteristics according to the amount of doping according to the present invention.

4 and 5 are graphs showing the characteristics of the thin film transistor according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100. Substrate 110. Buffer layer

120. Amorphous Silicon Layer 123. Capping Layer

123a. First capping layer 123b. Second capping layer

125. Metal Catalyst Layer 126. Metal Catalyst

127. Penetration 128, 130, 130 '. Semiconductor layer

132, 132 '. Source region 134, 134 '. Channel area

136, 136 '. Drain region 138. Gate electrode

140. Gate insulating film 150. Interlayer insulating film

152. Source electrode 154. Drain electrode

H. Heat Treatment Ⅰ. Opening

The present invention relates to a method for manufacturing a thin film transistor, and more particularly, in the method of crystallizing an amorphous silicon layer into a polycrystalline silicon layer by SGS crystallization method, after impregnating phosphorus (P) after SGS crystallization and heat treatment by gettering ( The present invention relates to a method of manufacturing a thin film transistor which minimizes the residual amount of the metal catalyst remaining in the polycrystalline silicon layer.

In general, the polycrystalline silicon layer is widely used as a semiconductor layer for thin film transistors because of its advantages in that it can be applied to high field effect mobility, high speed operation circuits, and CMOS circuits. The thin film transistor using the polycrystalline silicon layer is mainly used in the active element of the active matrix liquid crystal display device (AMLCD) and the switching element and the driving element of the organic light emitting element (OLED).

Crystallization of the amorphous silicon into polycrystalline silicon may include solid phase crystallization, solid phase crystallization, excimer laser crystallization, metal induced crystallization, and metal induced lateral crystallization. The solid phase crystallization method is a method of annealing an amorphous silicon layer over several hours to several tens of hours at a temperature of about 700 ° C. or less, which is a deformation temperature of glass, which is a material for forming a substrate of a display device using a thin film transistor. , The excimer laser crystallization method is to scan the excimer laser to the amorphous silicon layer and to crystallize by heating to a locally high temperature for a very short time, the metal-induced crystallization method is a metal layer such as nickel, palladium, gold, aluminum By contacting or injecting with said metal The crystalline silicon layer is a method of inducing a phase change to the polycrystalline silicon layer, and the metal-induced lateral crystallization method induces crystallization of the amorphous silicon layer sequentially as the silicide generated by the reaction between the metal and silicon continues to propagate to the side. It is a crystallization method using the method.

However, the above-mentioned solid-phase crystallization method has a disadvantage that not only the process time is too long but also the substrate is easily deformed by heat treatment at a high temperature for a long time, and the excimer laser crystallization method requires not only an expensive laser device but also There is a disadvantage that the interfacial property between the semiconductor layer and the gate insulating film is bad due to the protrusion (protrusion), when the crystallization by the metal-induced crystallization method or metal-induced side crystallization method, a large amount of metal catalyst in the crystallized polycrystalline silicon layer There is a disadvantage that the residual current increases the leakage current of the semiconductor layer of the thin film transistor.

At present, a method of crystallizing an amorphous silicon layer using a metal has been studied because it has an advantage that can be crystallized at a lower time than a solid phase crystallization (Solid Phase Crystallization) in a short time. Crystallization using metal is divided into Metal Induced Crystallization (MIC) and Metal Induced Lateral Crystallization (MILC). However, the method using the metal catalyst has a problem in that the device characteristics of the thin film transistor are deteriorated due to contamination by the metal catalyst.

In order to solve the contamination problem of the metal catalyst as described above, a method of manufacturing a polycrystalline silicon layer by a crystallization method using a cover layer (published patent 2003-0060403) has been developed. In the above method, an amorphous silicon layer and a cover layer are deposited on a substrate, a metal catalyst layer is formed thereon, and then the substrate is heat-treated or heat-treated using a laser to diffuse the metal catalyst into the amorphous silicon layer through the cover layer. After forming a seed (seed), it is a method of obtaining a polycrystalline silicon layer using this. The above method has an advantage of preventing metal contamination more than necessary because the metal catalyst diffuses through the cover layer, but there is still a problem that a large amount of the metal catalyst layer is present inside the polycrystalline silicon layer.

The present invention is to solve the above problems of the prior art, in the method of crystallizing an amorphous silicon layer into a polycrystalline silicon layer by the SGS crystallization method, after the crystallization of SGS and n-type impurities phosphorus (P) and the like and heat treatment By gettering, the amount of metal catalyst contributing to the crystallization is controlled by using a capping layer that can control the diffusion of the metal catalyst, and the size of the crystal grains of the polycrystalline silicon layer is largely formed by the controlled metal catalyst. An object of the present invention is to obtain a thin film transistor capable of minimizing the amount of metal catalyst remaining in the polycrystalline silicon layer.

Method of manufacturing a thin film transistor according to the present invention to achieve the above object,

Preparing a substrate;

Forming an amorphous silicon layer on the substrate;

Forming a capping layer on the amorphous silicon;

Depositing a metal catalyst on the capping layer;

First heat treating the substrate to diffuse a metal catalyst through the capping layer to move the substrate to an interface of an amorphous silicon layer;

Crystallizing an amorphous silicon layer into a polycrystalline silicon layer by a metal catalyst diffused by second heat treatment of the substrate;

Removing the capping layer;

Patterning the polycrystalline silicon to form a semiconductor layer;

Doping the semiconductor layer with a p-type dopant; And

And implanting n-type impurities into the p-type dopant-doped semiconductor layer and performing a third heat treatment.

The n-type impurity is a method of manufacturing a thin film transistor, characterized in that the injection of 1 * e ¹¹ / cm ² to 3 * e ¹⁵ / cm ² ,

The n-type impurity is doped in a source / drain region,

The n-type impurity is composed of a Group 5 element on the periodic table,

The n-type impurity is characterized in that any one of P, PH _X ⁺ or P ₂ H _X ,

The third heat treatment is characterized in that the heat treatment in the temperature range of 450 to 800 ℃,

The n-type impurity is characterized in that the acceleration voltage in the range of 10keV to 100keV,

The capping layer is composed of a first capping layer formed on the amorphous silicon layer and a second capping layer located on the first capping layer, characterized in that the opening is formed in the second capping layer,

The first capping layer is formed of a silicon oxide film, and the second capping layer is formed of a silicon nitride film,

The silicon oxide film is characterized in that the thickness of 1 to 20Å,

The silicon nitride film has a thickness of 1 to 2000 kPa.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the figures, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. BRIEF DESCRIPTION OF THE DRAWINGS The drawings depicting preferred embodiments of the invention may be exaggerated for clarity, and like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail.

1 is a cross-sectional view of the crystallization process according to the present invention.

First, as shown in FIG. 1, the buffer layer 110 is formed in a single layer or a plurality of layers by using an insulating film, such as a silicon oxide film or a silicon nitride film, on a substrate 100 such as glass or plastic. In this case, the buffer layer 110 serves to prevent the diffusion of moisture or impurities generated in the substrate 100 or to control the heat transfer rate during crystallization, thereby allowing the crystallization of the amorphous silicon layer to be performed well.

Subsequently, an amorphous silicon layer 120 is formed on the buffer layer 110. In this case, the amorphous silicon layer 120 may use a chemical vapor deposition method or a physical vapor deposition method. In addition, when the amorphous silicon layer 120 is formed or after the formation thereof, dehydrogenation may be performed to lower the concentration of hydrogen.

2A is a cross-sectional view illustrating an example of a process of forming a capping layer including a metal catalyst on the amorphous silicon layer.

Referring to FIG. 2A, a capping layer 123 having a stacked structure of a silicon oxide film and a silicon nitride film is formed on the amorphous silicon layer 120. The capping layer 123 is composed of a first capping layer 123a and a second capping layer 123b and an opening I is formed in the second capping layer 123b. Since the metal catalyst is easily diffused, the capping layer 123 of the present invention forms the first capping layer 123a formed on the amorphous silicon layer 120 as a silicon oxide film and forms the second capping layer 123b. The metal catalyst may be selectively penetrated through the opening I formed of the silicon nitride film and formed on the second capping layer 123b. Meanwhile, the order of materials forming the first capping layer 123a and the second capping layer 123b may be reversed.

In this case, the silicon oxide film used as the first capping layer 123a is formed by a chemical vapor deposition method or a physical vapor deposition method, or by using a thermal oxide film or a natural oxide film formed by UV oxidation, thermal oxidation, oxygen plasma oxidation, or natural oxidation. The chemical vapor deposition method or the physical vapor deposition method may be formed by depositing an oxide film on the amorphous silicon layer 120, and the UV oxidation method, thermal oxidation method, oxygen plasma oxidation method, or natural oxidation method may be performed on the amorphous silicon layer 120. Irradiate UV on the thermal oxide film, or heat the substrate 100 to form a thermal oxide film, or apply an oxygen plasma on the amorphous silicon layer 120 to form a thermal oxide film, or an atmosphere containing oxygen or A natural oxide film is formed by exposing the base surface of the amorphous silicon layer 120 for a few seconds or several tens of minutes in a vacuum. The method to be used to be formed.

At this time, the preferred method of forming the silicon oxide film is a method of forming using oxygen plasma, the process power (power) using 100 to 1000W, the process time is 10 to 1000 seconds, the process pressure is 70 to 400Pa A thermal oxide film is formed using oxygen plasma having conditions. Another method of forming the silicon oxide film is a method of naturally generating the natural oxide film on the amorphous silicon layer 120 by exposing the amorphous silicon layer 120 on the atmosphere or oxygen containing oxygen.

At this time, the thickness of the silicon oxide film is formed to a thickness of 1 to 20Å. At this time, the minimum thickness of the silicon oxide film should be 1Å or more, because the thickness of 1Å or less almost no silicon oxide film is present, so that the metal catalyst penetrates directly into the amorphous silicon layer 120 and the crystal grain size during the crystallization of the polycrystalline silicon layer. This is because it cannot be formed large, and when the thickness is 20 GPa or more, the metal catalyst hardly passes through the silicon oxide film and crystallization is difficult.

Subsequently, a second capping layer 123b having an opening I is formed on the silicon oxide layer used as the first capping layer 123a, and the second capping layer 123b is formed by a metal catalyst. It is preferable to form a silicon nitride film that can diffuse through, and is formed by a method such as chemical vapor deposition or physical vapor deposition. At this time, the thickness of the second capping layer 123b is formed to 1 to 2000Å. In the present invention, the metal catalyst may selectively penetrate into the amorphous silicon layer 120 through the silicon nitride film having the opening I formed, thereby controlling the amount and position of the seed.

2B is a cross-sectional view of a process of forming a metal catalyst layer on the capping layer.

Referring to FIG. 2B, a metal catalyst is deposited on the second capping layer 123b including the opening I to form the metal catalyst layer 125. At this time, the metal catalyst is any one or more of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd or Pt, preferably nickel ( Ni) is used.

In this case, in general, the metal-induced crystallization method or the metal-induced side crystallization method should carefully control the thickness or density of the metal catalyst, which is left on the surface of the polycrystalline silicon layer after crystallization, so that the leakage current of the thin film transistor This is because it causes a problem such as increasing the current). However, in the present invention, the metal catalyst layer 125 may be formed thick without precisely controlling the thickness or density. This filters the metal catalyst diffused by the silicon oxide film formed by the first capping layer 123a so that only a small amount of the metal catalyst contributes to the crystallization, and most of the metal catalyst diffuses through the silicon oxide film and contributes to the crystallization. You will not.

2C is a cross-sectional view of a process of forming a amorphous silicon layer as a polycrystalline silicon layer by heat treating a substrate.

Referring to FIG. 2C, the substrate 100 is heat treated (H) to diffuse or penetrate 127 the metal catalyst 126 of the metal catalyst layer 125 to the capping layer 123, and to form an amorphous layer with the capping layer 123. The amorphous silicon layer 120 crystallizes into a polycrystalline silicon layer by moving to the interface of the silicon layer 120 to form a seed, which is a nucleus of crystallization, and growing the seed in the crystallization direction. That is, the metal catalyst 126 combines with silicon of the amorphous silicon layer 120 to form metal silicide, and the metal silicide acts as a nucleus of crystallization and induces crystallization of the amorphous silicon layer 120. In this case, the heat treatment process may be performed on the entire substrate 100 or the capping layer 123 and the amorphous silicon layer 120, such as a furnace process, a rapid thermal annealing (RTA) process, a UV process, a plasma process, or a laser process. Use a process that can be heat treated.

In this case, the heat treatment process may be performed twice. In the first heat treatment process, the metal catalyst 126 moves to an interface between the capping layer 123 and the amorphous silicon layer 120 to form a seed. The second heat treatment process is a process in which the amorphous silicon layer 120 crystallizes into a polycrystalline silicon layer by the seed. At this time, the process temperature of a 1st heat treatment process is 200-800 degreeC, and the process temperature of a 2nd heat treatment process is 400-1300 degreeC. In addition, after the first heat treatment process, the metal catalyst layer 125 is removed to prevent diffusion or penetration of the metal catalyst during the second heat treatment process.

Accordingly, the size and uniformity of grains of the polycrystalline silicon layer are determined according to the number, density, or position of seeds generated on the interface between the capping layer 123 and the amorphous silicon layer 120, which is the capping layer 123. It is determined not only by the diffusion characteristics of the metal catalyst 126 in the inside but also by the density of the metal catalyst layer 125. That is, the lower the density of the metal catalyst layer 125, the smaller the diffusion of the metal catalyst 126 in the capping layer 123 (if the amount is too small diffusion does not crystallize, so an appropriate amount should be diffused) The grain size of the polycrystalline silicon layer becomes large. In addition, by controlling the position of the opening I formed on the second capping layer 123b, the position and direction in which the amorphous silicon layer 120 is crystallized into the polycrystalline silicon layer may be adjusted.

In this case, the capping layer 123 and the metal catalyst layer 125 for controlling the diffusion or penetration 127 of the metal catalyst 126 are formed on the amorphous silicon layer 120 as described above, and then heat treated to form the amorphous silicon layer. The crystallization method of forming the 120 into a polycrystalline silicon layer having a large grain size is referred to as a super grain silicon (SGS) crystallization method.

2D is a cross-sectional view of a process of manufacturing a thin film transistor using the polycrystalline silicon layer manufactured by the present invention.

Referring to FIG. 2D, the semiconductor layer 128 is formed by patterning the polycrystalline silicon layer crystallized by the SGS crystallization method including the capping layer (123 of FIG. 2C) on the substrate 100 on which the buffer layer 110 is formed. At this time, the semiconductor layer 128 has only a small amount of the metal catalyst remaining in the semiconductor layer 128 by the capping layer (123 of FIG. 2C), and thus has better leakage current characteristics than other crystallization methods.

Subsequently, as shown in 2e, a gate insulating layer 140 is formed on the substrate 100 on which the semiconductor layer 128 is formed. The gate insulating layer 140 forms a silicon oxide film or a silicon nitride film as a single layer or a multilayer. .

Subsequently, a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd) on the gate insulating layer 140, or multiple aluminum alloys are laminated on a chromium (Cr) or molybdenum (Mo) alloy. The gate electrode metal layer (not shown) is formed as a layer, and the gate electrode metal layer is etched by a photolithography process to form the gate electrode 138 in a predetermined portion corresponding to the semiconductor layer 128.

Subsequently, as shown in FIG. 2F, the source region 132 and the drain region 136 are formed by doping a predetermined type of impurity ions using the gate electrode 138 as a mask. The impurity ion is a p-type impurity, and the p-type impurity may be selected from the group consisting of boron (B), aluminum (Al), potassium (Ga) and indium (In). In the present invention, the impurity ion is a p-type impurity. Form a P-type thin film transistor using. In this case, an impurity doped region between the source region 132 and the drain region 136 which is not doped with impurities serves as a channel region 134. However, the doping process may be performed by forming a photoresist before forming the gate electrode 138.

2G is a cross-sectional view illustrating a gettering process for removing a metal catalyst remaining in a semiconductor layer by heat treatment.

As illustrated in FIG. 2G, a gettering process is performed by implanting (doping) an n-type impurity and performing a third heat treatment to remove trace metal catalyst remaining in the semiconductor layer 130. The gettering process is performed by doping an impurity in the source / drain regions 132 and 134 in which a small amount of p-type impurities remain. The impurities include P, PH _x ⁺ , and P ₂ H _x (where n is an impurity). , X = 1, 2, 3 ...), and Group 5 elements of the periodic table. Preferably, the n-type impurity uses phosphorus (P) and the dose is 1 * e ¹¹ / cm ² to 3 * e ¹⁵ / cm ² when doping. When the doping amount is less than 1 * e ¹¹ / cm ² , the amount of phosphorus (P) to be injected is not sufficient, so that a small amount of metal catalyst (Ni, etc.) remaining in the semiconductor layer 130 is sufficient. When the dose amount is not removed, the doping amount of 3 * e ¹⁵ / cm ² or more, as shown in Figure 3, the resistance value is increased, because the activation is not well (activation) appears as an electrical component. Therefore, the phosphorus (P), which is the n-type impurity, has an acceleration voltage of 10 keV to 100 keV, and the projection distance Rp representing the linear distance from the surface as an average movement path in the vertical direction is an interface between the polycrystalline silicon layer and the gate insulating film. It should be within ± 500Å at. In addition, the third heat treatment process is carried out at a temperature range of 450 ℃ to 800 ℃ to remove the trace metal catalyst remaining in the semiconductor layer 130.

By doping n-type impurities in the source / drain regions and performing a third heat treatment as described above, it can be seen that the characteristics of the P-type thin film transistor are improved as shown in FIGS. 4 and 5. 4 (a) and 5 (a) are graphs showing the characteristics of Vg and Id before gettering with n-type impurities, and FIGS. 4b and 5b are phosphorus (P) It is a graph showing the characteristic after gettering Ni. By the above process, it can be seen that the S-factor is 0.5 to about 0.3v / dec, the threshold voltage V _th is 2V to 1V, and the off improvement is improved from ˜e ¹² to ˜e ¹³ .

Subsequently, as shown in FIG. 2H, an interlayer insulating layer 150 that protects a lower structure is formed on the gate electrode 138 on the gate insulating layer 140, and then the interlayer insulating layer 150 and the gate insulating layer 140 are formed. A predetermined region is etched to form a contact hole, and source / drain electrodes 152 and 154 filling the contact hole are formed to obtain a gettered source region 132 ′, a drain region 136 ′, and a channel region 134 ′. The thin film transistor including the semiconductor layer 130 ′ is completed.

Accordingly, in the thin film transistor, the amount of the metal catalyst is controlled by the capping layer so that a small amount of the metal catalyst remains compared to the metal induction crystallization method or the induction side crystallization method, thereby forming a semiconductor layer having a large grain size of the polycrystalline silicon layer. .

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Many variations and modifications will be possible.

As described above, according to the present invention, the amount of the metal catalyst contributing to the crystallization is controlled by using a capping layer capable of controlling the diffusion of the metal catalyst, and the size of the crystal grains of the polycrystalline silicon layer is increased by the controlled metal catalyst. Forming and minimizing the amount of metal catalyst remaining in the polycrystalline silicon layer has an effect that can be produced a thin film transistor with excellent characteristics.

Claims (10)

Preparing a substrate; Forming an amorphous silicon layer on the substrate; Forming a capping layer on the amorphous silicon; Depositing a metal catalyst on the capping layer; First heat treating the substrate to diffuse a metal catalyst through the capping layer to move the substrate to an interface of an amorphous silicon layer; Crystallizing an amorphous silicon layer into a polycrystalline silicon layer by a metal catalyst diffused by second heat treatment of the substrate; Removing the capping layer; Patterning the polycrystalline silicon to form a semiconductor layer; Doping the semiconductor layer with a p-type dopant; And And implanting n-type impurities into the p-type dopant-doped semiconductor layer and performing a third heat treatment. The n-type impurity is a method of manufacturing a thin film transistor, characterized in that the injection in 1 * e ¹¹ / cm ² to 3 * e ¹⁵ / cm ² . The method of claim 1, And the n-type impurity is doped in a source / drain region. The method of claim 1, And said n-type impurity is a Group 5 element of the periodic table. The method of claim 1, The n-type impurity is a method of manufacturing a thin film transistor, characterized in that any one of P, PH _X ⁺ or P ₂ H _X. The method of claim 1, The third heat treatment is a method of manufacturing a thin film transistor, characterized in that the heat treatment in the temperature range of 450 to 800 ℃. The method of claim 1, The n-type impurity is a thin film transistor manufacturing method characterized in that the acceleration voltage in the range of 10keV to 100keV. The method of claim 1, The capping layer includes a first capping layer formed on an amorphous silicon layer and a second capping layer positioned on the first capping layer, and the opening is formed in the second capping layer. Manufacturing method. The method of claim 7, wherein And the first capping layer is formed of a silicon oxide film, and the second capping layer is formed of a silicon nitride film. The method of claim 8, The thickness of the silicon oxide film is a method of manufacturing a thin film transistor, characterized in that 1 to 20Å. The method of claim 8,  The thickness of the silicon nitride film is a method of manufacturing a thin film transistor, characterized in that 1 to 2000Å.

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