KR20090072099A - Polycrystalline silicon thin film transistor using milc and method for fabricating the same - Google Patents

Abstract

A polycrystalline silicon thin film transistor using metal induced lateral crystallization and a manufacturing method thereof are provided to perform a property of high performance and high quality and to have a LDD(Lightly Doped Drain) structure by including a region having low resistance and high resistance inside a source region and a drain region. An amorphous silicon layer is formed on an insulation substrate(10). An active region(20c) is formed by patterning the silicon layer. A first crystallization induced metal pattern and a second crystallization induced metal pattern are partly formed in a position in which a source region(25a,60b) and a drain region(25b,60c) of the active region are formed. A part of a top layer of an exposed active layer is etched by using the first crystallization induced metal pattern and the second crystallization induced metal pattern as a mask. The active region made of amorphous silicon is crystallized through a MIC(Metal Induced Crystallization) and MILC(Metal Induced Lateral Crystallization) thermal process using the first crystallization induced metal pattern and the second crystallization induced metal pattern. A gate insulation film and a gate electrode(50) are formed on the crystallized active region.

Description

Polycrystalline silicon thin film transistor using metal-induced lateral crystallization and its manufacturing method {POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR USING MILC AND METHOD FOR FABRICATING THE SAME}

The present invention provides a relatively lightly doped drain (LDD) structure by forming a relatively thin thickness of a portion of the source and drain regions adjacent to the channel region, and having regions having low and high resistances in the source and drain regions, respectively. It is possible to manufacture polycrystalline silicon thin film transistor having high performance and high quality characteristics, and to continuously deposit amorphous silicon and n ⁺ silicon deposition and to crystallize by one heat treatment, and to make source and drain regions without separate ion doping process The present invention relates to a polycrystalline silicon thin film transistor using a metal-induced lateral crystallization which can be formed, and a manufacturing method thereof.

Thin film transistors used in display devices such as LCDs and OLEDs are generally activated by depositing silicon on transparent substrates such as glass and quartz, forming gate and gate electrodes, injecting dopants into source and drain regions, and then performing annealing treatment. After forming, the insulating layer is formed. An active layer forming a source region, a drain region, and a channel region of a thin film transistor is usually formed by depositing a silicon layer on a transparent substrate such as glass by using a chemical vapor deposition (CVD) method.

However, the silicon layer deposited directly on the substrate by a method such as CVD has a low electron mobility as an amorphous silicon film. As display devices using thin film transistors require fast operation speeds and are miniaturized, the degree of integration of the driving IC is increased and the aperture ratio of the pixel area is reduced. Therefore, the driving circuit is formed simultaneously with the pixel TFTs by increasing the electron mobility of the silicon film, and individual pixels are It is necessary to increase the aperture ratio.

For this purpose, a technique is used in which an amorphous silicon layer is heat-treated to crystallize into a crystalline silicon layer having a polycrystalline structure having high electron mobility. Various methods have been proposed to crystallize an amorphous silicon layer of a thin film transistor into a crystalline silicon layer.

First, solid phase crystallization (SPC) is a method of annealing an amorphous silicon layer over several hours to several tens of hours at a temperature of 600 ° C. or less, which is a deformation temperature of glass forming a substrate. Since the SPC method requires a long time for heat treatment, when the productivity is low and the area of the substrate is large, there is a problem that deformation of the substrate may occur during a long heat treatment process even at a temperature of 600 ° C. or less.

Excimer Laser Crystallization (ELC) is a method in which an excimer laser is injected into a silicon layer to instantaneously crystallize the silicon layer by generating a locally high temperature for a very short time. The ELC method has a technical difficulty in precisely controlling the scanning of the laser light, and since only one substrate can be processed at a time, there is a problem that productivity is lowered than when batch processing of several substrates at the same time in the blast furnace.

In order to overcome the disadvantages of the conventional silicon layer crystallization method, when a metal such as nickel, gold, aluminum, or the like is contacted with or injected into the silicon, the amorphous silicon changes into crystalline silicon even at a low temperature of about 200 ° C. The phenomenon in which is derived is used. This phenomenon is called metal induced crystallization (MIC). When a thin film transistor is manufactured using the MIC phenomenon, metal remains in the crystalline silicon constituting the active layer of the thin film transistor. A problem arises that causes current leakage.

Recently, the metal induced side crystallization (Metal Induced Lateral Crystallization) does not directly induce phase change of silicon, but the silicide generated by the reaction of metal and silicon continues to propagate to the side, leading to the crystallization of silicon sequentially. : A method of crystallizing a silicon layer using a MILC phenomenon has been proposed (see SW Lee & SK Joo, IEEE Electron Device Letter, 17 (4), p.160, (1996)).

Nickel and palladium are known as metals that cause such a MILC phenomenon, and in the case of crystallizing the silicon layer using the MILC phenomenon, the silicide interface including the metal moves to the side as the phase change of the silicon layer propagates. In the silicon layer crystallized using, there is almost no metal component used to induce crystallization, which does not affect the current leakage and other operating characteristics of the transistor activation layer. In addition, in the case of using the MILC phenomenon, the crystallization of silicon can be induced at a relatively low temperature of 300 ° C to 500 ° C, and thus, multiple substrates can be simultaneously crystallized without damaging the substrate by using a furnace.

Conventional methods of crystallizing silicon layers constituting TFTs using MIC and MILC phenomena pattern an amorphous silicon layer formed on an insulating substrate by photolithography to form an active layer, and then form a gate insulating layer and a gate electrode on the active layer. do.

Subsequently, the entire substrate is doped with impurities using a gate electrode as a mask to form a source region, a channel region, and a drain region in the active layer, and then the entire substrate is partially formed in a partially formed MILC source metal layer in the source region and the drain region. The source and drain regions immediately below the metal layer remaining by annealing at a temperature of 300 ° C to 500 ° C are crystallized by MIC phenomenon and the portion of the source and drain regions where the metal layer is not covered (metal-offset) and the channel region under the gate electrode. Silver induces crystallization by the MILC phenomenon induced from the remaining metal layer.

However, the conventional method of manufacturing a polycrystalline thin film transistor using MILC has a problem in that source / drain resistance is high and ions must be implanted using expensive ion implantation equipment. In addition, since the heat treatment must be performed two or more times for crystallization and source / drain activation of the amorphous silicon, the process cost is high and the process takes a long time.

On the other hand, in the conventional manufacturing of TFTs having a top gate structure using a laser crystallization method (i.e., the case of using an excimer laser according to the above-mentioned excimer laser crystallization (ELC)), it is generally amorphous. The process of simultaneously depositing n ⁺ silicon layers on the silicon layer is not adopted. The reason is that the laser crystallization method does not use the process of forming / using the crystallized metal film pattern used for MILC crystallization, so if the n ⁺ silicon layer in the channel region is removed, a separate patterning process (ie, an etching mask is required) Because you have to go through

On the other hand, in the case of polycrystalline thin film transistors, unlike in the case of amorphous thin film transistors, the leakage current is large, and therefore, an LDD structure is required to suppress them (IEEE Trans. Electron Devices, Vol. 40, No. 5, pp.938, 1993), in particular, in the case of N-type thin film transistors, it is common to form LDD structures to reduce leakage current due to the hot electron effect. It is common to inject ions less than the concentration into the region where the LDD is to be formed by a separate process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to form a relatively thin thickness of a portion of a source and a drain region adjacent to a channel region, so that regions having low and high resistances in the source and drain regions, respectively, are provided. The present invention provides a polycrystalline silicon thin film transistor using a metal-induced lateral crystallization capable of manufacturing a polycrystalline silicon thin film transistor having an LDD structure substantially and having high performance and high quality.

Another object of the present invention is to provide a top gate method for continuously depositing amorphous silicon and n ⁺ silicon deposition and forming a source region and a drain region without performing a separate ion doping process while crystallization is performed in one heat treatment. The present invention provides a polycrystalline silicon thin film transistor and a method of manufacturing the same.

Another object of the present invention is a top gate polycrystalline silicon which can reduce the process time and cost by performing crystallization of amorphous silicon and activation of impurities implanted into the source and drain regions in one heat treatment. A thin film transistor and its manufacturing method are provided.

Another object of the present invention is to provide a top gate polycrystalline silicon thin film transistor capable of forming an LDD structure using a single ion implantation using n ⁺ silicon and a method of manufacturing the same.

The present invention for achieving the above object, forming an amorphous silicon layer on the insulating substrate, and patterning it to form an activation region; Partially forming first and second crystallization inducing metal patterns in the source region and the drain region formation position of the activation region; Etching a portion of the upper layer of the exposed active layer by using the first and second crystallization inducing metal patterns as an etching mask; Crystallizing an activation region made of amorphous silicon through MIC and MILC crystallization heat treatment using the first and second crystallization inducing metal patterns; And forming a gate insulating film and a gate electrode on the crystallized activation region.

In addition, according to another aspect of the invention, the present invention comprises the steps of continuously forming an amorphous silicon layer and n ⁺ silicon layer on the insulating substrate, patterning it to form an activation region; Partially forming first and second crystallization inducing metal patterns in the source region and the drain region forming positions of the activation region on the n + silicon layer; By using the first and second crystallization induction metal pattern as an etching mask to sequentially expose the n ⁺ silicon layer and a portion of the upper layer of the active layer to define a first source region and a first drain region consisting of n ⁺ silicon layer step; Crystallizing a first source region made of n ⁺ silicon layer and an activation region made of amorphous silicon with M ⁺ and MILC crystallization heat treatment using the first and second crystallization inducing metal patterns; And forming a gate insulating film and a gate electrode on the crystallized activation region.

The present invention may further include forming a source region and a drain region by implanting ions into a substrate using the gate electrode as an ion implantation mask, wherein the source region and the drain region each have a different resistance value. It is preferable to include the formed LDD structure.

The present invention may further include forming a source region and a drain region by implanting ions into a substrate at a concentration lower than that of the n ⁺ silicon layer using the gate electrode as an ion implantation mask. The drain region may also include an LDD structure composed of regions having different ion implantation concentrations.

Furthermore, the present invention may further include removing the first and second crystallization inducing metal patterns after crystallizing the activation region.

In this case, the first and second crystallization induction metal pattern is preferably formed by a lift off method using a photoresist.

The first and second crystallization inducing metal patterns are preferably formed in the source region and the drain region so as to have a micrometer offset from both side ends of the portion where the channel region is to be formed, respectively.

According to another feature of the invention, the present invention is a transparent insulating substrate; A channel region made of crystalline silicon not implanted with ions on the transparent insulating substrate; A first source region and a first drain region each formed on one side and the other side of the channel region on the transparent insulating substrate and made of crystalline silicon implanted with ions and having a first resistance value; A second source region and a first source region formed on the transparent insulating substrate and formed outside the first source region and the first drain region, respectively; 2 drain region; A gate insulating layer formed on the channel region; And a top gate polycrystalline silicon thin film transistor including a gate electrode formed on the gate insulating layer.

The second source region and the second drain may be thicker than the first source region and the first drain region, respectively.

The polycrystalline silicon thin film transistor may further include a third source region and a third drain region formed on the second source region and the second drain region, respectively, and formed of n ⁺ silicon layers.

Further, the ion implantation concentration of the second source region and the second drain region is preferably set lower than the n ⁺ silicon layer of the third source region and the third drain region.

In this case, the second source region and the second drain are amorphous silicon converted to crystalline silicon through MIC crystallization heat treatment using first and second crystallization induction metal patterns, respectively, and the first source region and the first drain region. The and channel regions are amorphous silicon converted to crystalline silicon through MILC crystallization heat treatment using the first and second crystallization inducing metal patterns, respectively.

As described above, in the present invention, the thickness of a portion of the source and drain regions adjacent to the channel region is relatively thin, and the LDD is substantially provided by providing regions having low and high resistances in the source and drain regions, respectively. With this structure, a polycrystalline silicon thin film transistor having high performance and high quality characteristics can be manufactured.

In addition, in the present invention, amorphous silicon and n ⁺ silicon deposition may be continuously deposited and crystallized by a single heat treatment, and source and drain regions may be formed without a separate ion doping process. In this case, it is also possible to form the LDD region in the source region and the drain region by performing one ion doping process.

Furthermore, in the present invention, the process time and the process cost can be reduced by performing crystallization of amorphous silicon and activating impurities implanted into the source and drain regions in one heat treatment.

In order to fully understand the present invention, the advantages of the operability of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1A to 1F are cross-sectional views illustrating a method of manufacturing a polycrystalline silicon thin film transistor using metal induced side crystallization (MILC) according to a first embodiment of the present invention.

Referring to FIG. 1A, an amorphous silicon layer 20 is deposited on a transparent insulating substrate 10 such as a glass substrate by using low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD) in a CVD chamber. Deposition and patterning is performed to a thickness of 70 nm to 100 nm to define the activation region.

Subsequently, as shown in FIG. 1B, the first and second crystallization induction metal patterns 30a and 30b are lifted off using photoresist PR at the source and drain region formation positions on the activation region 20a made of amorphous silicon, respectively. Form by the lift-off method. In more detail, the crystallization induced metal patterns 30a and 30b are partially disposed on the source region and the drain region with a few micrometer offset (interval) from both ends of the channel region formed at the center of the activation region 20a using a lift off method. To be formed.

The material usable as the crystallization induction metal patterns 30a and 30b is the same as the material that can be used for MILC, for example Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Any one of Mo, Tr, Ru, Rh, Cd, Pt may be used.

Thereafter, by using the crystallization induction metal pattern (30a, 30b) as an etching mask, a portion of the upper layer of the exposed active region 20a, including the portion where the channel region is to be formed, is removed by dry etching to a predetermined depth as shown in FIG. 1C. .

Forming the modified activation region 20b from which a portion of the upper layer of the exposed activation region 20a is removed may be the source region 25a and the drain region 25b adjacent to the channel region 25c as shown in FIG. 1F. By forming a relatively thin thickness of a portion of the thin film, implanting impurities in a subsequent process, and then diffusing the impurity ions by heat treatment, the low-resistance regions each having a low resistance value in the source region 25a and the drain region 25b, respectively. And high resistance regions 251a and 253a having high resistance values 251b and 253b.

As described above, when the source region 25a and the drain region 25b are formed to include the low resistance regions 251b and 253b having low resistance values and the high resistance regions 251a and 253a having high resistance values, respectively. As a result, the electrical characteristics of the TFT can be improved by exhibiting the same effect as that of the LDD structure capable of reducing the leakage current of the TFT.

When the etching process is completed, the amorphous silicon of the deformed activation region 20b is crystallized through heat treatment using the crystallization induction metal patterns 30a and 30b to obtain an activation region 20c made of crystalline silicon. The heat treatment is performed at 400 to 500 ° C. for 30 minutes to 4 hours, and the amorphous silicon thin film located under the crystallization induction metal patterns 30a and 30b is crystallized by MIC and exposed to the amorphous activation region 20b. The silicon thin film is crystallized by MILC.

Thereafter, after the crystallization heat treatment is completed, the crystallization induction metal patterns 30a and 30b formed on the activation region 20c are removed, as shown in FIG. 1D.

When the crystallization heat treatment process is completed, a polycrystalline thin film transistor may be manufactured by forming a gate insulating layer 40 and a gate electrode 50 on the channel region as shown in FIG. 1E.

That is, a silicon oxide film or a silicon nitride film is formed as an insulating film for forming a gate insulating film, for example, and a conductive material such as W, Pt, Ti, Al, Ni, Mo, etc. is used as the metal film for forming a gate electrode. After forming sequentially, an etch mask (not shown) is formed thereon with photoresist. Subsequently, the gate insulating film forming insulating film and the gate electrode forming metal film are sequentially etched using an etching mask to form the gate electrode 50 and the gate insulating film 40.

After the gate electrode 50 and the gate insulating film 40 are formed, the source region 25a and the drain region 25b having the LDD (Lightly Doped Drain) structure are then formed using ion doping, as shown in FIG. 1F. Can be formed.

That is, the N-type or P-type dopant ions are implanted into the activation region 20c formed of the crystallization layer using the etching mask as an ion implantation mask to define the source region 25a and the drain region 25b. In this case, the dopant to be injected may be P, PH ₃ or As in the case of N-type, and B, B ₂ H ₆ or BH ₃ in the case of P-type. As a result, the region where the dopant is not injected between the source region 25a and the drain region 25b becomes the channel region 25c.

When the doping of the source region 25a and the drain region 25b is completed, the substrate 10 is subjected to heat treatment for 1 hour to 5 hours at a temperature between 400 ° C. and 600 ° C., for example, 580 ° C. under a hydrogen atmosphere. By activating the dopant implanted in the source region and the drain region, the dangling bond is removed and the leakage current of the manufactured thin film transistor is reduced.

Finally, according to a well-known process, an interlayer insulating film is formed on the substrate 10 and a portion of the interlayer insulating film is etched to form a contact window for the source region 25a and the drain region 25b. (Not shown) is formed using a conductive material to complete the thin film transistor.

In general, when fabricating a MOSFET, an LDD structure is formed through two ion implantation of regions having different ion implantation concentrations in the source and drain regions, but as described above, in the present invention, the source region 25a adjacent to the channel region 25c is formed. And when the thickness of a portion of the drain region 25b is formed relatively thin, the impurities are implanted, and the impurity ions are diffused by heat treatment, each of the source region 25a and the drain region 25b has a low resistance value. Low resistance regions 251b and 253b and high resistance regions 251a and 253a having high resistance values are provided.

As a result, the source region 25a and the drain region 25b of the present invention have a low-resistance and high-resistance region structure exhibiting the same effect as that of the LDD structure capable of substantially reducing the leakage current of the TFT. A polycrystalline silicon thin film transistor having characteristics can be formed by only one ion implantation.

2A to 2E are cross-sectional views illustrating a method of manufacturing a polycrystalline silicon thin film transistor using metal induced side crystallization according to a second preferred embodiment of the present invention.

Referring to FIG. 2A, an amorphous silicon layer 20 on an insulating substrate 10, such as a glass substrate, is about 70 nm in a CVD chamber by using a xylene gas by low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD). To 100 nm, and n ⁺ silicon layer 60 is continuously deposited to a thickness of 40 nm to 100 nm using a siren gas and a phosphine gas (PH ₃ ). Thereafter, the n ⁺ silicon layer 60 and the amorphous silicon layer 20 are sequentially patterned to define an activation region 20a including the patterned n ⁺ silicon layer 60a and the amorphous silicon layer.

Next, as shown in FIG. 2B, crystallization induction metal patterns 30a and 30b are formed at the source region and the drain region formation position on the n ⁺ silicon layer 60a by a lift-off method using photoresist. In more detail, the crystallization induced metal patterns 30a and 30b may be partially formed on the source region and the drain region with a few micrometer offset (interval) from both ends of the channel region formed at the center of the activation region using a lift off method. do.

The material usable as the crystallization induction metal patterns 30a and 30b is the same as the material that can be used for MILC, for example Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Any one of Mo, Tr, Ru, Rh, Cd, Pt may be used.

Subsequently, using the crystallization induction metal pattern (30a, 30b) as an etching mask, sequentially etching by dry etching to remove the exposed n ⁺ silicon layer 60a and the upper portion of the active region 20a as shown in Figure 2c The n ⁺ silicon layer 60a is separated to define the first source region 60b and the first drain region 60c, and an activation region 20b having a channel region in the center at the bottom thereof is obtained.

When the etching process is completed, the amorphous of the first source region 60b and the first drain region 60c and the deformed activation region 20b made of n ⁺ silicon through heat treatment using the crystallization induction metal patterns 30a and 30b. Silicon is crystallized to obtain a first source region 60b, a first drain region 60c, and an activation region 20c made of crystalline silicon. The heat treatment is performed at 400 to 500 ° C. for 30 minutes to 4 hours, and the first source region 60b and the first drain region 60c and the deformed activation region positioned under the crystallization induction metal patterns 30a and 30b. The amorphous silicon of 20b is crystallized by MIC, and the amorphous silicon of the exposed modified activation region 20b is crystallized by MILC.

In this case, the first source region 60b and the first drain region 60c made of n ⁺ silicon simultaneously activate impurities during the crystallization heat treatment.

Thereafter, after the crystallization heat treatment is completed, the crystallization induction metal patterns 30a and 30b are removed.

When the crystallization heat treatment process is completed, the polycrystalline thin film transistor may be manufactured by forming the gate insulating layer 40 and the gate electrode 50 on the channel region as shown in FIG. 2D. The gate electrode 50 and the gate insulating film 40 can be formed in the same manner as in the first embodiment.

After the gate electrode 50 and the gate insulating film 40 are formed, as shown in FIG. 2E, when ion doping is performed, the source region 25a having a lightly doped drain (LDD) structure is partially formed in each region. The drain region 25b can be formed.

In other words, using the gate electrode 50 as an ion implantation mask, N-type or P-type dopant ions are formed in the first source region 60b and the first drain region 60c and the activation region 20c formed of a crystallization layer. Is injected at a concentration lower than n ⁺ silicon to form LDD regions 251c and 253c in the exposed activation region 20c.

In this case, the dopant to be injected may be P, PH ₃ or As in the case of N-type, and B, B ₂ H ₆ or BH ₃ in the case of P-type. As a result, the region where the dopant is not injected between the source region 25a and the drain region 25b becomes the channel region 25c.

When the doping of the source region 25a and the drain region 25b is completed, the substrate 10 is heat-treated under a hydrogen atmosphere at a temperature between 400 ° C. and 600 ° C., for example, at 580 ° C. for 1 hour to 5 hours. In addition, the dopant implanted in the source region and the drain region is activated, and the dangling bond is removed to reduce the leakage current of the manufactured thin film transistor.

Further, in the second embodiment, similarly to the first embodiment, the activation region 20c forms a relatively thin thickness of a portion of the source region and the drain region, implants impurities, and diffuses impurity ions by heat treatment. Thus, the low resistance regions 251b and 253b having low resistance values and the high resistance regions having high resistance values, that is, the LDD regions 251c and 253c are provided in the source region 25a and the drain region 25b, respectively. .

As described above, in the present invention, the source region 25a and the drain region 25b each have a high concentration implanted first source region 60b and first drain region 60c made of n ⁺ silicon, and a low resistance having a low resistance value. By providing the regions 251b and 253b and the LDD regions 251c and 253c positioned at offset portions having a high resistance value, the LDD structures can reduce the leakage current of the TFTs, thereby improving the electrical characteristics of the TFTs. It becomes possible.

In addition, in the present invention, as described above, amorphous silicon and n ⁺ silicon deposition may be continuously deposited and crystallized by a single heat treatment, and source and drain regions 25a and 25b may be formed without a separate ion doping process.

Furthermore, in the present invention, the crystallization of the amorphous silicon and the activation of the impurities implanted into the source and drain regions 25a and 25b by one heat treatment can reduce the processing time and the processing cost.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The present invention can be applied to a polycrystalline silicon thin film transistor having a LDD structure by forming a relatively thin thickness of a portion of the source and drain regions adjacent to the channel region in a top gate polycrystalline silicon thin film transistor of the top gate type. .

In addition, in the present invention, in the top gate polycrystalline silicon thin film transistor, amorphous silicon and n ⁺ silicon deposition are continuously deposited and crystallization is performed in one heat treatment, and at the same time, source and drain regions are removed without a separate ion doping process. Can be formed. In this case, it is also possible to form the LDD region in the source region and the drain region by performing one ion doping process.

1A to 1F are cross-sectional views illustrating a method of manufacturing a polycrystalline silicon thin film transistor using metal induced side crystallization according to a first embodiment of the present invention.

2A to 2E are cross-sectional views illustrating a method of manufacturing a polycrystalline silicon thin film transistor using metal induced side crystallization according to a second preferred embodiment of the present invention.

* Explanation of Signs of Major Parts in Drawings *

10: insulating substrate 20: amorphous silicon layer

20a-20c: active area 25a, 60b: source area

25b, 60c: drain region 25c: channel region

30a and 30b: crystallization induction metal pattern 40: gate insulating film

50: gate electrode 60, 60a: n ⁺ silicon layer

251a, 253a: high resistance region 251b, 253b: low resistance region

251c, 253c: LDD region

Claims (12)

Forming an amorphous silicon layer on the insulating substrate and patterning it to form an activation region; Partially forming first and second crystallization inducing metal patterns in the source region and the drain region formation position of the activation region; Etching a portion of the upper layer of the exposed active layer by using the first and second crystallization inducing metal patterns as an etching mask; Crystallizing an activation region made of amorphous silicon through MIC and MILC crystallization heat treatment using the first and second crystallization inducing metal patterns; And And forming a gate insulating film and a gate electrode over the crystallized activation region. Continuously forming an amorphous silicon layer and an n ⁺ silicon layer on the insulating substrate, and patterning the silicon layer to form an activation region; Partially forming first and second crystallization inducing metal patterns in the source region and the drain region forming positions of the activation region on the n + silicon layer; By using the first and second crystallization induction metal pattern as an etching mask, sequentially exposed n ⁺ silicon layer and a part of the upper layer of the active layer to define a first source region and a first drain region consisting of n ⁺ silicon layer Doing; Crystallizing a first source region made of n ⁺ silicon layer and an activation region made of amorphous silicon with M ⁺ and MILC crystallization heat treatment using the first and second crystallization inducing metal patterns; And And forming a gate insulating film and a gate electrode over the crystallized activation region. The method of claim 1, further comprising performing ion implantation on a substrate using the gate electrode as an ion implantation mask to form a source region and a drain region, And the source and drain regions each comprise an LDD structure including regions having different resistance values. The method of claim 2, further comprising forming a source region and a drain region by implanting ions into a substrate at a concentration lower than that of the n ⁺ silicon layer using the gate electrode as an ion implantation mask. And the source region and the drain region each comprise an LDD structure including regions having different ion implantation concentrations. The method according to claim 1 or 2, And removing the first and second crystallization induced metal patterns after the crystallization of the activation region. The method according to claim 1 or 2, The first and second crystallization induced metal pattern is a method of manufacturing a polycrystalline silicon thin film transistor using a metal induced side crystallization, characterized in that formed by a lift off method using a photoresist. The method of claim 6, The first and second crystallization-inducing metal patterns are formed in the source region and the drain region to have a micrometer offset from both side ends of the portion where the channel region is to be formed, respectively. Method for manufacturing a transistor. Transparent insulating substrates; A channel region made of crystalline silicon not implanted with ions on the transparent insulating substrate; A first source region and a first drain region each formed on one side and the other side of the channel region on the transparent insulating substrate and made of crystalline silicon implanted with ions and having a first resistance value; A second source region and a first source region formed on the transparent insulating substrate and formed outside the first source region and the first drain region, respectively; 2 drain region; A gate insulating layer formed on the channel region; And A top gate polycrystalline silicon thin film transistor including a gate electrode formed on the gate insulating layer. The method of claim 8, And the second source region and the second drain are formed to be thicker than the first source region and the first drain region, respectively. The method according to claim 8 or 9, And a third source region and a third drain region formed on the second source region and the second drain region, respectively, and formed of n ⁺ silicon layers, respectively. The method of claim 10, The ion gate concentration of the second source region and the second drain region is set to be lower than the n ⁺ silicon layer of the third source region and the third drain region, the top gate type polycrystalline silicon thin film transistor. The method of claim 8, In the second source region and the second drain, amorphous silicon is converted into crystalline silicon through MIC crystallization heat treatment using first and second crystallization inducing metal patterns, respectively. Top gate polycrystalline silicon of the first source region, the first drain region and the channel region, wherein amorphous silicon is converted to crystalline silicon through MILC crystallization heat treatment using the first and second crystallization inducing metal patterns, respectively. Thin film transistor.

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