JP2003203922A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for which the resistance of the source region, the drain region and an LDD region can be controlled precisely, reliability can be improved, a manufacture process is simplified and productivity can be improved, and to provide a manufacturing method. <P>SOLUTION: A crystalline silicon film 103 is formed on a glass substrate, and an amorphous silicon film having conduction type, which is formed on the crystalline silicon film 103, is irradiated with laser beams with a gate electrode 107 as a mask so as to crystallize them. Thus, the source region 109a, the drain region 109b and the LDD regions (108a and 108b) are formed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method. More specifically, the present invention relates to a semiconductor device having a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region and a method for manufacturing the semiconductor device. In particular, the present invention is effective for a semiconductor device using a thin film transistor (TFT) provided on a substrate having an insulating surface,
It can be used for an active matrix type liquid crystal display device, a contact image sensor or a three-dimensional IC (integrated circuit).

[0002]

2. Description of the Related Art In recent years, high-performance semiconductor devices on insulating substrates such as glass have been developed for the realization of large-sized, high-resolution liquid crystal display devices, high-speed, high-resolution contact type image sensors, three-dimensional ICs and the like. Have been attempted to form. Normal,
A thin film silicon semiconductor is generally used for the semiconductor element used in the above-mentioned device. The thin film silicon semiconductor is an amorphous silicon semiconductor.
It is roughly classified into two, that is, a film made of (a-Si) and a film made of a crystalline silicon film.

Since the above-mentioned amorphous silicon semiconductor has a low production temperature, it can be produced relatively easily by a vapor phase method, and it is most commonly used because it has high mass productivity. However, since the physical properties such as conductivity are inferior to those of a silicon semiconductor having crystallinity, in order to realize higher-speed characteristics of the liquid crystal display device, contact image sensor or three-dimensional IC in the future, the crystallinity is There is a strong demand for establishment of a method for manufacturing a thin film semiconductor device made of a silicon semiconductor having the above. Note that polycrystalline silicon, microcrystalline silicon, and the like are known as silicon semiconductors having crystallinity.

As a method for obtaining the above-described crystalline thin film silicon semiconductor, (1) a method of directly forming a film having crystallinity at the time of film formation (2) forming an amorphous semiconductor film, A method of irradiating the amorphous semiconductor film with strong light and crystallizing by the energy (3) Forming an amorphous semiconductor film in advance and applying heat energy to the amorphous semiconductor film to crystallize It is known how to make it.

However, in the above method (1), crystallization progresses at the same time as the film forming step. Therefore, in order to obtain crystalline silicon having a large grain size, it is indispensable to increase the film thickness, and good semiconductor properties are required. It is technically difficult to form the film on the entire surface of the substrate. In addition, the film forming temperature is 600
There is a cost problem in that an inexpensive glass substrate having a high temperature of ℃ or more cannot be used.

Further, in the above method (2), since the crystallization phenomenon in the melting and solidifying process is utilized, the grain boundaries are favorably processed with a small grain size, and high quality crystalline silicon is obtained. However, taking the case of using the most commonly used excimer laser as an example, the stability of the laser beam is not sufficient, so that the entire surface of a large-area substrate is uniformly processed to have uniform crystallinity. There is a problem that it is difficult to obtain a silicon film and it is difficult to obtain a plurality of semiconductor elements having uniform characteristics on the same substrate. Further, there is a problem that the irradiation area of the laser light is small and the throughput is low.

Further, in the above method (3),
Although it has an advantage that it can be applied to a large area as compared with the methods (1) and (2), crystallization requires a heat treatment at a high temperature of 600 ° C. or higher for several tens of hours. That is, in order to use an inexpensive glass substrate and improve throughput, the contradictory problems of lowering the heating temperature and crystallization in a short time must be solved at the same time. Further, in the method (3), since the solid-phase crystallization phenomenon is utilized, the crystal grains even spread out parallel to the substrate surface and have a grain size of several μm.
However, since the grown crystal grains collide with each other to form a grain boundary, the grain boundary acts as a trap level for carriers and causes a decrease in the mobility of the TFT.

A method for producing a silicon film having high quality and uniform crystallinity by applying heat treatment at a lower temperature for a shorter time by applying the method (3) is disclosed in Japanese Patent Laid-Open No. 6-3338.
No. 24, JP-A-6-333825, and JP-A-8-330602. In these publications, a metal element such as nickel is introduced into the surface of an amorphous silicon film to a certain amount, and then heat treatment is performed, so that a low temperature of 600 ° C. or less and a treatment time of about several hours are required. Crystallized.

The mechanism of crystallization is understood by the fact that the generation of crystal nuclei with a metal element as a nucleus occurs at an early stage, and then the metal element serves as a catalyst to promote crystal growth and the crystallization rapidly progresses. To be done. In that sense, these metal elements are hereinafter referred to as catalyst elements. Crystallization of the crystalline silicon film, which has been promoted by these catalytic elements to promote crystallization, has a twin structure, whereas the silicon film crystallized by the usual solid phase growth method has a twin crystal structure. The inside of each columnar crystal is in a state close to a single crystal.

If the catalytic element that promotes crystallization remains in the silicon film, normal TFT characteristics cannot be obtained.
Therefore, JP-A-6-333824 and JP-A-8-2
As disclosed in Japanese Patent No. 36471, gettering using P ions or the like is performed. PSG (phosphorus silicide glass) on the surface of the silicon film containing the catalytic element
A method of providing a film and gettering a catalytic element with phosphorus contained therein, a method of implanting phosphorus ions into a silicon film containing a catalytic element by an ion doping method, a film having phosphorus or boron is provided, and the catalytic element is provided therein. Have been proposed.

In a TFT using a crystalline silicon film obtained by a method of promoting crystallization by the above catalytic element, the ratio of on-current and off-current (leakage current) is large,
High pressure resistance is required. As a method of reducing the off-current, a dual gate structure, a thin film of polysilicon, and an LDD (Lightly Doped Drain) structure have been considered, but all have advantages and disadvantages. Dual gate structure is 2
This is a method in which more than one transistor is connected in parallel and the gate electrode is commonly used, and the off current is reduced by relaxing the electric field in the drain region when the transistors are turned off. However, it is not desirable to form two or more transistors in a limited space because it leads to a reduction in the aperture ratio of the picture element.

The thinning of the polysilicon is a very simple method, and the off current is reduced by increasing the resistance between the source region and the drain region by thinning the film. However, the expected reduction effect has not been obtained. The LDD (Lightly Doped Drain) structure is, for example,
When the source region and the drain region are n + layers, the n − layer is provided between the channel region and the source region and between the channel region and the drain region. Usually, after forming a gate electrode on a polysilicon film, low concentration ions are implanted using the gate electrode as a mask to form an n-layer. Then, after forming a sidewall insulator on the sidewall of the gate electrode, ion implantation is performed again to form an n + layer.

As another method, using the gate electrode as a mask, an n-layer is formed by oblique rotation ion implantation, and then an n + layer is formed by a normal ion implantation method. This method is called a gate overlap LDD structure because the n − layer deeply enters the channel region and the gate electrode largely overlaps.

In either structure, the off-current can be reduced by relaxing the electric field in the drain region to improve the breakdown voltage. However, when a voltage is applied to the gate electrode, the n-layer in the source region is reduced. The current resistance is reduced due to the parasitic resistance of. On the other hand, in the gate overlap LDD structure, the n − layer exists below the gate electrode, so that the current driving capability is not impaired.

[0015]

However, in the above semiconductor device, in the method of forming the source region, the drain region (high-concentration portion) and the LDD region (low-concentration portion) by ion implantation, fluctuations in ion implantation conditions are involved. Also, there is a problem that the resistance of the LDD region largely varies due to the influence of the film thickness distribution of the gate insulating film, which makes control difficult. Further, since the ion implantation is required a plurality of times and the manufacturing process such as the formation of the sidewall insulator or the oblique rotation ion implantation becomes complicated, there is a problem that the process is not efficient.

Therefore, an object of the present invention is to provide a source region,
The resistance of the drain region and LDD region can be controlled accurately,
It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof, which can improve reliability, simplify a manufacturing process, and improve productivity.

[0017]

To achieve the above object, a semiconductor device of the present invention comprises a crystalline silicon film formed on a substrate having an insulating surface, and a crystalline silicon film formed on the crystalline silicon film. A source region and a drain region formed at a predetermined interval, and a source-side height formed between the source region and the drain region on the crystalline silicon film so as to be adjacent to the source region. A resistance region, and a drain-side high resistance region formed so as to be adjacent to the drain region between the source region and the drain region on the crystalline silicon film,
A gate insulating film formed to cover the crystalline silicon film and the source region, the drain region, the source-side high resistance region and the drain-side high resistance region, and the source region of the gate insulating film. The source side high resistance region and a gate electrode formed so as to overlap the drain side high resistance region are provided on a region between the drain region and the source region, the drain region and the source side high resistance region. And the drain side high resistance region,
It is characterized in that it is formed by crystallizing an amorphous silicon film having a conductivity type formed on the above crystalline silicon film.

According to the semiconductor device having the above structure, an amorphous silicon film having a predetermined impurity concentration (phosphorus, boron, etc.) is previously formed on the crystalline silicon film, and the amorphous silicon film is formed. The resistance of the source region, the drain region, and the LDD region (source-side high resistance region, drain-side high resistance region) can be easily controlled by crystallizing and activating the film by energy beam irradiation or the like. That is, L, which is a portion of the amorphous silicon film overlapping the gate electrode
DD area (source-side high resistance area, drain-side high resistance area)
When activated by irradiation with an energy beam (for example, a laser or a lamp), a high resistance region is formed by reducing the activation rate by blocking with a gate electrode. In advance
By determining the impurity concentration (phosphorus or boron) and irradiating an energy beam (for example, a laser or a lamp) with a constant energy, the resistance control of the LDD region (source-side high resistance region, drain-side high resistance region) becomes easy. Become. Further, an amorphous silicon film having the above-mentioned conductivity type is formed on the crystalline silicon film by CVD (Chemical Vapor Depositio).
(n: chemical vapor deposition) method, etc., so that the impurity concentration can be easily controlled and the impurities in the source region, the drain region, and the LDD region formed from the amorphous silicon film having the conductivity type can be controlled. The peak of the concentration profile of the element (phosphorus, boron, etc.) can be selectively brought to the upper side of the crystalline silicon film where the current path is formed. In addition, the source region, the drain region and L
DD area (source-side high resistance area, drain-side high resistance area)
Since they can be formed simultaneously, the manufacturing process can be shortened.

The semiconductor device of one embodiment is characterized in that the surface resistance of the source-side high resistance region and the drain-side high resistance region is 10 kΩ / □ or less.

According to the semiconductor device of the above embodiment, the surface resistance of the source-side high resistance region and the drain-side high resistance region is set to 10 kΩ / □ or less, thereby reducing the series resistance between the source and the drain. The on-current increases and the TFT characteristics improve.

Further, in the semiconductor device of one embodiment, the surface resistance of the source region and the drain region is 100-5.
It is characterized in that it is 000 kΩ / □.

According to the semiconductor device of the above embodiment, the surface resistance of the source region and the drain region is 100 to 100.
By setting the resistance to 5000 kΩ / □, the off current can be suppressed low. Further, if the resistance is too high, it affects the series resistance between the source and the drain, but within the above resistance range, the series resistance does not deteriorate the TFT characteristics.

The semiconductor device of one embodiment is characterized in that the source-side high resistance region and the drain-side high resistance region have a width of 0.5 to 2 μm.

According to the semiconductor device of the above embodiment, by setting the width of the source-side high resistance region and the drain-side high resistance region to 0.5 to 2 μm, it is possible to obtain the optimum off current. Good TFT characteristics can be obtained.

In the semiconductor device of one embodiment, the crystalline silicon film has a thickness of 25 nm or more and 80 nm or more.
It is characterized in that it is less than or equal to nm.

According to the semiconductor device of the above embodiment, the crystalline silicon film has a catalytic element that promotes crystallization by setting the thickness of the amorphous silicon film before crystallization to 25 nm or more. Sufficient crystal growth is obtained by the introduction. Furthermore, by setting the thickness of the amorphous silicon film before crystallization to 80 nm or less, the columnar crystal does not have a two-layer structure, and problems such as deterioration of crystallinity and residual catalytic element do not occur.

The semiconductor device of one embodiment is characterized in that the above-mentioned crystalline silicon film is formed by using a catalytic element that promotes the crystallinity.

According to the semiconductor device of the above embodiment, the crystalline silicon film is formed from the amorphous silicon film by using the catalytic element that promotes the crystallinity.
A silicon film with good crystallinity can be formed, high mobility can be obtained, and on-current increases.

Further, in the semiconductor device of one embodiment, the concentration of the catalytic element in the crystalline silicon film is 1 × 10 ¹⁶ a.
It is characterized by being less than toms / cm ³ .

According to the semiconductor device of the above embodiment, the concentration of the catalytic element remaining in the crystalline silicon film formed from the amorphous silicon film using the catalytic element is 1 × 10 ¹⁶ atoms / By setting it to ³ cm ³ or less, a semiconductor device without an increase in leak current or deterioration in characteristics can be obtained.

Further, in the semiconductor device of one embodiment, the catalytic elements used for forming the above-mentioned crystalline silicon film for promoting crystallization are nickel, cobalt, palladium, platinum,
One of the elements of copper, silver, gold, indium, tin, aluminum and antimony or two or more elements are characterized.

According to the semiconductor device of the above embodiment, one or more elements of nickel, cobalt, palladium, platinum, copper, silver, gold, indium, tin, aluminum and antimony are added to the amorphous silicon film. By introducing, the effect of promoting crystallization of the amorphous silicon film can be obtained with a small amount.

The semiconductor device of one embodiment is characterized in that the interlayer insulating film is silicon nitride.

According to the semiconductor device of the above embodiment, by performing annealing after forming the silicon nitride that is the interlayer insulating film, it is possible to hydrogenate the crystalline silicon film in the lower portion and to move the silicon film. The TFT characteristics such as frequency and S value can be improved.

Further, in the method of manufacturing a semiconductor device of the present invention, a step of forming an amorphous silicon film on a substrate having an insulating surface, and the amorphous silicon film is crystallized. A step of introducing a catalytic element that promotes and a heat treatment of the amorphous silicon film into which the catalytic element that promotes crystallization is performed, so that the amorphous silicon film is crystal-grown to form a crystalline silicon film. And a step of forming a predetermined interval on the crystalline silicon film.
Forming an amorphous silicon film having a conductivity type so as to form one island region; forming a gate insulating film covering the crystalline silicon film and the amorphous silicon film having the conductivity type; After forming the gate insulating film, a part of the inside of the amorphous silicon film having the conductivity type is formed on the gate insulating film so as to form the two island regions at the predetermined intervals. Forming a gate electrode so as to overlap, forming a gate electrode, forming an interlayer insulating film on the gate insulating film and on the gate electrode, and forming an interlayer insulating film, and then forming the gate And a step of crystallizing an amorphous silicon film having the above conductivity type by energy beam irradiation using the electrode as a mask.

According to the method for manufacturing a semiconductor device, the impurity concentration (phosphorus, phosphorus, etc.) is previously formed on the crystalline silicon film.
By depositing an amorphous silicon film having a predetermined content of boron (or the like) and crystallization and activation by energy beam irradiation using the gate electrode as a mask, the source region, the drain region, and the LDD region (source-side high It is possible to easily control the resistance of the resistance region and the high resistance region on the drain side. The LDD region (source-side high resistance region, drain-side high resistance region) that overlaps with the gate electrode of the amorphous silicon film is shielded by the gate electrode when activated by irradiation with an energy beam (for example, laser or lamp). A high resistance region is formed by reducing the activation rate with. Since the impurity concentration (phosphorus or boron) is determined in advance and the energy beam (for example, laser or lamp) is irradiated with constant energy, the source region, the drain region and the LDD region (source-side high resistance region, drain-side high resistance region) ) Resistance control is easy. Further, an impurity concentration can be easily controlled by forming an amorphous silicon film having the above conductivity type over a crystalline silicon film by a CVD method or the like, and an amorphous silicon film having the conductivity type. It is possible to selectively bring the peaks of the concentration profile of the impurity element (phosphorus, boron, etc.) in the source region, the drain region and the LDD region formed from the above to the upper side of the crystalline silicon film where the current path is formed. it can. Further, since the source region, the drain region and the LDD region (source-side high resistance region, drain-side high resistance region) can be formed at the same time, the process can be shortened.

In the method for manufacturing a semiconductor device according to one embodiment, the amorphous silicon film having the conductivity type is a mixed gas of silane gas, hydrogen gas, PH ₃ gas or silane gas, hydrogen gas, B ₂ H ₆ gas. CVD using mixed gas of
It is characterized in that it is formed by a method.

According to the method of manufacturing a semiconductor device of the above embodiment, the amorphous silicon film having the conductivity type is formed by the plasma CVD method using silane gas, hydrogen gas, PH ₃ gas or B ₂ H ₆ gas. Therefore, by adjusting the gas amount, the impurity element (phosphorus or boron) can be more accurately doped as compared with the ion implantation method.

Further, in the method for manufacturing a semiconductor device according to one embodiment, in the step of crystallizing the amorphous silicon film to form a crystalline silicon film, the catalyst element for promoting the crystallization is introduced. After crystallizing the amorphous silicon film by heat treatment, the crystallized silicon film is completely crystallized by any one of heat treatment in a furnace, lamp annealing, laser irradiation, or a combination thereof. It is characterized by making it.

According to the method for manufacturing a semiconductor device of the above-described embodiment, the amorphous silicon in which the catalytic element is introduced is formed by any one of heat treatment in a furnace, lamp annealing, laser irradiation, or a combination thereof. It is possible to fully crystallize the layer. It is particularly desirable that the amorphous silicon film is not completely crystallized by heat treatment or lamp irradiation, but is then completely crystallized by laser. That is, it is particularly desirable to perform crystallization by a combination of heat treatment and a laser, or a combination of lamp annealing and a laser, which dramatically improves transistor characteristics.

Further, in the method for manufacturing a semiconductor device of one embodiment, in the step of crystallizing the amorphous silicon film to form a crystalline silicon film, the heat treatment after the introduction of the catalytic element is performed at 540 ° C. It is characterized in that it is performed within a temperature range of 600 ° C.

According to the method for manufacturing a semiconductor device of the above embodiment, when the heat treatment is performed within the temperature range of 540 ° C. to 600 ° C. after the introduction of the catalyst element, the amorphous silicon film is completely crystallized. There is no end. Therefore, after the introduction of the catalytic element for promoting crystallization, the crystallization is incomplete when the crystallization is performed by the heat treatment, and the complete crystallization is performed by the laser annealing, whereby the transistor characteristics can be improved.

The method of manufacturing a semiconductor device according to one embodiment is characterized in that at least nickel is used as the catalyst element.

According to the method of manufacturing a semiconductor device of the above embodiment, the catalyst element usually promotes crystal growth of the amorphous silicon film by silicidation. For example,
The crystal structure of NiSi ₂ which is a silicide compound of nickel as the catalyst element is most similar to the crystal structure of single crystal silicon among the silicide compounds of various catalyst elements, and its lattice constant is also the lattice constant of crystal silicon. Very close. Therefore, the NiSi ₂ acts as the best template for crystallization of the amorphous silicon film, and greatly promotes the crystallization of the amorphous silicon film.

In the method for manufacturing a semiconductor device of one embodiment, the amorphous silicon film having the conductivity type is crystallized by one of lamp annealing and laser irradiation, or a combination thereof. The catalyst element contained in the crystalline silicon film is gettered.

According to the method of manufacturing a semiconductor device of the above embodiment, the portion to be the LDD region is shielded by the gate electrode,
It is possible to lower the activation rate and increase the resistance.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the illustrated embodiments.

1 and 2 are process drawings showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device of the present invention is applied to a step of forming an N-type TFT on a glass substrate. The TFT in this embodiment can be used not only as an active matrix type driver circuit and a pixel portion but also as an element constituting a thin film integrated circuit. In addition, in this embodiment, as a representative of them, a pixel TFT of an active matrix substrate for a liquid crystal display device in which hundreds of thousands to millions of N-type TFTs need to be particularly uniformly formed on the substrate is described. To do.

1 (a) to 1 (e) and 2 (a) to 2 (d) show the manufacturing process of the N-type thin film transistor according to the present invention in the order of processes. Although it is actually composed of hundreds of thousands of TFTs or more, one TFT is used in this embodiment.
Will be briefly described.

First, as shown in FIG. 1A, a base film 102 of silicon oxide having a thickness of 200 nm is formed on an insulating substrate 101 such as a glass substrate by a plasma CVD method. Next, a thickness of 25 to 8 is formed by a plasma CVD method.
An intrinsic amorphous silicon film of 0 nm (for example, 40 nm) is formed. After that, an unnecessary portion of the amorphous silicon film is removed to perform element isolation, and a crystalline silicon film 103 which is an element formation region to be a source region, a drain region, and a channel region of a thin film transistor later is formed. The island area. When the present invention is applied to an active matrix type liquid crystal display device, island regions are arranged in a matrix.

Next, the surface concentration of 1 × 10 ^{13 to} 1 × 10 ¹⁵ a is applied to the crystalline silicon film 103 by the sputtering method.
toms / cm ² (for example, 7 × 10 ¹³ atoms / cm 2
Ni is added so that it becomes ² ). After that, heat treatment is performed at 540 ° C. to 620 ° C. for several hours in an inert atmosphere. In this embodiment, 5 in a nitrogen atmosphere.
Heat treatment was performed at 80 ° C. for 4 hours. However, the method of adding Ni is not limited to the sputtering method, and a method of forming a coating film using a coating liquid containing a Ni compound may be used.

Subsequently, crystallization is performed by laser irradiation. The laser light has a wavelength of 248 nm and a pulse width of 20.
A KrF excimer laser of nsec is used, but other lasers may be used. Laser irradiation conditions are
Energy density is 200 to 400 mJ / cm ² (for example, 2
50 mJ / cm ² ) and 2 to 10 shots per place
(For example, 2 shots). It is useful to heat the substrate to about 200 to 450 ° C. during the irradiation with the laser light. After that, a resist film 104 is provided and patterned to form an n-type amorphous silicon film.

Next, after resist patterning, FIG.
As shown in, the n-type amorphous silicon films 105 and 105 are formed by the plasma CVD method. The conditions at this time are: substrate temperature 170 ° C., power 0.5 W / cm ² , pressure 0.2 torr, SiH ₄ gas flow rate 100 sccm, H
₂ gas flow rate 300 sccm, PH ₃ gas flow rate 20 s
Perform in ccm. The n-type amorphous silicon film 105, 10
The film thickness of 5 was set to 30 nm. Then, after forming the n-type amorphous silicon films 105, 105, the resist film 104 is removed as shown in FIG.

After that, as shown in FIG. 1D, a thickness of 50 nm to 250 nm (for example, 1
The gate insulating film 106 is formed by forming a silicon oxide film having a thickness of 00 nm.

Subsequently, as shown in FIG. 1E, an aluminum film having a thickness of 400 to 800 nm (for example, 600 nm) is formed by a sputtering method, and then the aluminum film is patterned to form an n-type amorphous silicon. Membrane 10
Gate electrode 10 so that it overlaps with 5,105
Form 7. The width of this overlap is 0.5-2μ
m. In this embodiment, it is set to 1.5 μm. Note that the gate electrode 107 is not limited to aluminum, and may be a metal film of any one of tungsten, tantalum, molybdenum, and silver, or a stacked film of a combination thereof.

Next, as shown in FIG. 2A, laser light as an energy beam is applied to the n-type amorphous silicon film 10 using the gate electrode 107 as a mask.
Crystallize and activate 5,105. At this time, the laser light has a wavelength of 248 nm and a pulse width of 20 nse.
Although the KrF excimer laser of c was used, other lasers may be used. The irradiation condition of the laser light is such that the energy density is 200 to 400 mJ / cm ² , for example, 250.
mJ / cm ² and ² to 10 shots (for example, 2 shots) per place. In addition to the laser, an ultraviolet lamp may be used, or a combination of a laser and a lamp may be used.

As a result, as shown in FIG. 2B, the portion irradiated with the laser beam has a high activation rate and becomes a low resistance region (source region 109a, drain region 109b), and the gate electrode 107 The portions where the light is shielded are LDD regions (source-side high-resistance region 108a, drain-side high-resistance region 108b) which are high-resistance regions. Further, the catalytic element in the crystalline silicon film 103 is gettered to the n-type silicon region (source region 109a, drain region 109b).

Next, as shown in FIG. 2 (c), plasma C
An interlayer insulating film 110 is formed by forming a 600-nm-thick silicon nitride film by a VD method. continue,
The crystalline silicon film 103 is hydrogenated by performing heat treatment for 1 hour in a nitrogen atmosphere at 400 ° C. and 20 atm or less.

Next, as shown in FIG. 2D, the silicon nitride film 11 on the source region 109a and the drain region 109b is formed.
A contact hole is formed in each of the holes 0, and a metal wiring 111 of the thin film transistor is formed by a multilayer film of a metal material (for example, titanium nitride and aluminum). Furthermore, when using this thin film transistor as a pixel switching element of a liquid crystal display device or the like, a pixel electrode (not shown) made of ITO (Indium-Tin-Oxide: tin-added indium oxide) is formed instead of the metal electrode 111, Complete the thin film transistor.

In the above-mentioned embodiment, nickel is added as a catalyst element for promoting crystallization, but one of nickel, cobalt, palladium, platinum, copper, silver, gold, indium, tin, aluminum and antimony or You may use combining 2 or more types of elements.

[0061]

As is apparent from the above, according to the semiconductor device and the method of manufacturing the same of the present invention, the active region is formed in the crystalline silicon film formed on the substrate having the insulating surface, and the source region is formed. By forming the drain region by depo-doping and forming the LDD region by the resist work, the gate forming method and the crystallization method, the resistance control of the LDD region can be facilitated and the reliability such as off current can be improved. Further, the source region, the drain region and the LDD region can be formed at the same time, the manufacturing process can be simplified, and the productivity can be improved.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view subsequent to FIG.

[Explanation of symbols]

101 ... Insulating substrate, 102 ... a base film, 103 ... Crystalline silicon film, 104 ... resist, 105 ... n-type amorphous silicon film, 106 ... Gate insulating film, 107 ... Gate electrode, 108a ... Source side high resistance region, 108b ... high resistance region on the drain side, 109a ... Source area, 109b ... the drain region, 110 ... Interlayer insulating film, 111 ... Metal electrode.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 616T 627G 616A 616V F term (reference) 2H092 HA02 HA04 JA24 JA34 JA37 JA41 KA02 KA04 KA05 MA02 MA05 MA06 MA07 MA08 MA28 MA29 MA30 NA25 NA27 PA01 5F045 AA08 AB04 AC01 AC19 5F052 AA02 AA11 AA17 AA24 BB07 CA07 DA02 DB03 EA16 FA06 FA19 HA01 JA01 5F110 AA16 BB02 BB35 HG35 EE EE GG45 GG35 EE45 EE14 GG14 EE14 GG14 EE14 FF14 EE11 HL01 HL03 HL11 HM02 HM04 HM15 NN02 NN04 NN24 NN35 NN72 PP01 PP02 PP03 PP04 PP05 PP10 PP13 PP34 QQ11 QQ23 QQ28

Claims (15)

[Claims] 1. A crystalline silicon film formed on a substrate having an insulating surface, a source region and a drain region formed on the crystalline silicon film at a predetermined interval, and the crystal described above. Source-side high-resistance region formed between the source region and the drain region on the crystalline silicon film adjacent to the source region; the source region on the crystalline silicon film; A drain-side high-resistance region formed between the drain region and the drain-side high-resistance region, the crystalline silicon film, the source region, the drain region, the source-side high-resistance region, and the drain-side high-resistance region. On the gate insulating film formed so as to cover the resistance region, and on the region of the gate insulating film between the source region and the drain region, the saw Side high resistance region and a gate electrode formed so as to overlap the drain side high resistance region, the source region, the drain region and the source side high resistance region and the drain side high resistance region, the crystalline A semiconductor device, which is formed by crystallizing an amorphous silicon film having a conductivity type formed over the existing silicon film. 2. The semiconductor device according to claim 1, wherein the surface resistance of the source-side high resistance region and the drain-side high resistance region is 10 kΩ / □ or less. 3. The semiconductor device according to claim 1, wherein the surface resistance of the source region and the drain region is 10 or less.
A semiconductor device having a resistance of 0 to 5000 kΩ / □. 4. The semiconductor device according to claim 1, wherein the source-side high resistance region and the drain-side high resistance region have a width of 0.5 to 2 μm. Semiconductor device. 5. The semiconductor device according to claim 1, wherein the crystalline silicon film has a thickness of 25 nm or more and 80 nm or less. 6. The semiconductor device according to claim 1, wherein the crystalline silicon film is formed by using a catalytic element that promotes crystallinity. apparatus. 7. The semiconductor device according to claim 6, The catalytic element concentration of the crystalline silicon film is 1 × 1.
0¹⁶atoms / cm ³Half characterized by
Conductor device. 8. The semiconductor device according to claim 6, wherein the catalyst element used for forming the crystalline silicon film that promotes crystallization is nickel, cobalt, palladium,
A semiconductor device comprising one element or two or more elements of platinum, copper, silver, gold, indium, tin, aluminum and antimony. 9. The semiconductor device according to claim 1, wherein the interlayer insulating film is silicon nitride. 10. A step of forming an amorphous silicon film on a substrate having an insulating surface, and a step of introducing a catalytic element for promoting crystallization of the amorphous silicon film into the amorphous silicon film, Heat-treating the amorphous silicon film into which the catalytic element that promotes crystallization is introduced to crystallize the amorphous silicon film to form a crystalline silicon film; A step of forming an amorphous silicon film having a conductivity type on the film so as to form two island regions at a predetermined interval, and the crystalline silicon film and the amorphous silicon film having the conductivity type. A step of forming a gate insulating film for covering, and a step of forming the gate insulating film, and then forming a non-conductivity type non-conductive film formed on the gate insulating film so as to form two island regions at a predetermined interval. Crystalline silicon Forming a gate electrode so that a part of the inside of the film overlaps; forming the gate electrode, and then forming an interlayer insulating film on the gate insulating film and on the gate electrode; and the interlayer insulating film. And crystallization of the conductive type amorphous silicon film by energy beam irradiation using the gate electrode as a mask. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the amorphous silicon film having a conductivity type is silane gas,
A method of manufacturing a semiconductor device, wherein a film is formed by a plasma CVD method using a mixed gas of hydrogen gas and PH ₃ gas or a mixed gas of silane gas, hydrogen gas and B ₂ H ₆ gas. 12. The method of manufacturing a semiconductor device according to claim 10, wherein in the step of crystallizing the amorphous silicon film to form a crystalline silicon film, a catalyst element that promotes the crystallization is used. After the introduced amorphous silicon film is crystallized by heat treatment, the crystallized silicon film is subjected to any one of heat treatment in a furnace, lamp annealing, laser irradiation, or a combination thereof. A method for manufacturing a semiconductor device, which is characterized by completely crystallizing by. 13. The method of manufacturing a semiconductor device according to claim 10, wherein in the step of crystallizing the amorphous silicon film to form a crystalline silicon film, the catalyst element of A method of manufacturing a semiconductor device, wherein the heat treatment after the introduction is performed within a temperature range of 540 ° C to 600 ° C. 14. The method of manufacturing a semiconductor device according to claim 10, wherein at least nickel is used as the catalyst element. 15. The method for manufacturing a semiconductor device according to claim 10, wherein the amorphous silicon film having the conductivity type is crystallized by one of lamp annealing and laser irradiation, or a combination thereof. At the same time, a method of manufacturing a semiconductor device is characterized in that the catalytic element contained in the crystalline silicon film is gettered.