WO2010067639A1 - アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 - Google Patents
アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 Download PDFInfo
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
Definitions
- the present invention relates to an active matrix substrate in which a plurality of pixel electrodes are provided in one pixel region, and a liquid crystal display device (pixel division method) using the same.
- a plurality of subpixels provided in one pixel are controlled to have different luminances, and the area level of these subpixels.
- a liquid crystal display device pixel division method, for example, see Patent Document 1 that displays a halftone by a tone.
- three pixel electrodes 121a to 121c are arranged along the data signal line 115 in one pixel region, and the source electrode 116s of the transistor 116 is a contact electrode.
- 117a, the contact electrode 117a and the control electrode 118 are connected via an extraction wiring 119
- the control electrode 118 and the contact electrode 117b are connected via an extraction wiring 126
- the contact electrode 117a and the pixel electrode 121a are in contact with each other.
- the contact electrode 117b and the pixel electrode 121c are connected via the contact hole 120b via the hole 120a, and the electrically floating pixel electrode 121b overlaps the control electrode 118 via the insulating layer.
- the pixel electrode 121b is Are capacitively coupled to each pixel electrode 121a ⁇ 121c (capacitively coupled pixel split method).
- a storage capacitor is formed in an overlapping portion between the control electrode 118 and the capacitor wiring 113.
- each of the sub-pixels corresponding to the pixel electrodes 121a and 121c can be a bright sub-pixel, and the sub-pixel corresponding to the pixel electrode 121b can be a dark sub-pixel.
- Halftone can be displayed by area gradation of dark sub-pixel (1).
- Japanese Patent Publication Japanese Patent Laid-Open No. 2006-39290 (Publication Date: February 9, 2006)”
- the signal potential is written from the data signal line to the pixel electrode 121b by cutting the lead-out wiring 119.
- the pixel electrode 121b is not capacitively coupled to the pixel electrode 121a.
- the sub-pixel (dark sub-pixel) corresponding to the pixel electrode 121b tends to be defective, and the yield may be reduced.
- the present invention proposes a structure capable of improving the yield of an active matrix substrate of a capacitively coupled pixel division method.
- the active matrix substrate includes a scanning signal line, a data signal line, and a transistor connected to the scanning signal line and the data signal line, and an active element in which first and second pixel electrodes are provided in one pixel region.
- the first pixel electrode is a matrix substrate, wherein the first pixel electrode is connected to the data signal line through the transistor, and is electrically connected to one of the first and second pixel electrodes.
- a second capacitor electrode a capacitor is formed between the other pixel electrode of the first and second pixel electrodes and the first capacitor electrode, and the other pixel electrode and the second capacitor electrode, A capacitance is formed between the two.
- the above configuration is such that the first and second pixel electrodes provided in one pixel region are connected via two capacitors (coupling capacitors) in a capacitively coupled pixel division type active matrix substrate. Thereby, even if a defect occurs in one capacitor in the manufacturing process or the like, the capacitive coupling between the first and second pixel electrodes can be maintained by the other capacitor.
- the first capacitor electrode and the second capacitor electrode are electrically connected to the first pixel electrode, and a capacitor is formed between the first capacitor electrode and the second pixel electrode.
- the first capacitor electrode is connected to the first pixel electrode and the short-circuited portion.
- the capacitance coupling between the second and second pixel electrodes can be maintained by the capacitance (coupling capacitance) formed between the second capacitance electrode and the second pixel electrode. Thereby, the production yield of the present active matrix substrate and the liquid crystal panel including the same can be increased.
- the active matrix substrate may have a configuration in which one conduction electrode of the transistor, the first capacitor electrode, and the second capacitor electrode are formed in the same layer. Thereby, the layer structure and manufacturing process of the active matrix substrate can be simplified.
- At least part of the first capacitor electrode overlaps the other pixel electrode through an interlayer insulating film covering the channel of the transistor, and at least part of the second capacitor electrode is formed between the interlayer electrodes.
- a structure in which the other pixel electrode overlaps with the insulating film interposed therebetween can also be employed.
- the outer periphery of the first and second pixel electrodes is composed of a plurality of sides, and one side of the first pixel electrode and one side of the second pixel electrode are adjacent to each other.
- Each of the second capacitor electrodes may be arranged so as to overlap the gap between the adjacent two sides, the first pixel electrode, and the second pixel electrode.
- one conductive electrode of the transistor is connected to the first pixel electrode through a contact hole, and the conductive electrode is connected to the first capacitor electrode through a lead wire drawn from the first pixel electrode.
- the first pixel electrode and the second capacitor electrode may be connected via a contact hole.
- one conductive electrode of the transistor and the first pixel electrode are connected through a contact hole, and the first pixel electrode and the first capacitor electrode are connected through a contact hole.
- the first pixel electrode and the second capacitor electrode may be connected via a contact hole.
- one conduction electrode of the transistor is connected to the first pixel electrode through a contact hole, and the second pixel electrode and the first capacitor electrode are connected through a contact hole.
- the second pixel electrode and the second capacitor electrode may be connected via a contact hole.
- the present active matrix substrate may have a configuration in which the first and second pixel electrodes are arranged in the column direction with the extending direction of the scanning signal lines as the row direction.
- the first pixel electrode in one pixel region and the second pixel electrode in the other pixel region are adjacent in the row direction. It can also be.
- the first pixel electrode may surround the second pixel electrode.
- the second pixel electrode may surround the first pixel electrode.
- the first pixel electrode or a conductor and a capacitor electrically connected thereto are formed, and the second pixel electrode or a conductor and a capacitor electrically connected thereto are formed.
- a configuration in which a storage capacitor wiring is further provided may be employed.
- the storage capacitor wiring may be configured to extend in the same direction as the scanning signal line so as to cross the center of the pixel region.
- the first capacitor electrode and the second capacitor electrode may form a capacity with the storage capacitor wiring.
- the storage capacitor wiring may be configured to extend in the same direction as the scanning signal line so as to cross the center of the pixel region.
- each of the first capacitor electrode and the second capacitor electrode may form a capacity with the storage capacitor wiring.
- the interlayer insulating film is composed of an inorganic insulating film and an organic insulating film thicker than the inorganic insulating film, and at least a part of the portion overlapping with the first capacitor electrode overlaps with the second capacitor electrode. For at least part of the portion, the organic insulating film may be removed.
- the interlayer insulating film has a thin film portion formed by removing the organic insulating film, including a region overlapping with a part of the first capacitor electrode and a part of the second capacitor electrode,
- the first and second capacitor electrodes are arranged side by side in the extending direction of the scanning signal line, the first capacitor electrode straddles one side of the thin film portion, and the second capacitor electrode faces the one side. It can also be set as the structure which straddles the edge to do.
- the first capacitor electrode since the overlapping area of the second pixel electrode and the overlapping area of the second capacitor electrode and the second pixel electrode compensate each other, an effect that the total amount of the two capacitors (coupling capacitors) hardly changes can be obtained.
- the thin film portion may be configured to overlap either one of the first and second pixel electrodes.
- the gap between the first and second pixel electrodes may function as an alignment regulating structure.
- the first pixel electrode surrounds the second pixel electrode
- the outer periphery of the second pixel electrode includes two sides parallel to each other
- the outer periphery of the first pixel electrode Includes a side facing one of the two sides via a first gap, and a side facing the other via a second gap
- the first capacitor electrode is connected to the first pixel electrode and the first side.
- the first capacitor electrode and the second capacitor electrode may be configured to be line-symmetric with respect to a line parallel to the first gap and the second gap and passing through the center of both gaps. .
- the active matrix substrate includes a scanning signal line, a data signal line, and a transistor connected to the scanning signal line and the data signal line, and the first, second, and third pixel electrodes are provided in one pixel region.
- the first pixel electrode is connected to the data signal line through the transistor, the third pixel electrode is electrically connected to the first pixel electrode, and the first pixel electrode is connected to the first pixel electrode.
- a first capacitor electrode electrically connected to the one pixel electrode; and a second capacitor electrode electrically connected to the third pixel electrode; and between the first capacitor electrode and the second pixel electrode. In this case, a capacitor is formed, and a capacitor is formed between the second capacitor electrode and the second pixel electrode.
- the active matrix substrate includes a scanning signal line, a data signal line, and a transistor connected to the scanning signal line and the data signal line, and the first, second, and third pixel electrodes are provided in one pixel region.
- the first pixel electrode is connected to the data signal line through the transistor, the third pixel electrode is electrically connected to the first pixel electrode, and the first pixel electrode is connected to the first pixel electrode.
- a first capacitor electrode electrically connected to the two pixel electrodes; a capacitor formed between the first capacitor electrode and the first pixel electrode; the second capacitor electrode and the third pixel; A capacitor is formed between the electrodes.
- the active matrix substrate includes a scanning signal line, a data signal line, and a transistor connected to the scanning signal line and the data signal line, and the first, second, and third pixel electrodes are provided in one pixel region.
- the second pixel electrode includes first and second capacitor electrodes connected to the data signal line through the transistor and electrically connected to the second pixel electrode.
- a capacitor is formed between the first capacitor electrode and the first pixel electrode, and a capacitor is formed between the second capacitor electrode and the third pixel electrode.
- the active matrix substrate includes a scanning signal line, a data signal line, and a transistor connected to the scanning signal line and the data signal line, and the first, second, and third pixel electrodes are provided in one pixel region.
- the second pixel electrode is connected to the data signal line through the transistor, and is electrically connected to the first pixel electrode, and the third capacitor electrode,
- a second capacitor electrode electrically connected to the pixel electrode, a capacitor is formed between the first capacitor electrode and the second pixel electrode, and the second capacitor electrode and the second pixel electrode Capacitance is formed between them.
- the active matrix substrate further includes first and second storage capacitor lines in the pixel region, the first capacitor electrode forms a capacitor with the first storage capacitor line, and the second capacitor electrode is the second storage electrode.
- a structure in which a capacitor wiring and a capacitor are formed may be employed.
- the manufacturing method of the active matrix substrate includes a scanning signal line, a data signal line, and a transistor connected to the scanning signal line and the data signal line, and the first and second pixel electrodes are provided in one pixel region.
- An active matrix substrate manufacturing method in which the first pixel electrode is connected to the data signal line through the transistor, and is electrically connected to one of the first and second pixel electrodes.
- a first capacitor electrode which is connected and forms a capacitor with the other pixel electrode; and a second capacitor electrode which is electrically connected to the one pixel electrode and forms a capacitor with the other pixel electrode.
- the manufacturing method of the active matrix substrate includes a scanning signal line, a data signal line, and a transistor connected to the scanning signal line and the data signal line, and the first and second pixel electrodes are provided in one pixel region.
- An active matrix substrate manufacturing method in which the first pixel electrode is connected to the data signal line through the transistor, and is electrically connected to one of the first and second pixel electrodes.
- a first capacitor electrode that is connected to the other pixel electrode and the storage capacitor wiring, and is electrically connected to the one pixel electrode, and the other pixel electrode and the storage capacitor wiring are connected to the capacitor.
- Forming a second capacitor electrode forming a short circuit between the first capacitor electrode and the other pixel electrode, and shorting between the second capacitor electrode and the other pixel electrode.
- Detecting at least one of a short circuit between the first capacitor electrode and the storage capacitor line, a short circuit between the second capacitor electrode and the storage capacitor line, and the first capacitor electrode and the other pixel electrode Detecting at least one of a short circuit between the first capacitor electrode and the storage capacitor line, a short circuit between the second capacitor electrode and the storage capacitor line, and the first capacitor electrode and the other pixel electrode.
- the first capacitor electrode is cut between the connection point with the one pixel electrode and the short circuit point, and the first capacitor electrode is disconnected.
- the second capacitor electrode is connected to the one pixel electrode. And a step of cutting between the short-circuited portions.
- the manufacturing method of the present liquid crystal panel includes a scanning signal line, a data signal line, and a transistor connected to the scanning signal line and the data signal line, and a first pixel electrode and a second pixel electrode are provided in one pixel, A method of manufacturing a liquid crystal panel in which the first pixel electrode is connected to the data signal line through the transistor, and is electrically connected to one of the first and second pixel electrodes. And forming a first capacitor electrode that forms a capacitor with the other pixel electrode, and a second capacitor electrode that is electrically connected to the one pixel electrode and forms a capacitor with the other pixel electrode.
- the first capacitor electrode is cut between a connection point with the one pixel electrode and a short circuit point, and the second capacitor electrode and the other pixel electrode are disconnected.
- a step of cutting the second capacitor electrode between the connection portion with the one pixel electrode and the short-circuit portion when a short circuit is detected.
- the manufacturing method of the present liquid crystal panel includes a scanning signal line, a data signal line, and a transistor connected to the scanning signal line and the data signal line, and a first pixel electrode and a second pixel electrode are provided in one pixel, A method of manufacturing a liquid crystal panel in which the first pixel electrode is connected to the data signal line through the transistor, and is electrically connected to one of the first and second pixel electrodes.
- a first capacitor electrode that forms a capacity with the other pixel electrode and the storage capacitor line, and a capacitor that is electrically connected to the one pixel electrode and that forms a capacitor with the other pixel electrode and the storage capacitor line.
- the first capacitor electrode is cut between the connection point with the one pixel electrode and the short circuit point, and the second capacitor electrode and the other pixel electrode And a step of cutting the second capacitor electrode between the connection point with the one pixel electrode and the short-circuit point when a short circuit of the second capacitor electrode and a short circuit of the storage capacitor line are detected. It is characterized by including.
- This liquid crystal panel includes the above active matrix substrate.
- the present liquid crystal display unit includes the liquid crystal panel and a driver.
- the present liquid crystal display device includes the liquid crystal display unit and a light source device.
- the television receiver includes the liquid crystal display device and a tuner unit that receives a television broadcast.
- the present invention connects the first and second pixel electrodes provided in one pixel region via two capacitors (coupling capacitors) in parallel in a capacitively coupled pixel-divided active matrix substrate. Is. In this way, even if a defect occurs in one capacitor during the manufacturing process, etc., the capacitive coupling between the first and second pixel electrodes can be maintained by the other capacitor, thereby increasing the manufacturing yield of the present active matrix substrate. Can do.
- FIG. 1 is a circuit diagram illustrating a configuration of a liquid crystal panel according to a first embodiment.
- FIG. 2 is a plan view showing a specific example of the liquid crystal panel of FIG. 1.
- FIG. 3 is a cross-sectional view taken along the line AB in FIG. 2.
- FIG. 3 is a cross-sectional view taken along arrow AB in the modified configuration of FIG. 2.
- 3 is a timing chart illustrating a driving method of a liquid crystal display device including the liquid crystal panel of FIG. 1. It is a schematic diagram which shows the display state for every flame
- FIG. 6 is a circuit diagram illustrating another configuration of the liquid crystal panel according to the first embodiment. It is a top view which shows the specific example of the liquid crystal panel shown in FIG. FIG. 6 is a circuit diagram illustrating another configuration of the liquid crystal panel according to the first embodiment.
- FIG. 15 is a schematic diagram illustrating a display state for each frame when the driving method of FIG. 5 is used in a liquid crystal display device including the liquid crystal panel of FIG. 14. It is a top view which shows the specific example of the liquid crystal panel shown in FIG. FIG.
- FIG. 6 is a circuit diagram illustrating another configuration of the liquid crystal panel according to the first embodiment.
- FIG. 18 is a plan view illustrating a specific example of the liquid crystal panel illustrated in FIG. 17.
- FIG. 6 is a circuit diagram illustrating a configuration of a liquid crystal panel according to a second embodiment.
- FIG. 20 is a plan view illustrating a specific example of the liquid crystal panel illustrated in FIG. 19.
- FIG. 20 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 19.
- FIG. 20 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 19.
- FIG. 20 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 19.
- FIG. 20 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 19.
- FIG. 20 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 19.
- FIG. 19 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 19.
- FIG. 20 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 19.
- FIG. 10 is a circuit diagram showing another configuration of the liquid crystal panel according to the second embodiment.
- FIG. 27 is a plan view illustrating a specific example of the liquid crystal panel illustrated in FIG. 26.
- FIG. 10 is a circuit diagram showing another configuration of the liquid crystal panel according to the second embodiment.
- FIG. 29 is a plan view illustrating a specific example of the liquid crystal panel illustrated in FIG. 28.
- FIG. 29 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 28.
- It is a circuit diagram which shows the structure of the liquid crystal panel concerning this Embodiment 3.
- FIG. 32 is a plan view showing a specific example of the liquid crystal panel shown in FIG. 31.
- FIG. 32 is a plan view showing a specific example of the liquid crystal panel shown in FIG. 31.
- FIG. 32 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 31.
- FIG. 32 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 31.
- FIG. 32 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 31.
- FIG. 10 is a circuit diagram illustrating another configuration of the liquid crystal panel according to the fourth embodiment.
- FIG. 37 is a plan view showing a specific example of the liquid crystal panel shown in FIG. 36.
- FIG. 37 is a plan view showing another specific example of the liquid crystal panel shown in FIG. 36.
- FIG. 37 is a plan view showing a modification of the liquid crystal panel shown in FIG. 36.
- FIG. 26 is a block diagram illustrating functions of the present television receiver. It is a disassembled perspective view which shows the structure of this television receiver. It is a top view which shows the other specific example of the liquid crystal panel shown in FIG.
- FIG. 29 is a plan view illustrating another specific example of the liquid crystal panel illustrated in FIG. 28. It is a top view which shows the structure of the conventional liquid crystal panel.
- the extending direction of the scanning signal lines is hereinafter referred to as the row direction.
- the scanning signal line may extend in the horizontal direction or in the vertical direction. Needless to say, it is good. Further, the alignment regulating structure formed in the liquid crystal panel is omitted as appropriate.
- FIG. 1 is an equivalent circuit diagram showing a part of the liquid crystal panel according to the first embodiment.
- the present liquid crystal panel includes a data signal line (15x ⁇ 15y) extending in the column direction (vertical direction in the drawing) and a scanning signal line (16x ⁇ 16y) extending in the row direction (horizontal direction in the drawing). ), Pixels (101 to 104) arranged in the row and column directions, storage capacitor lines (18p, 18q), and common electrode (counter electrode) com, and the structure of each pixel is the same.
- the pixel column including the pixels 101 and 102 and the pixel column including the pixels 103 and 104 are adjacent to each other, and the pixel row including the pixels 101 and 103 and the pixel row including the pixels 102 and 104 are adjacent to each other. is doing.
- one data signal line and one scanning signal line are provided corresponding to one pixel.
- Two pixel electrodes are arranged in the column direction in one pixel, and two pixel electrodes 17a and 17b provided in the pixel 101 and two pixel electrodes 17c and 17d provided in the pixel 102 are arranged in a line.
- two pixel electrodes 17A and 17B provided on the pixel 103 and two pixel electrodes 17C and 17D provided on the pixel 104 are arranged in a line, and the pixel electrodes 17a and 17A, the pixel electrodes 17b and 17B, Pixel electrodes 17c and 17C and pixel electrodes 17d and 17D are adjacent to each other in the row direction.
- the storage capacitor line 18p crosses the pixels 101 and 103, and the storage capacitor line 18q crosses the pixels 102 and 104, respectively.
- the pixel electrodes 17a and 17b are connected via the coupling capacitors Cab1 and Cab2 arranged in parallel, and the pixel electrode 17a is connected to the data signal line 15x via the transistor 12a connected to the scanning signal line 16x.
- the storage capacitor Cha (Cha1 and Cha2) is formed between the pixel electrode 17a and the storage capacitor line 18p, and the storage capacitor Chb is formed between the pixel electrode 17b and the storage capacitor line 18p.
- a liquid crystal capacitor Cla is formed between the common electrodes com, and a liquid crystal capacitor Clb is formed between the pixel electrode 17b and the common electrode com.
- the pixel electrodes 17c and 17d are connected via the coupling capacitors Ccd1 and Ccd2 arranged in parallel, and the pixel electrode 17c is connected to the scanning signal line 16y.
- a storage capacitor Chc Chc1 ⁇ Chc2
- a capacitor Chd is formed, a liquid crystal capacitor Clc is formed between the pixel electrode 17c and the common electrode com, and a liquid crystal capacitor Cld is formed between the pixel electrode 17d and the common electrode com.
- the pixel electrodes 17A and 17B are connected via the coupling capacitors CAB1 and CAB2 arranged in parallel, and the pixel electrode 17A is connected to the scanning signal line 16x.
- a storage capacitor ChA ChA1 and ChA2 is formed between the pixel electrode 17A and the storage capacitor line 18p, and stored between the pixel electrode 17B and the storage capacitor line 18p.
- a capacitor ChB is formed, a liquid crystal capacitor ClA is formed between the pixel electrode 17A and the common electrode com, and a liquid crystal capacitor ClB is formed between the pixel electrode 17B and the common electrode com.
- the scanning signal lines 16x and 16y are sequentially selected.
- Vb Va ⁇ [(C1 + C2) / (Cl + Ch + C1 + C2)]]. That is,
- means a potential difference between Va and com potential Vcom), so that the subpixel including the pixel electrode 17a is a bright subpixel at the time of halftone display.
- the sub-pixel including the pixel electrode 17b is a dark sub-pixel, and display can be performed according to the area gradation of these bright / dark sub-pixels. Thereby, the viewing angle characteristic of the liquid crystal display device can be enhanced.
- FIG. 2 shows a specific example of the pixel 101 in FIG.
- a transistor 12a is arranged near the intersection of the data signal line 15x and the scanning signal line 16x, and a rectangular pixel electrode 17a is formed in a pixel region defined by both signal lines (15x and 16x).
- rectangular pixel electrodes 17b are arranged in the column direction, and one of the four sides forming the outer periphery of the first pixel electrode is adjacent to one of the four sides forming the outer periphery of the second pixel electrode.
- the storage capacitor line 18p extending in the row direction is arranged so as to overlap the pixel electrode 17b.
- the capacitor electrodes 37a and 38a are arranged so as to overlap the storage capacitor line 18p and the pixel electrode 17b.
- the capacitor electrode 37a extends in the same direction as the storage capacitor wiring 18p and overlaps the storage capacitor wiring 18p and the pixel electrode 17b.
- the capacitor electrode 38a is arranged side by side in the row direction (the extending direction) with the capacitor electrode 37a, extends in the same direction as the extending direction of the storage capacitor line 18p, and overlaps the storage capacitor line 18p and the pixel electrode 17b.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a.
- the drain lead wiring 27a is connected to the capacitor electrode 37a formed in the same layer and is connected to the pixel electrode 17a through the contact hole 11a.
- the capacitor electrode 37a is connected to the interlayer insulating film.
- the coupling capacitor Cab1 (see FIG. 1) between the pixel electrodes 17a and 17b is formed at the overlapping portion of the pixel electrode 17b.
- the capacitor electrode 38a is connected to the pixel electrode 17a through the contact hole 68a and overlaps with the pixel electrode 17b through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab2 (see FIG. 1) is formed.
- the capacitor electrode 37a overlaps the storage capacitor wiring 18p through the gate insulating film, and the storage capacitor Cha1 (see FIG. 1) is formed in the overlapping portion between the two, and the capacitor electrode 38a passes through the gate insulating film.
- the storage capacitor Cha2 (see FIG. 1) is formed at the overlapping portion of the wiring 18p.
- the pixel electrode 17b and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a storage capacitor Chb (see FIG. 1) is formed in the overlapping portion between them.
- FIG. 3 is a cross-sectional view taken along the line AB of FIG.
- the present liquid crystal panel includes an active matrix substrate 3, a color filter substrate 30 facing the active matrix substrate 3, and a liquid crystal layer 40 disposed between both substrates (3, 30).
- the scanning signal line 16x and the storage capacitor line 18p are formed on the glass substrate 31, and the inorganic gate insulating film 22 is formed so as to cover them.
- a semiconductor layer 24 i layer and n + layer
- a source electrode 8a and a drain electrode 9a in contact with the n + layer, a drain lead wiring 27a, and capacitance electrodes 37a and 38a are formed on the inorganic gate insulating film 22.
- An inorganic interlayer insulating film 25 is formed so as to cover these.
- Pixel electrodes 17a and 17b are formed on the inorganic interlayer insulating film 25, and an alignment film (not shown) is formed so as to cover these (pixel electrodes 17a and 17b).
- the inorganic interlayer insulating film 25 is penetrated, whereby the pixel electrode 17a and the drain lead wiring 27a are connected.
- the inorganic interlayer insulating film 25 is penetrated, whereby the pixel electrode 17a and the capacitor electrode 38a are connected.
- the capacitor electrode 37a connected in the same layer as the drain lead-out wiring 27a overlaps the pixel electrode 17b via the inorganic interlayer insulating film 25, whereby a coupling capacitor Cab1 (see FIG. 1) is formed, and the capacitor electrode 38a. Overlaps with the pixel electrode 17b through the inorganic interlayer insulating film 25, thereby forming a coupling capacitor Cab2 (see FIG. 1).
- the capacitor electrode 37a overlaps the storage capacitor wiring 18p via the inorganic gate insulating film 22, whereby a storage capacitor Cha1 (see FIG. 1) is formed, and the capacitor electrode 38a passes through the inorganic gate insulating film 22. This overlaps with the storage capacitor line 18p, thereby forming a storage capacitor Cha2 (see FIG. 1). Further, the pixel electrode 17b and the storage capacitor wiring 18p overlap with each other via the inorganic interlayer insulating film 25 and the inorganic gate insulating film 22, thereby forming the storage capacitor Chb (see FIG. 1).
- the colored layer 14 is formed on the glass substrate 32, the common electrode (com) 28 is formed thereon, and an alignment film (not shown) is formed so as to cover the common electrode (com) 28. Yes.
- FIG. 5 is a timing chart showing a driving method of the present liquid crystal display device (normally black mode liquid crystal display device) provided with the liquid crystal panel shown in FIGS.
- Sv and SV indicate signal potentials supplied to two adjacent data signal lines (for example, 15x and 15y), and Gx and Gy are gate-on pulse signals supplied to the scanning signal lines 16x and 16y.
- Va ⁇ Vb, VA ⁇ VB, and Vc ⁇ Vd indicate the potentials of the pixel electrodes 17a and 17b, 17A and 17B, and 17c and 17d, respectively.
- the scanning signal lines are sequentially selected, the polarity of the signal potential supplied to the data signal lines is inverted every horizontal scanning period (1H), and the same number in each frame.
- the polarity of the signal potential supplied in the horizontal scanning period is inverted in units of one frame, and in the same horizontal scanning period, a signal potential having a reverse polarity is supplied to two adjacent data signal lines.
- the scanning signal lines are sequentially selected (for example, the scanning signal lines 16x and 16y are selected in this order), and one of the two adjacent data signal lines (for example, , A signal potential having a positive polarity is supplied to the data signal line 15x in the first horizontal scanning period (for example, including the writing period of the pixel electrode 17a), and the second horizontal scanning period (for example, writing of the pixel electrode 17c) is performed.
- a negative polarity signal potential is supplied to the other of the two data signal lines (for example, the data signal line 15y) for the first horizontal scanning period (for example, the writing period of the pixel electrode 17A).
- a subpixel including 17d is “dark”, a subpixel including pixel electrode 17A (minus polarity) is “bright”, and a subpixel including pixel electrode 17B (minus polarity) is “dark”. Is as shown in FIG.
- the scanning signal lines are sequentially selected (for example, the scanning signal lines 16x and 16y are selected in this order), and one of the two adjacent data signal lines (for example, the data signal line 15x) is the first.
- the negative polarity signal potential is supplied during the horizontal scanning period (for example, including the writing period of the pixel electrode 17a), and the positive polarity signal potential is supplied for the second horizontal scanning period (for example, including the writing period of the pixel electrode 17c).
- a positive polarity signal potential is supplied to the other of the two data signal lines (for example, the data signal line 15y) in the first horizontal scanning period (for example, including the writing period of the pixel electrode 17A).
- a negative polarity signal potential is supplied in the first horizontal scanning period (for example, including the writing period of the pixel electrode 17C). Accordingly, as shown in FIG. 5,
- , and the sub-pixel including the pixel electrode 17a (minus) is “bright”.
- the subpixel including the pixel electrode 17b (minus) is “dark”, the subpixel including the pixel electrode 17c (plus polarity) is “bright”, and the subpixel including the pixel electrode 17d (plus polarity) is “dark”.
- the sub-pixel including the electrode 17A (plus polarity) is “bright”, and the sub-pixel including the pixel electrode 17B (plus polarity) is “dark”, as shown in FIG. 6B as a whole.
- an alignment regulating slit is formed in the pixel electrode 17a.
- S1 to S4 are provided
- alignment regulating ribs L1 and L2 are provided in a portion corresponding to the pixel electrode 17a of the color filter substrate
- alignment regulating slits S5 to S8 are provided in the pixel electrode 17b, and the color filter substrate.
- Orientation regulating ribs L3 and L4 are provided at portions corresponding to the pixel electrodes 17b.
- an alignment regulating slit may be provided in the common electrode of the color filter substrate.
- the pixel electrode 17a and the pixel electrode 17b are connected (capacitively coupled) by two parallel coupling capacitors (Cab1 and Cab2).
- the capacitive coupling of the pixel electrodes 17a and 17b can be maintained by the capacitive electrode 38a even if the wire is disconnected (in the manufacturing process or the like).
- the drain lead-out line 27a is cut at a portion after the contact hole 11a, or The capacitive coupling of the pixel electrodes 17a and 17b can be maintained by performing a correction process in which the capacitive electrode 37a is laser-cut between the connection portion with the pixel electrode 17a and the short-circuit portion.
- the capacitor electrode 38a and the storage capacitor wiring 18p or the pixel electrode 17b are short-circuited, the capacitor electrode 38a may be laser-cut between the contact hole 68a and the short-circuited portion.
- the drain lead-out wiring 27a (part after the contact hole 11a) is irradiated with a laser from the back surface (glass substrate side) of the active matrix substrate to cut it (see FIG. 8) or from the front surface of the active matrix substrate (opposite the glass substrate), the drain lead wiring 27a is irradiated with laser through the gap between the pixel electrodes 17a and 17b to cut it. become. Further, when the correction process is performed at the liquid crystal panel stage, the drain lead-out wiring 27a (part after the contact hole 11a) is irradiated with laser from the back surface of the liquid crystal panel (the glass substrate side of the active matrix substrate) to cut it. Will do.
- the present embodiment it is possible to increase the manufacturing yield of the liquid crystal panel and the active matrix substrate used therefor.
- the conventional active matrix substrate (reference) shown in FIG. 47 if the lead wiring 119 is disconnected, the potential control of the pixel electrode 121b becomes impossible.
- the control electrode 118 and the capacitor wiring 113 are short-circuited, the signal potential can be written to the pixel electrode 121a by cutting the lead-out wiring 119, but the pixel electrode 121b is connected to the pixel electrode 121a. 121c is not capacitively coupled.
- each of the capacitance electrodes 37a and 38a overlaps with the pixel electrode 17b and the storage capacitance wiring 18p.
- the aperture ratio can be increased by causing the capacitance electrodes 37a and 38a provided for forming the coupling capacitance to function as electrodes for forming the storage capacitance.
- the method for manufacturing a liquid crystal panel includes an active matrix substrate manufacturing process, a color filter substrate manufacturing process, and an assembly process in which both substrates are bonded to each other and filled with liquid crystal.
- an inspection process is performed during or after at least one of the active matrix substrate manufacturing process and the assembly process, and when a pixel (sub-pixel) defect is detected in the inspection process, a correction process for correcting the defect is added. Is done.
- a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, or copper, an alloy film thereof, or a laminated film thereof (thickness: 1000 mm to 3000 mm) is sputtered onto a substrate such as glass or plastic. Then, patterning is performed by photolithography technology (Photo Engraving Process, hereinafter referred to as “PEP technology”), and scanning signal lines and gate electrodes of transistors (scanning signal lines may also serve as gate electrodes) ) And a storage capacitor wiring.
- PEP technology Photo Engraving Process
- an inorganic insulating film such as silicon nitride or silicon oxide is formed by CVD (Chemical Vapor Deposition) method on the entire substrate on which the scanning signal lines are formed, thereby forming a gate insulating film To do.
- an intrinsic amorphous silicon film (thickness 1000 to 3000 mm) and an n + amorphous silicon film (thickness 400 to 700 mm) doped with phosphorus are continuously formed on the gate insulating film (whole substrate) by CVD.
- patterning is performed by the PEP technique, and a silicon laminated body including an intrinsic amorphous silicon layer and an n + amorphous silicon layer is formed in an island shape on the gate electrode.
- a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, or copper, an alloy film thereof, or a stacked film thereof (thickness 1000 to 3000 mm) is formed on the entire substrate on which the silicon laminate is formed. Then, patterning is performed by the PEP technique to form data signal lines, transistor source / drain electrodes, drain lead-out wirings, and capacitor electrodes.
- the n + amorphous silicon layer constituting the silicon stacked body is removed by etching to form a transistor channel.
- the semiconductor layer may be formed of an amorphous silicon film as described above.
- a polysilicon film may be formed, or a laser annealing treatment is performed on the amorphous silicon film and the polysilicon film to form a crystal. May be improved. Thereby, the moving speed of the electrons in the semiconductor layer is increased, and the characteristics of the transistor (TFT) can be improved.
- an inorganic insulating film such as silicon nitride or silicon oxide is formed by CVD on the entire substrate on which the data signal lines and the like are formed to form an inorganic interlayer insulating film.
- the interlayer insulating film is etched away by PEP technology to form a contact hole.
- a transparent conductive film (thickness 1000 to 2000 mm) made of ITO (Indium / Tin / Oxide), IZO (Indium / Zinc / Oxide), zinc oxide, tin oxide or the like is formed on the entire substrate on the interlayer insulating film in which the contact holes are formed. Is formed by sputtering, and then patterned by PEP technology to form each pixel electrode.
- polyimide resin is printed on the entire substrate on the pixel electrode with a thickness of 500 to 1000 mm, and then fired and rubbed in one direction with a rotating cloth to form an alignment film.
- the active matrix substrate is manufactured as described above.
- the color filter substrate manufacturing process will be described below.
- a chromium thin film or a resin containing a black pigment is formed on a glass or plastic substrate (entire substrate), and then patterned by PEP technology to form a black matrix.
- red, green and blue color filter layers are formed in a pattern in the gap of the black matrix by using a pigment dispersion method or the like.
- a transparent conductive film made of ITO, IZO, zinc oxide, tin oxide or the like is formed on the entire substrate on the color filter layer to form a common electrode (com).
- polyimide resin is printed on the entire substrate on the common electrode with a thickness of 500 to 1000 mm, and then fired and rubbed in one direction with a rotating cloth to form an alignment film.
- a color filter substrate can be manufactured as described above.
- a seal material made of a thermosetting epoxy resin or the like is applied to one of the active matrix substrate and the color filter substrate by screen printing in a frame-like pattern lacking the liquid crystal inlet portion, and the liquid crystal layer is applied to the other substrate.
- a spherical spacer having a diameter corresponding to the thickness and made of plastic or silica is dispersed.
- the active matrix substrate and the color filter substrate are bonded together, and the sealing material is cured.
- the liquid crystal panel is manufactured.
- a short-circuit occurrence location is detected by performing an appearance inspection or an electro-optical inspection on the active matrix substrate.
- the short circuit include a short circuit between the capacitor electrode and the storage capacitor wiring and a short circuit between the capacitor electrode and the pixel electrode.
- the appearance inspection is to optically inspect the wiring pattern using a CCD camera or the like.
- the electro-optical inspection is an active inspection after a modulator (electro-optical element) is placed so as to face the active matrix substrate.
- a wiring pattern is electro-optically inspected by applying a voltage between a matrix substrate and a modulator and making light incident and capturing a change in luminance of the light with a CCD camera.
- a correction process is performed in which the short-circuited capacitive electrode or a conductor portion (for example, drain lead wiring) connected thereto is laser-cut.
- a fourth harmonic (wavelength 266 nm) of a YAG (Yttrium Aluminum Garnet) laser is used.
- a correction process may be performed in which a portion in the contact hole is removed (trimmed) by a laser or the like among the pixel electrodes connected to the short-circuited capacitor electrode via the contact hole. .
- laser irradiation can usually be performed from the front surface (pixel electrode side) or the back surface (substrate side) of the active matrix substrate.
- the first inspection step and the correction step may be performed after the formation of the pixel electrode, the formation of the capacitor electrode, or the formation of the channel of the transistor. In this way, defects can be corrected at an earlier stage of the manufacturing process, and the manufacturing yield of the active matrix substrate can be increased.
- a short circuit location is detected by performing a lighting inspection on the liquid crystal panel.
- the short circuit include a short circuit between the capacitor electrode and the storage capacitor wiring and a short circuit between the capacitor electrode and the pixel electrode.
- a gate inspection signal having a bias voltage of ⁇ 10 V, a period of 16.7 msec, a pulse width of 50 ⁇ sec and a pulse voltage of +15 V is input to each scanning signal line to turn on all TFTs.
- a source inspection signal having a potential of ⁇ 2 V whose polarity is inverted every 16.7 msec is input to each data signal line, and a signal potential corresponding to ⁇ 2 V is applied to the pixel electrode via the source electrode and the drain electrode of each TFT.
- a common electrode inspection signal having a direct current potential of ⁇ 1 V is input to the common electrode (com) and the storage capacitor wiring.
- a voltage is applied to the liquid crystal capacitor formed between the pixel electrode and the common electrode, and the storage capacitor formed between the storage capacitor wiring and the capacitor electrode, and the sub-pixel configured by the pixel electrode is turned on. It becomes a state.
- the pixel electrode and the storage capacitor wiring are brought into conduction and become a black spot (normally black). Thereby, a short circuit location is detected.
- a correction process is performed in which the short-circuited capacitive electrode or a conductor portion (for example, drain lead wiring) connected thereto is laser-cut.
- laser irradiation is usually performed from the back surface of the active matrix substrate (the substrate side of the active matrix substrate).
- the cross section AB in FIG. 2 may be configured as shown in FIG. That is, the thick organic gate insulating film 21 and the thin inorganic gate insulating film 22 are formed on the glass substrate 31, and the thin inorganic interlayer insulating film 25 and the thick organic interlayer insulating film 26 are formed below the pixel electrode. In this way, effects such as reduction of various parasitic capacitances, prevention of short-circuiting between wirings, and reduction of pixel electrode tearing due to planarization can be obtained. In this case, as shown in FIG.
- the organic gate insulating film 21 is pierced through the portion located below the capacitive electrodes 37a and 38a, and the organic interlayer insulating film 26 is placed on the capacitive electrodes 37a and 38a. It is preferable to pierce through the position. By doing so, the above-described effects can be obtained while sufficiently securing the capacitance value of the coupling capacitance (Cab1 ⁇ Cab2) and the capacitance value of the holding capacitance (Cha1 ⁇ Cha2 ⁇ Chb).
- the penetrated portion (thin film portion 51a) of the organic interlayer insulating film 26 is a region as indicated by a dotted line portion in FIG.
- the thin film portion 51a is formed in a rectangular shape by the first side (J1) to the fourth side (J4), the capacitive electrode 37a straddles the first side (J1), and the capacitance A capacitive electrode 38a arranged side by side in the row direction with the electrode 37a straddles the third side (J3) facing the first side (J1).
- the inorganic interlayer insulating film 25, the organic interlayer insulating film 26, and the contact holes 11a and 11b in FIG. 4 can be formed as follows, for example. That is, after forming a transistor (TFT) and a data signal line, a mixed gas of SiH 4 gas, NH 3 gas and N 2 gas is used, and an inorganic interlayer made of SiNx having a thickness of about 3000 mm so as to cover the entire surface of the substrate. An insulating film 25 (passivation film) is formed by CVD. Thereafter, an organic interlayer insulating film 26 made of a positive photosensitive acrylic resin having a thickness of about 3 ⁇ m is formed by spin coating or die coating.
- photolithography is performed to form a penetrating portion of the organic interlayer insulating film 26 and various contact patterns. Further, using the patterned organic interlayer insulating film 26 as a mask, CF 4 gas and O 2 gas The inorganic interlayer insulating film 25 is dry-etched using a mixed gas. Specifically, for example, the penetration portion of the organic interlayer insulating film is half-exposed in the photolithography process so that the organic interlayer insulating film remains thin when development is completed, while the contact hole portion is By performing full exposure in the photolithography process, an organic interlayer insulating film is not left when development is completed.
- the organic gate insulating film 21 and the organic interlayer insulating film 26 may be, for example, an insulating film made of a SOG (spin-on glass) material, and the organic gate insulating film 21 and the organic interlayer insulating film 26 are made of acrylic resin. , At least one of an epoxy resin, a polyimide resin, a polyurethane resin, a novolac resin, and a siloxane resin may be contained.
- the drain electrode 9a of the transistor 12a is connected to the pixel electrode 17a through the contact hole 11a, and the pixel electrode 17a and the capacitor electrode 37a are connected through the contact hole 67a.
- the drain lead wiring connecting the drain electrode 9a and the capacitor electrode 37a can be shortened, and the aperture ratio can be increased.
- the pixel electrode 17a and the pixel electrode 17b are connected (capacitively coupled) by two coupling capacitors (Cab1 and Cab2) in parallel, a contact hole 67a is formed in a manufacturing process or the like. Even when it becomes defective, the capacitive coupling of the pixel electrodes 17a and 17b can be maintained.
- the storage capacitor Chb may be formed by the configuration shown in FIG. That is, as shown in FIG. 11, the storage capacitor electrode 39b formed in the same layer as the capacitor electrodes 37a and 38a is connected to the pixel electrode 17b through the contact hole 69b, whereby the storage capacitor electrode 39b and the storage capacitor A storage capacitor Chb is formed between the wiring 18p.
- the storage capacitor Chb since the storage capacitor Chb is formed between the pixel electrode 17b and the storage capacitor line 18p as shown in FIG. 2, the insulating film interposed therebetween can be reduced (thin). , You can earn a retention capacity value.
- the insulating film forming the storage capacitor Chb can be made thin, the width of the storage capacitor wiring 18p can be narrowed without changing the size of the storage capacitor value, and the aperture ratio can be improved without degrading the reliability. The effect that it can plan is also acquired.
- the present invention is not limited to this.
- one of the two pixel electrodes provided in one pixel, which is far from the transistor, may be connected to the transistor.
- a specific example of the pixel 101 in FIG. 12 is shown in FIG. In the liquid crystal panel of FIG. 1, of the two pixel electrodes provided in one pixel, the one closer to the transistor is connected to the transistor, but the present invention is not limited to this.
- a specific example of the pixel 101 in FIG. 12 is shown in FIG. In the liquid crystal panel of FIG.
- a transistor 12a is disposed in the vicinity of the intersection of the data signal line 15x and the scanning signal line 16x, and a rectangular pixel electrode 17a and The rectangular pixel electrodes 17b are arranged in the column direction, and one of the four sides forming the outer periphery of the first pixel electrode is adjacent to one of the four sides forming the outer periphery of the second pixel electrode. Yes.
- the storage capacitor line 18p extending in the row direction is arranged so as to overlap the pixel electrode 17a.
- the capacitor electrodes 37b and 38b are arranged so as to overlap the storage capacitor line 18p and the pixel electrode 17a.
- the capacitor electrode 37b extends in the same direction as the storage capacitor wiring 18p and overlaps the storage capacitor wiring 18p and the pixel electrode 17a.
- the capacitor electrode 38b is arranged side by side in the row direction (the extending direction) with the capacitor electrode 37b, extends in the same direction as the extending direction of the storage capacitor line 18p, and overlaps the storage capacitor line 18p and the pixel electrode 17a.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a.
- the drain lead wiring 27a is connected to the capacitor electrode 37b formed in the same layer and is connected to the pixel electrode 17b through the contact hole 11b.
- the capacitor electrode 37b is connected to the interlayer insulating film.
- the coupling capacitor Cab1 (see FIG. 12) between the pixel electrodes 17a and 17b is formed at the overlapping portion of the pixel electrode 17a.
- the capacitor electrode 38b is connected to the pixel electrode 17b through the contact hole 68b and overlaps the pixel electrode 17a through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab2 (see FIG. 12) is formed.
- the capacitor electrode 37b overlaps the storage capacitor wiring 18p via the gate insulating film, and the storage capacitor Chb1 (see FIG. 12) is formed at the overlapping portion between them, and the capacitor electrode 38b passes through the gate insulating film via the gate insulating film.
- the storage capacitor Chb2 (see FIG. 12) is formed at the overlapping portion of the wiring 18p.
- the pixel electrode 17a and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a storage capacitor Cha (see FIG. 12) is formed at the overlapping portion between the two.
- the subpixel including the pixel electrode 17a is “dark”, and the subpixel including the pixel electrode 17b is “bright”.
- the pixel electrode 17a and the pixel electrode 17b are connected (capacitively coupled) by two coupling capacitors (Cab1 and Cab2) in parallel, for example, the capacitor electrode 37b at P in FIG.
- the pixel electrode 17a and the pixel electrode 17a are short-circuited (in the manufacturing process or the like)
- the pixel electrode 17a or 17b is subjected to a correction process in which the capacitor electrode 37b is laser-cut between the contact hole 11b and the short-circuited portion.
- the capacitive coupling can be maintained.
- the capacitor electrode 38b and the pixel electrode 17a are short-circuited, the capacitor electrode 38b may be laser-cut between the contact hole 68b and the short-circuited portion.
- one of two pixels adjacent in the row direction is connected to the pixel electrode closer to the transistor, and the other is connected to the transistor farther from the transistor.
- the subpixel including the pixel electrode 17a (positive polarity) is “bright”, and the pixel electrode 17b
- the subpixel including (positive polarity) is “dark”
- the subpixel including the pixel electrode 17c (minus polarity) is “bright”
- the subpixel including the pixel electrode 17d (minus polarity) is “dark”
- the pixel electrode 17A The sub-pixel including (minus polarity) is “dark”
- the sub-pixel including the pixel electrode 17B (minus polarity) is “bright”, as a whole, as shown in FIG.
- the subpixel including the pixel electrode 17a (minus polarity) is “bright”, the subpixel including the pixel electrode 17b (minus polarity) is “dark”, and the subpixel including the pixel electrode 17c (plus polarity).
- the sub-pixel including the pixel electrode 17d positive polarity
- the sub-pixel including the pixel electrode 17A positive polarity
- the sub-pixel including the pixel electrode 17B positive polarity
- liquid crystal panel of FIG. 14 bright subpixels are not aligned in the row direction, and dark subpixels are not aligned in the row direction, so that unevenness in the row direction can be reduced.
- FIG. 16 shows a specific example of the pixels 101 and 103 in FIG.
- a transistor 12a is disposed in the vicinity of the intersection of the data signal line 15x and the scanning signal line 16x, and the pixel region defined by both signal lines (15x and 16x) has a rectangular shape.
- the pixel electrode 17a and the rectangular pixel electrode 17b are arranged in the column direction, and one of the four sides forming the outer periphery of the first pixel electrode and one of the four sides forming the outer periphery of the second pixel electrode. And are adjacent.
- the storage capacitor wiring 18p extending in the row direction is arranged so as to overlap the entire gap between the two adjacent sides (the gap between the pixel electrodes 17a and 17b).
- the capacitor electrodes 37a and 38a are arranged so as to overlap the storage capacitor line 18p and the pixel electrode 17b.
- the capacitor electrode 37a extends in the same direction as the storage capacitor wiring 18p and overlaps the storage capacitor wiring 18p and the pixel electrode 17b.
- the capacitor electrode 38a is arranged side by side in the row direction (the extending direction) with the capacitor electrode 37a, extends in the same direction as the extending direction of the storage capacitor line 18p, and overlaps the storage capacitor line 18p and the pixel electrode 17b.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a.
- the drain lead wiring 27a is connected to the capacitor electrode 37a formed in the same layer and is connected to the pixel electrode 17a through the contact hole 11a.
- the capacitor electrode 37a is connected to the interlayer insulating film.
- the coupling capacitor Cab1 (see FIG. 14) between the pixel electrodes 17a and 17b is formed at the overlapping portion of the pixel electrode 17b.
- the capacitor electrode 38a is connected to the pixel electrode 17a through the contact hole 68a and overlaps the pixel electrode 17b through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab2 (see FIG. 14) is formed.
- the capacitor electrode 37a overlaps the storage capacitor wiring 18p via the gate insulating film, and a large part of the storage capacitor Cha1 (see FIG. 14) is formed in the overlapping portion between them, and the capacitor electrode 38a passes through the gate insulating film. It overlaps with the storage capacitor line 18p, and most of the storage capacitor Cha2 (see FIG. 14) is formed in the overlapping portion between them.
- the pixel electrode 17b and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a storage capacitor Chb (see FIG. 14) is formed in the overlapping portion of both.
- a transistor 12A is disposed in the vicinity of the intersection of the data signal line 15y and the scanning signal line 16x, and a rectangular pixel electrode 17A and a rectangular shape are formed in a pixel region defined by both signal lines (15y ⁇ 16x).
- the pixel electrodes 17B having a shape are arranged in the column direction, and one of the four sides forming the outer periphery of the first pixel electrode is adjacent to one of the four sides forming the outer periphery of the second pixel electrode.
- the storage capacitor wiring 18p extending in the row direction is arranged so as to overlap the entire gap between the two adjacent sides (the gap between the pixel electrodes 17A and 17B).
- the capacitor electrodes 37B and 38B are arranged so as to overlap the storage capacitor line 18p and the pixel electrode 17A.
- the capacitor electrode 37B extends in the same direction as the extending direction of the storage capacitor line 18p and overlaps the storage capacitor line 18p and the pixel electrode 17A.
- the capacitor electrode 38B is arranged side by side in the row direction (the extending direction) with the capacitor electrode 37B, extends in the same direction as the extending direction of the storage capacitor line 18p, and overlaps the storage capacitor line 18p and the pixel electrode 17A.
- the source electrode 8A and the drain electrode 9A of the transistor 12A are formed on the scanning signal line 16x, and the source electrode 8A is connected to the data signal line 15y.
- the drain electrode 9A is connected to the drain lead wiring 27A.
- the drain lead wiring 27A is connected to the capacitor electrode 37B formed in the same layer and connected to the pixel electrode 17B through the contact hole 11B.
- the capacitor electrode 37B is connected to the interlayer insulating film.
- the coupling capacitor CAB1 (see FIG. 14) between the pixel electrodes 17A and 17B is formed at the overlapping portion of the pixel electrode 17A.
- the capacitor electrode 38B is connected to the pixel electrode 17B through the contact hole 68B and overlaps the pixel electrode 17A through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17A and 17B is overlapped with both of them.
- CAB2 (see FIG. 14) is formed.
- the capacitor electrode 37B overlaps the storage capacitor wiring 18p through the gate insulating film, and a large part of the storage capacitor ChB1 (see FIG. 14) is formed in the overlapping portion between them, and the capacitor electrode 38B passes through the gate insulating film. It overlaps with the storage capacitor line 18p, and most of the storage capacitor ChB2 (see FIG. 14) is formed in the overlapping portion between them.
- the pixel electrode 17A and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a storage capacitor ChA (see FIG. 14) is formed in the overlapping portion between them.
- the capacitor electrode is electrically connected to the pixel electrode corresponding to the sub-pixel that becomes the bright sub-pixel, but the present invention is not limited to this.
- the present liquid crystal panel may have a configuration in which the capacitor electrode is electrically connected to a pixel electrode corresponding to a sub-pixel that is a dark sub-pixel.
- a specific example 101 of the pixel in FIG. 17 is shown in FIG.
- a transistor 12a is disposed in the vicinity of the intersection of the data signal line 15x and the scanning signal line 16x.
- the rectangular pixel electrodes 17b are arranged in the column direction, and one of the four sides forming the outer periphery of the first pixel electrode is adjacent to one of the four sides forming the outer periphery of the second pixel electrode. Yes.
- the storage capacitor line 18p extending in the row direction is arranged so as to overlap the pixel electrode 17a.
- the capacitor electrodes 37b and 38b are arranged so as to overlap the storage capacitor line 18p and the pixel electrode 17a.
- the capacitor electrode 37b extends in the same direction as the storage capacitor wiring 18p and overlaps the storage capacitor wiring 18p and the pixel electrode 17a.
- the capacitor electrode 38b is arranged side by side in the row direction (the extending direction) with the capacitor electrode 37b, extends in the same direction as the extending direction of the storage capacitor line 18p, and overlaps the storage capacitor line 18p and the pixel electrode 17a.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- the capacitor electrode 37b is connected to the pixel electrode 17b through the contact hole 67b and overlaps with the pixel electrode 17a through an interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab1 (see FIG. 17) is formed.
- the capacitor electrode 38b is connected to the pixel electrode 17b through the contact hole 68b and overlaps the pixel electrode 17a through the interlayer insulating film, and the coupling capacitance Cab2 between the pixel electrodes 17a and 17b is overlapped with both of them. (See FIG. 17) is formed.
- the capacitor electrode 37b overlaps the storage capacitor wiring 18p via the gate insulating film, and the storage capacitor Chb1 (see FIG. 17) is formed in the overlapping portion between them, and the capacitor electrode 38b passes through the gate insulating film.
- the storage capacitor Chb2 (see FIG. 17) is formed at the overlapping portion of the wiring 18p.
- the pixel electrode 17a and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a storage capacitor Cha (see FIG. 17) is formed at the overlapping portion between them.
- the sub-pixel including the pixel electrode 17a is “bright”, and the sub-pixel including the pixel electrode 17b is “dark”.
- the capacitor electrode 37b at P in FIG.
- the pixel electrode 17a and the pixel electrode 17a are connected (capacitively coupled) by two parallel coupling capacitors (Cab1 and Cab2), for example, the capacitor electrode 37b at P in FIG.
- the pixel electrode 17a or 17b is subjected to a correction process in which the capacitor electrode 37b is laser-cut between the contact hole 67b and the short-circuited portion.
- the capacitive coupling can be maintained.
- the capacitor electrode 38b and the pixel electrode 17a are short-circuited, the capacitor electrode 38b may be laser-cut between the contact hole 68b and the short-circuited portion.
- FIG. 19 is an equivalent circuit diagram showing a part of the liquid crystal panel according to the second embodiment.
- data signal lines (15x ⁇ 15y) extending in the column direction (vertical direction in the drawing) and scanning signal lines (16x ⁇ 16y) extending in the row direction (horizontal direction in the drawing).
- Pixels (101 to 104) arranged in the row and column directions, storage capacitor lines (18p, 18q), and common electrode (counter electrode) com, and the structure of each pixel is the same.
- the pixel column including the pixels 101 and 102 and the pixel column including the pixels 103 and 104 are adjacent to each other, and the pixel row including the pixels 101 and 103 and the pixel row including the pixels 102 and 104 are adjacent to each other. is doing.
- one data signal line and one scanning signal line are provided corresponding to one pixel.
- one pixel is provided with two pixel electrodes, one of which surrounds the other, the pixel 101 is provided with a pixel electrode 17b and a pixel electrode 17a surrounding the pixel electrode, and the pixel 102 includes a pixel electrode 17d and A pixel electrode 17c surrounding the pixel electrode 17c and a pixel electrode 17B surrounding the pixel electrode 17B are provided.
- the pixel 104 includes a pixel electrode 17D and a pixel electrode 17C surrounding the pixel electrode 17C. .
- FIG. 20 shows a specific example of the pixel 101 in FIG.
- a transistor 12a is disposed in the vicinity of the intersection of the data signal line 15x and the scanning signal line 16x, and the pixel region defined by both signal lines (15x and 16x) has a V direction when viewed in the row direction.
- a pixel electrode 17b having a letter shape and a pixel electrode 17a surrounding the pixel electrode 17b are arranged, and a storage capacitor line 18p extends in the row direction across the center of the pixel.
- the pixel electrode 17b is on the storage capacitor line 18p and forms a first side that forms approximately 90 ° with respect to the row direction and an angle of approximately 45 ° with respect to the row direction from one end of the first side.
- a second side extending, a third side extending substantially 315 ° from the other end of the first side with respect to the row direction, one end on the storage capacitor wiring 18p, parallel to the second side, and A fourth side that is shorter than this, a sixth side that is connected to one end of the fourth side, is parallel to the third side and is shorter than the third side, and connects the second and fourth sides;
- the inner periphery of the pixel electrode 17a is composed of seven sides opposed to the first to seventh sides.
- a gap between the first side of the pixel electrode 17b and one side of the inner periphery of the pixel electrode 17a facing the first side is a first gap K1, and the second side of the pixel electrode 17b and the pixel electrode 17a facing the second side.
- the gap between one side of the inner circumference of the pixel electrode is the second gap K2, and the gap between the third side of the pixel electrode 17b and the one side of the inner circumference of the pixel electrode 17a opposite thereto is the third gap K3.
- the gap between the fourth side of the pixel electrode 17b and one side of the inner periphery of the pixel electrode 17a facing this is the fourth gap K4, and the fifth side of the pixel electrode 17b and the pixel electrode 17a facing this are separated.
- a gap with one side of the inner periphery is a fifth gap K5.
- the capacitive electrodes 37a and 38a are arranged so as to overlap the first gap K1, the pixel electrode 17a, and the pixel electrode 17b. More specifically, the capacitor electrodes 37a and 38a both have a shape extending in the row direction so as to cross the first gap K1, and are arranged in the column direction so as to overlap the storage capacitor line 18p. .
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- the capacitor electrode 37a is connected to the pixel electrode 17a through the contact hole 67a and overlaps with the pixel electrode 17b through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab1 (see FIG. 19) is formed.
- the capacitor electrode 38a is connected to the pixel electrode 17a through the contact hole 68a and overlaps with the pixel electrode 17b through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab2 (see FIG. 19) is formed.
- the capacitor electrode 37a overlaps the storage capacitor wiring 18p via the gate insulating film, and a large part of the storage capacitor Cha1 (see FIG. 19) is formed in the overlapping portion between them, and the capacitor electrode 38a passes through the gate insulating film. It overlaps with the storage capacitor line 18p, and most of the storage capacitor Cha2 (see FIG. 19) is formed in the overlapping portion between them.
- the pixel electrode 17b and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a storage capacitor Chb (see FIG. 19) is formed at the overlapping portion between them.
- the pixel electrode 17a and the pixel electrode 17b are connected (capacitively coupled) by two parallel coupling capacitors (Cab1 and Cab2).
- the capacitor electrode 37a is laser-cut between the contact hole 67a and the short-circuited portion, thereby performing a correction process. Capacitive coupling can be maintained. Further, even when the contact hole 67a is poorly formed in the manufacturing process or the like, the capacitive coupling of the pixel electrodes 17a and 17b can be maintained.
- the capacitor electrode 38a and the storage capacitor line 18p or the pixel electrode 17b are short-circuited, the capacitor electrode 38a may be laser-cut between the contact hole 68a and the short-circuited portion.
- the capacitive electrode 37a is irradiated with laser from the front surface of the active matrix substrate (opposite the glass substrate) through the gap between the pixel electrodes 17a and 17b to cut it.
- the capacitive electrode 37a is irradiated with laser from the front surface of the active matrix substrate (opposite the glass substrate) through the gap between the pixel electrodes 17a and 17b to cut it.
- an opening may be formed in the storage capacitor wiring 18p so as to overlap the first gap K1.
- capacitor electrode 37a and the storage capacitor wiring 18p or the pixel electrode 17b are short-circuited, a portion of the pixel electrode 17a in the contact hole 67a is removed (trimmed) by a laser or the like, and the pixel electrode 17a and the capacitor are removed. Capacitive coupling of the pixel electrodes 17a and 17b can also be maintained by electrically disconnecting the electrode 37a.
- the capacitor electrode 37a overlaps the pixel electrode 17b and the storage capacitor line 18p, and the capacitor electrode 38a overlaps the pixel electrode 17b and the storage capacitor line 18p.
- the aperture ratio can be increased by causing the capacitance electrodes 37a and 38a provided for forming the coupling capacitance to function as electrodes for forming the storage capacitance.
- the pixel electrode 17a since the pixel electrode 17a surrounds the pixel electrode 17b that is electrically floating, the pixel electrode 17a functions as a shield electrode and suppresses the jumping of charges into the pixel electrode 17b. can do. Thereby, the burn-in of the sub-pixel (dark sub-pixel) including the pixel electrode 17b can be suppressed.
- the description of the alignment regulating structure is omitted.
- K5 functions as an alignment regulating structure
- a rib L3 parallel to the gaps K2 and K4 and a rib L4 parallel to the gaps K3 and K5 are provided in a portion corresponding to the pixel electrode 17b of the color filter substrate.
- Ribs L1 and L5 parallel to the gaps K2 and K4 and ribs L2 and L6 parallel to the gaps K3 and K5 are provided in a portion corresponding to the pixel electrode 17a of the filter substrate.
- an alignment regulating slit may be provided in the common electrode of the color filter substrate.
- the capacitor electrodes 37a and 38a have a shape extending 315 ° with respect to the row direction so as to intersect the third gap K3, and do not overlap with the storage capacitor line 18p.
- the drain electrode 9a of the transistor 12a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- the capacitor electrode 37a is connected to the pixel electrode 17a through the contact hole 67a and overlaps with the pixel electrode 17b through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them. Cab1 (see FIG. 19) is formed.
- the capacitor electrode 38a is connected to the pixel electrode 17a through the contact hole 68a, and the capacitor electrode 38a overlaps the pixel electrode 17b through the interlayer insulating film, and the pixel electrodes 17a and 17b are overlapped with each other.
- a coupling capacitor Cab2 (see FIG. 19) is formed. Further, a part of the pixel electrode 17a overlaps with the storage capacitor wiring 18p via the gate insulating film and the interlayer insulating film, and the storage capacitor Cha (corresponding to Cha1 and Cha2 in FIG. 19) is formed in the overlapping portion of both. . In addition, a part of the pixel electrode 17b overlaps with the storage capacitor wiring 18p via the gate insulating film and the interlayer insulating film, and a storage capacitor Chb (see FIG. 19) is formed at the overlapping portion between them.
- the capacitor electrode 37 a and the pixel electrode 17 b are short-circuited (in the manufacturing process or the like)
- the third side Through the gap K3 the capacitor electrode 37a (which does not overlap with the storage capacitor line 18p) can be irradiated with laser to cut it.
- the pixel electrode 17a and the capacitor electrode 37a may be electrically separated by removing (trimming) a portion of the pixel electrode 17a in the contact hole 67a with a laser or the like.
- the storage capacitor line 18p extends from the storage capacitor line 18p so as to overlap the first side, the second side, the sixth side, and the fourth side of the pixel electrode 17b, and merges with the storage capacitor line 18p again.
- a storage capacitor wiring extending portion 18y that extends from the portion 18x and the storage capacitor wiring 18p so as to overlap the first side, the third side, the seventh side, and the fifth side of the pixel electrode 17b and merges with the storage capacitor wiring 18p again. And are provided.
- the storage capacitor wiring extending portions 18x and 18y surrounding the electrically floating pixel electrode 17b function as a shield electrode of the pixel electrode 17b, electric charge jumps into the pixel electrode 17b and the like. It can be effectively suppressed. Thereby, the burn-in of the sub-pixel (dark sub-pixel) including the pixel electrode 17b can be suppressed.
- FIG. 24 shows another specific example of the pixel 101 in FIG.
- a transistor 12a is disposed in the vicinity of the intersection of the data signal line 15x and the scanning signal line 16x, and a trapezoidal shape as viewed in the row direction is formed in the pixel region defined by both signal lines (15x and 16x).
- a pixel electrode 17b having a shape and a pixel electrode 17a surrounding the pixel electrode 17b are arranged, and a storage capacitor wiring 18p extends in the row direction across the center of the pixel.
- the pixel electrode 17b intersects with the storage capacitor line 18p and forms a first side that is approximately 90 ° with respect to the row direction, and a second side that is parallel to the first side and intersects with the storage capacitor line 18p.
- a third side extending from the one end of the first side at about 45 ° to the row direction, and a fourth side extending from the other end of the first side at about 315 ° to the row direction;
- the inner periphery of the pixel electrode 17a is composed of four sides facing the first to fourth sides, and the outer periphery of the pixel electrode 17a is rectangular.
- a gap between the first side of the pixel electrode 17b and one side of the inner periphery of the pixel electrode 17a facing the first side is a first gap K1, and the second side of the pixel electrode 17b and the pixel electrode 17a facing the second side.
- a gap with one side of the inner circumference is a second gap K2, and the capacitive electrode 37a is arranged to overlap the pixel electrode 17a, the first gap K1, and the pixel electrode 17b, and the capacitive electrode 38a is a pixel electrode. 17a, the second gap K2, and the pixel electrode 17b.
- the capacitor electrode 37a has a shape extending in the row direction so as to intersect the first gap K1
- the capacitor electrode 38a has a shape extending in the row direction so as to intersect the second gap K2. They are arranged in the row direction so as to overlap the storage capacitor wiring 18p.
- the capacitive electrodes 37a and 38a are arranged so as to substantially coincide with the capacitive electrode 37b when the capacitive electrode 37a is rotated by 180 ° about a point on the storage capacitive wiring 18p in the pixel 101. That is, the capacitive electrodes 37a and 38a are line symmetric with respect to a line parallel to the first gap K1 and the second gap K2 and passing through the centers of both gaps.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- the capacitor electrode 37a is connected to the pixel electrode 17a through the contact hole 67a and overlaps with the pixel electrode 17b through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab1 (see FIG. 19) is formed.
- the capacitor electrode 38a is connected to the pixel electrode 17a through the contact hole 68a, and the capacitor electrode 38a overlaps the pixel electrode 17b through the interlayer insulating film, and the pixel electrodes 17a and 17b are overlapped with each other.
- a coupling capacitor Cab2 (see FIG. 19) is formed.
- the capacitor electrode 37a overlaps the storage capacitor wiring 18p via the gate insulating film, and a large part of the storage capacitor Cha1 (see FIG. 19) is formed in the overlapping portion between them, and the capacitor electrode 38a passes through the gate insulating film. It overlaps with the storage capacitor line 18p, and most of the storage capacitor Cha2 (see FIG. 19) is formed in the overlapping portion between them.
- the pixel electrode 17b and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a storage capacitor Chb (see FIG. 19) is formed at the overlapping portion between them.
- the pixel electrode 17a and the pixel electrode 17b are connected (capacitively coupled) by two parallel coupling capacitors (Cab1 and Cab2).
- the capacitor electrode 38a and the storage capacitor wiring 18p or the pixel electrode 17b are short-circuited, the capacitor electrode 38a may be laser-cut between the contact hole 68a and the short-circuited portion.
- the capacitive electrode 37a is irradiated with a laser from the front surface (opposite side of the glass substrate) of the active matrix substrate through the first gap K1 to cut it.
- the capacitive electrode 37a is irradiated with a laser from the front surface (opposite side of the glass substrate) of the active matrix substrate through the first gap K1 to cut it.
- an opening may be formed in the storage capacitor wiring 18p so as to overlap the first gap K1.
- capacitor electrode 37a and the storage capacitor wiring 18p or the pixel electrode 17b are short-circuited, a portion of the pixel electrode 17a in the contact hole 67a is removed (trimmed) by a laser or the like, and the pixel electrode 17a and the capacitor are removed. Capacitive coupling of the pixel electrodes 17a and 17b can also be maintained by electrically disconnecting the electrode 37a.
- the capacitor electrodes 37a and 38a are arranged side by side in the extending direction (row direction) of the storage capacitor wiring 18p so as to overlap the storage capacitor wiring 18p.
- the capacitive electrodes 37a and 38a are symmetrical with respect to a line parallel to the first gap K1 and the second gap K2 and passing through the centers of the gaps.
- each of the capacitive electrodes 37a and 38a overlaps with the pixel electrode 17b and the holding capacitive wiring 18p.
- the aperture ratio can be increased by causing the capacitance electrodes 37a and 38a provided for forming the coupling capacitance to function as electrodes for forming the storage capacitance.
- the capacitor electrodes 37a and 38a have a shape extending in the row direction and are arranged in the row direction so as to overlap with the storage capacitor wire 18p, the line width of the storage capacitor wire 18p can be reduced. Thereby, an aperture ratio can be raised further.
- the storage capacitor Chb may be formed by the configuration shown in FIG. That is, as shown in FIG. 25, the storage capacitor electrode 39b formed in the same layer as the capacitor electrodes 37a and 38a is connected to the pixel electrode 17b through the contact hole 69b, whereby the storage capacitor electrode 39b and the storage capacitor A storage capacitor Chb is formed between the wiring 18p.
- the insulating film interposed therebetween can be reduced (thin). , You can earn a retention capacity value.
- the insulating film forming the storage capacitor Chb can be made thin, the width of the storage capacitor wiring 18p can be narrowed without changing the size of the storage capacitor value, and the aperture ratio can be improved without degrading the reliability. The effect that it can plan is also acquired.
- one of the two pixel electrodes provided in one pixel surrounds the other, and the surrounding pixel electrode is connected to the transistor, but the present invention is not limited to this.
- one of two pixel electrodes provided in one pixel surrounds the other, and the surrounded pixel electrode can be connected to a transistor.
- FIG. 27 shows a specific example of the pixel 101 in FIG.
- the shape and arrangement of the pixel electrodes 17a and 17b and the storage capacitor wiring 18p are the same as those in FIG.
- the capacitive electrodes 37b and 38b are arranged so as to overlap the second gap K2, the pixel electrode 17a, and the pixel electrode 17b.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the pixel electrode 17b through the drain lead line 27a and the contact hole 11b.
- the capacitor electrode 37b is connected to the pixel electrode 17b through the contact hole 67b, and a part of the capacitor electrode 37b overlaps with the pixel electrode 17a through the interlayer insulating film, and the coupling capacitor Cab1 (see FIG. 26) is overlapped with both of them. ) Is formed.
- the capacitor electrode 38b is connected to the pixel electrode 17b through the contact hole 68b, and a part of the capacitor electrode 38b overlaps the pixel electrode 17a through the interlayer insulating film, and the coupling capacitor Cab2 (see FIG. 26) is formed.
- a part of the pixel electrode 17a overlaps with the storage capacitor wiring 18p via the gate insulating film and the interlayer insulating film, and the storage capacitor Cha (see FIG. 26) is formed in the overlapping portion between them.
- a part of the pixel electrode 17b overlaps with the storage capacitor wiring 18p via the gate insulating film and the interlayer insulating film, and a storage capacitor Chb (see FIG. 26) is formed in the overlapping portion of both.
- the sub-pixel including the pixel electrode 17a is “dark”, and the sub-pixel including the pixel electrode 17b is “bright”.
- the capacitor electrode 37b and the pixel electrode 17a are connected (capacitively coupled) by two parallel coupling capacitors (Cab1 and Cab2), for example, the capacitor electrode 37b and the pixel electrode 17a are connected to each other. If the capacitor electrode 37b is short-circuited (in the manufacturing process or the like), the capacitive coupling of the pixel electrodes 17a and 17b is maintained by performing a correction process in which the capacitor electrode 37b is laser-cut between the contact hole 67b and the short-circuited portion. be able to. Furthermore, even when the contact hole 67b is poorly formed in the manufacturing process or the like, the capacitive coupling of the pixel electrodes 17a and 17b can be maintained. Note that when the capacitor electrode 38b and the pixel electrode 17a are short-circuited, the capacitor electrode 38b may be laser-cut between the contact hole 68b and the short-circuited portion.
- the capacitive electrode 37b is irradiated with a laser from the front surface (opposite side of the glass substrate) of the active matrix substrate through the second gap K2 to cut it.
- the capacitive electrode 37b is irradiated with a laser from the front surface (opposite side of the glass substrate) of the active matrix substrate through the second gap K2 to cut it.
- the capacitor electrode is electrically connected to the pixel electrode corresponding to the sub-pixel that becomes the bright sub-pixel, but the present invention is not limited to this.
- the present liquid crystal panel may have a configuration in which the capacitor electrode is electrically connected to the pixel electrode corresponding to the sub-pixel serving as the dark sub-pixel.
- a specific example 101 of the pixel in FIG. 28 is shown in FIG.
- the transistor 12a is arranged near the intersection of the data signal line 15x and the scanning signal line 16x, and the pixel region defined by both signal lines (15x ⁇ 16x) is arranged.
- a pixel electrode 17b having a trapezoidal shape when viewed in the row direction and a pixel electrode 17a surrounding the pixel electrode 17b are arranged, and a storage capacitor wiring 18p extends in the row direction across the center of the pixel.
- the capacitor electrode 37b has a shape extending in the row direction so as to intersect the first gap K1
- the capacitor electrode 38b has a shape extending in the row direction so as to intersect the second gap K2. They are arranged in the row direction so as to overlap the storage capacitor wiring 18p.
- the capacitance electrodes 37b and 38b are arranged so as to substantially coincide with the capacitance electrode 38b when the capacitance electrode 37b is rotated by 180 ° around the point on the storage capacitance wiring 18p in the pixel 101. That is, the capacitive electrodes 37b and 38b are line symmetric with respect to a line parallel to the first gap K1 and the second gap K2 and passing through the center of both gaps.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- the capacitor electrode 37b is connected to the pixel electrode 17b through the contact hole 67b and overlaps with the pixel electrode 17a through an interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab1 (see FIG. 28) is formed.
- the capacitor electrode 38b is connected to the pixel electrode 17b through the contact hole 68b and overlaps the pixel electrode 17a through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab2 (see FIG. 28) is formed.
- the capacitor electrode 37b overlaps the storage capacitor wiring 18p via the gate insulating film, and a large part of the storage capacitor Chb1 (see FIG. 28) is formed in the overlapping portion between them, and the capacitor electrode 38b passes through the gate insulating film. It overlaps with the storage capacitor line 18p, and most of the storage capacitor Chb2 (see FIG. 28) is formed in the overlapping portion between them.
- the pixel electrode 17a and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and the storage capacitor Cha (see FIG. 28) is formed in the overlapping portion between them.
- the sub-pixel including the pixel electrode 17a is “bright”, and the sub-pixel including the pixel electrode 17b is “dark”.
- the pixel electrode 17a and the pixel electrode 17b are connected (capacitively coupled) by two parallel coupling capacitors (Cab1 and Cab2).
- the pixel electrode 17a and the pixel electrode 17a are short-circuited (in a manufacturing process or the like)
- the pixel electrode 17a or 17b is subjected to a correction process in which the capacitor electrode 37b is laser-cut between the contact hole 67b and the short-circuited portion.
- the capacitive coupling can be maintained.
- the capacitor electrode 38b and the pixel electrode 17a are short-circuited, the capacitor electrode 38b may be laser-cut between the contact hole 68b and the short-circuited portion.
- the capacitor electrodes 37b and 38b are arranged side by side in the extending direction (row direction) of the storage capacitor wiring 18p so as to overlap the storage capacitor wiring 18p.
- 37b and 38b are axisymmetric with respect to a line parallel to the first gap K1 and the second gap K2 and passing through the centers of both gaps.
- the thick organic gate insulating film 21 and the thin inorganic gate insulating film 22 are formed on the glass substrate 31 as in the liquid crystal panel according to the first embodiment (see FIG. 4). Then, a thin inorganic interlayer insulating film 25 and a thick organic interlayer insulating film 26 may be formed under the pixel electrode. In this way, effects such as reduction of various parasitic capacitances, prevention of short-circuiting between wirings, and reduction of pixel electrode tearing due to planarization can be obtained. In this case, for example, in the region indicated by the dotted line in FIG. 30, as shown in FIG.
- the organic gate insulating film 21 pierces the portion located below the capacitance electrodes 37 a and 38 a, About the insulating film 26, it is preferable to penetrate the part located on the capacitive electrodes 37a and 38a. By doing so, the above-described effects can be obtained while sufficiently securing the capacitance value of the coupling capacitance (Cab1 ⁇ Cab2) and the capacitance value of the holding capacitance (Cha1 ⁇ Cha2 ⁇ Chb).
- the penetration portion (thin film portion 51a) of the organic interlayer insulating film 26 in FIG. 30 is formed in a rectangular shape by the first side (J1) to the fourth side (J4), and the capacitance Since the electrode 37a straddles the first side (J1) and the capacitor electrode 38a arranged side by side in the row direction with the capacitor electrode 37a straddles the third side (J3) facing the first side (J1), the capacitance Even when the electrodes 37a and 38a are displaced in the row direction, the overlapping area of the capacitive electrode 37a and the pixel electrode 17b and the overlapping area of the capacitive electrode 38a and the pixel electrode 17b compensate each other, so that two capacitances (coupling capacitances) are obtained. The effect is that the total amount of is hard to change.
- the thin film portion 51a of FIG. 30 may be formed in the region of the pixel electrode 17b so as to overlap only the pixel electrode 17b. That is, the first side (J1) to the fourth side (J4) forming the rectangular thin film portion 51a are configured to be located in the region of the pixel electrode 17b. Thereby, in addition to the effect obtained by the configuration shown in FIG. 30 (the total amount of the two capacitors is difficult to change), the overlapping area between the capacitor electrodes 37a and 38a and the pixel electrode 17b is reduced. The effect that the possibility of a short circuit between 38a and the pixel electrode 17b can be reduced is obtained.
- FIG. 31 is an equivalent circuit diagram showing a part of the liquid crystal panel according to the third embodiment.
- data signal lines (15x / 15y) extending in the column direction (vertical direction in the figure) and scanning signal lines (16x / 16y) extending in the row direction (horizontal direction in the figure).
- Pixels (101 to 104) arranged in the row and column directions, storage capacitor wiring (18p to 18s), and common electrode (counter electrode) com, and the structure of each pixel is the same.
- the pixel column including the pixels 101 and 102 and the pixel column including the pixels 103 and 104 are adjacent to each other, and the pixel row including the pixels 101 and 103 and the pixel row including the pixels 102 and 104 are adjacent to each other. is doing.
- one data signal line, one scanning signal line, and two storage capacitor lines are provided corresponding to one pixel.
- Each pixel is provided with three pixel electrodes
- the pixel 101 is provided with pixel electrodes 17a, 17b, and 17a '
- the pixel 102 is provided with pixel electrodes 17c, 17d, and 17c'.
- the pixel 103 is provided with pixel electrodes 17A, 17B, and 17A '
- the pixel 104 is provided with pixel electrodes 17C, 17D, and 17C'.
- FIG. 32 shows a specific example of the pixel 101 in FIG.
- a transistor 12a is arranged near the intersection of the data signal line 15x and the scanning signal line 16x, and a pixel electrode having a trapezoidal shape is formed in a pixel region defined by both signal lines (15x and 16x).
- 17a a pixel electrode 17a ′ having a trapezoidal shape substantially coincident with the shape of the pixel electrode 17a rotated by 180 ° at a position of approximately 315 ° with respect to the row direction of the storage capacitor wiring 18p, and the pixel electrodes 17a.
- the pixel electrode 17b is arranged so as to correspond to (engage with) the shape of the pixel electrodes 17a and 17a ′.
- the storage capacitor lines 18p and 18r are arranged in parallel to each other, the storage capacitor line 18p extends in the row direction across the pixel electrodes 17a and 17b, and the storage capacitor line 18r crosses the pixel electrodes 17b and 17a ′ in the row direction. Is stretched.
- each of the pixel electrodes 17a, 17b, and 17a ′ has a part of the pixel electrode 17a close to the scanning signal line 16x and a part of the pixel electrode 17a ′ close to the scanning signal line 16y.
- One end of the pixel electrode 17b is disposed close to the scanning signal line 16x, and the other end is disposed close to the scanning signal line 16y.
- at least a part of each of the pixel electrodes 17a and 17a ′ is arranged in proximity to each of the scanning signal lines 16x and 16y, and the pixel electrode 17b connects the scanning signal lines 16x and 16y. It extends in the row direction.
- the capacitor electrode 37a is disposed so as to overlap the storage capacitor line 18p and the pixel electrodes 17a and 17b
- the capacitor electrode 38a is disposed so as to overlap the storage capacitor line 18r and the pixel electrodes 17b and 17a ′.
- the capacitor electrode 37a extends in the same direction as the extending direction of the storage capacitor line 18p and overlaps the storage capacitor line 18p and the pixel electrodes 17a and 17b.
- the capacitor electrode 38a has a shape substantially coincident with the shape of the capacitor electrode 37a rotated by 180 °, is arranged in parallel with the capacitor electrode 37a, extends in the same direction as the extension direction of the storage capacitor wiring 18r, and holds it. It overlaps with the capacitor wiring 18r and the pixel electrodes 17b and 17a '.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- a relay wiring 110a is connected to the pixel electrode 17a through a contact hole 111a, and the relay wiring 110a is connected to the pixel electrode 17a ′ through a contact hole 112a.
- the capacitor electrode 37a is connected to the pixel electrode 17a through the contact hole 67a and overlaps with the pixel electrode 17b through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab1 (see FIG. 31) is formed.
- the capacitor electrode 38a is connected to the pixel electrode 17a 'via the contact hole 68a and overlaps the pixel electrode 17b via the interlayer insulating film, and the overlap between the two is provided between the pixel electrodes 17a' and 17b.
- a coupling capacitor Cab2 (see FIG. 31) is formed.
- the capacitor electrode 37a overlaps the storage capacitor wiring 18p via the gate insulating film, and a large part of the storage capacitor Cha1 (see FIG. 31) is formed in the overlapping portion between them, and the capacitor electrode 38a passes through the gate insulating film. It overlaps with the storage capacitor wiring 18r, and many of the storage capacitors Cha2 (see FIG. 31) are formed in the overlapping portion between them.
- the pixel electrode 17b and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a large part of the storage capacitor Chb1 (see FIG. 31) is formed in the overlapping portion between the pixel electrode 17b and the storage electrode.
- the capacitor wiring 18r overlaps with the interlayer insulating film and the gate insulating film, and the storage capacitor Chb2 (see FIG. 31) is formed in the overlapping portion between the two.
- the sub-pixel including the pixel electrodes 17a and 17a ′ is “bright”, and the sub-pixel including the pixel electrode 17b is “dark”.
- the pixel electrodes 17a and 17a ′ and the pixel electrode 17b are connected (capacitively coupled) by two coupling capacitors (Cab1 and Cab2) in parallel.
- the capacitor electrode 37a and the pixel electrode 17b are short-circuited (in a manufacturing process or the like)
- the pixel electrode is obtained by performing a correction process in which the capacitor electrode 37a is laser-cut between the contact hole 67a and the short-circuited portion.
- Capacitive coupling of 17a, 17b, and 17a ' can be maintained.
- the capacitive coupling of the pixel electrodes 17a, 17b, and 17a ′ can be maintained.
- the capacitor electrode 38a and the pixel electrode 17b are short-circuited
- the capacitor electrode 38a may be laser-cut between the contact hole 68a and the short-circuited portion.
- the capacitor electrode 37a extends in the same direction as the extending direction of the storage capacitor line 18p, overlaps the storage capacitor line 18p and the pixel electrodes 17a and 17b, and the capacitor electrode 38a includes the capacitor electrode 37a. Is formed in the same direction as that of the storage capacitor line 18r and overlaps with the storage capacitor line 18r and the pixel electrodes 17b and 17a '.
- the capacitor electrode 37a overlaps the pixel electrode 17b and the storage capacitor line 18p, and the capacitor electrode 38a overlaps the pixel electrode 17b ′ and the storage capacitor line 18r.
- the aperture ratio can be increased by causing the capacitance electrodes 37a and 38a provided for forming the coupling capacitance to function as electrodes for forming the storage capacitance.
- the capacitor electrodes 37a and 38a have a shape extending in the row direction and are arranged so as to overlap the storage capacitor wires 18p and 18r, the line width of the storage capacitor wires 18p and 18r can be reduced. . Thereby, an aperture ratio can be raised further.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- One end of the capacitance electrode 37a is connected to the pixel electrode 17a via the contact hole 67a, and the other end is connected to the pixel electrode 17a 'via the contact hole 112a. Further, the capacitor electrode 37a overlaps the pixel electrode 17b through an interlayer insulating film, and coupling capacitances Cab1 and Cab2 (see FIG.
- the capacitor electrode 38a has one end connected to the pixel electrode 17a through the contact hole 111a and the other end connected to the pixel electrode 17a 'through the contact hole 68a. Further, the capacitor electrode 38a overlaps the pixel electrode 17b through an interlayer insulating film, and coupling capacitances Cab1 and Cab2 (see FIG. 31) between the pixel electrodes 17a and 17a ′ and 17b are formed in the overlapping portion of both. . Further, the capacitor electrode 37a overlaps the storage capacitor wiring 18p via the gate insulating film, and a large part of the storage capacitor Cha1 (see FIG.
- the capacitor electrode 38a passes through the gate insulating film. It overlaps with the storage capacitor wiring 18r, and many storage capacitors Cha2 (see FIG. 31) are formed in the overlapping portion between them.
- the pixel electrode 17b and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a large part of the storage capacitor Chb1 (see FIG. 31) is formed in the overlapping portion between the pixel electrode 17b and the storage electrode.
- the capacitor wiring 18r overlaps with the interlayer insulating film and the gate insulating film, and the storage capacitor Chb2 (see FIG. 31) is formed in the overlapping portion between the two.
- the pixel electrodes 17a and 17a ′ of FIG. 32 are connected to each other through a connection portion 17aa made of ITO or the like in the outer peripheral region of the pixel electrode 17b. That is, the pixel electrode integrally formed by the pixel electrodes 17a and 17a 'is provided so as to surround the pixel electrode 17b. This eliminates the need for the contact holes 111a and 112a and the relay wiring 110a for connecting the pixel electrodes 17a and 17a 'shown in FIG. 32, thereby increasing the aperture ratio.
- the pixel electrodes 17a and 17a 'surround the pixel electrode 17b that is electrically floating the pixel electrodes 17a and 17a' function as a shield electrode, thereby suppressing the jumping of charges into the pixel electrode 17b. Can do. Thereby, the burn-in of the sub-pixel (dark sub-pixel) including the pixel electrode 17b can be suppressed.
- the capacitor electrode is configured to be electrically connected to the pixel electrode corresponding to the sub-pixel serving as the bright sub-pixel, but is not limited thereto.
- the liquid crystal panel may have a configuration in which the capacitor electrode is electrically connected to a pixel electrode corresponding to a sub-pixel that is a dark sub-pixel.
- a specific example 101 of the pixel having this configuration is shown in FIG.
- a transistor 12a is disposed in the vicinity of the intersection of the data signal line 15x and the scanning signal line 16x, and a pixel electrode 17a having a trapezoidal shape is formed in a pixel region defined by both signal lines (15x and 16x).
- a pixel electrode 17a ′ having a trapezoidal shape substantially coincident with the shape of the pixel electrode 17a rotated by 180 ° at a position of approximately 315 ° with respect to the row direction of the storage capacitor wiring 18p, and these pixel electrodes 17a and 17a
- the pixel electrode 17b is arranged so as to correspond to (engage with) the shape of the pixel electrodes 17a and 17a'.
- the storage capacitor lines 18p and 18r are arranged in parallel to each other, the storage capacitor line 18p extends in the row direction across the pixel electrodes 17a and 17b, and the storage capacitor line 18r crosses the pixel electrodes 17b and 17a ′ in the row direction. Is stretched.
- each of the pixel electrodes 17a, 17b, and 17a ′ has a part of the pixel electrode 17a close to the scanning signal line 16x and a part of the pixel electrode 17a ′ close to the scanning signal line 16y.
- One end of the pixel electrode 17b is disposed close to the scanning signal line 16x, and the other end is disposed close to the scanning signal line 16y.
- at least a part of each of the pixel electrodes 17a and 17a ′ is arranged in proximity to each of the scanning signal lines 16x and 16y, and the pixel electrode 17b connects the scanning signal lines 16x and 16y. It extends in the row direction.
- the capacitor electrode 37b is disposed so as to overlap the storage capacitor line 18p and the pixel electrodes 17a and 17b, and the capacitor electrode 38b is disposed so as to overlap the storage capacitor line 18r and the pixel electrodes 17b and 17a ′. More specifically, the capacitor electrode 37b extends in the same direction as the storage capacitor wiring 18p and overlaps the storage capacitor wiring 18p and the pixel electrodes 17a and 17b.
- the capacitor electrode 38b has a shape substantially coinciding with the shape of the capacitor electrode 37b rotated by 180 °, is arranged in parallel with the capacitor electrode 37b, extends in the same direction as the extending direction of the storage capacitor wiring 18r, and holds it. It overlaps with the capacitor wiring 18r and the pixel electrodes 17b and 17a '.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- a relay wiring 110a is connected to the pixel electrode 17a through a contact hole 111a, and the relay wiring 110a is connected to the pixel electrode 17a ′ through a contact hole 112a.
- the capacitor electrode 37b is connected to the pixel electrode 17b through the contact hole 67b and overlaps the pixel electrode 17a through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab1 (see FIG. 31) is formed.
- the capacitor electrode 38b is connected to the pixel electrode 17b through the contact hole 68b and overlaps with the pixel electrode 17a 'through the interlayer insulating film, and the overlap between the two is provided between the pixel electrodes 17a' and 17b.
- a coupling capacitor Cab2 (see FIG. 31) is formed.
- the capacitor electrode 37b overlaps the storage capacitor wiring 18p through the gate insulating film, and a large part of the storage capacitor Chb1 (see FIG. 31) is formed in the overlapping portion between them, and the capacitor electrode 38b passes through the gate insulating film. It overlaps with the storage capacitor wiring 18r, and many of the storage capacitors Chb2 (see FIG. 31) are formed in the overlapping portion between them. Further, the pixel electrode 17a and the storage capacitor line 18p are overlapped with each other via the interlayer insulating film and the gate insulating film, and a storage capacitor Cha1 (see FIG. 31) is formed at the overlapping portion between the pixel electrode 17a and the storage electrode 18a ′. The capacitor wiring 18r overlaps with the interlayer insulating film and the gate insulating film, and the storage capacitor Cha2 (see FIG. 31) is formed in the overlapping portion between the two.
- the sub-pixel including the pixel electrodes 17a and 17a ′ is “bright”, and the sub-pixel including the pixel electrode 17b is “dark”.
- the pixel electrode 17a and the pixel electrode 17b are connected (capacitively coupled) by two parallel coupling capacitors (Cab1 and Cab2).
- the pixel electrode 17a and the pixel electrode 17a are short-circuited (in a manufacturing process or the like)
- the pixel electrode 17a or 17b is subjected to a correction process in which the capacitor electrode 37b is laser-cut between the contact hole 67b and the short-circuited portion. 17a 'capacitive coupling can be maintained.
- the capacitor electrode 38b and the pixel electrode 17a ′ are short-circuited, the capacitor electrode 38b may be laser-cut between the contact hole 68b and the short-circuited portion.
- FIG. 36 is an equivalent circuit diagram showing a part of the liquid crystal panel according to the fourth embodiment.
- data signal lines (15x ⁇ 15y) extending in the column direction (up and down direction in the figure) and scanning signal lines (16x and 16y) extending in the row direction (left and right direction in the figure).
- Pixels (101 to 104) arranged in the row and column directions, storage capacitor wiring (18p to 18s), and common electrode (counter electrode) com, and the structure of each pixel is the same.
- the pixel column including the pixels 101 and 102 and the pixel column including the pixels 103 and 104 are adjacent to each other, and the pixel row including the pixels 101 and 103 and the pixel row including the pixels 102 and 104 are adjacent to each other. is doing.
- one data signal line, one scanning signal line, and two storage capacitor lines are provided corresponding to one pixel.
- Each pixel is provided with three pixel electrodes
- the pixel 101 is provided with pixel electrodes 17b, 17a, and 17b '
- the pixel 102 is provided with pixel electrodes 17d, 17c, and 17d'.
- the pixel 103 is provided with pixel electrodes 17B, 17A, and 17B '
- the pixel 104 is provided with pixel electrodes 17D, 17C, and 17D'.
- FIG. 37 shows a specific example of the pixel 101 in FIG.
- a transistor 12a is arranged near the intersection of the data signal line 15x and the scanning signal line 16x, and a pixel electrode having a trapezoidal shape is formed in a pixel region defined by both signal lines (15x and 16x).
- 17b a pixel electrode 17b ′ having a trapezoidal shape substantially coincident with the shape of the pixel electrode 17b rotated by 180 ° at a position of approximately 315 ° with respect to the row direction of the storage capacitor wiring 18p
- the pixel electrode 17a is arranged so as to correspond to (engage with) the shape of the pixel electrodes 17b and 17b'.
- the storage capacitor lines 18p and 18r are arranged in parallel to each other, the storage capacitor line 18p extends in the row direction across the pixel electrodes 17a and 17b, and the storage capacitor line 18r crosses the pixel electrodes 17a and 17b 'in the row direction. Is stretched.
- each of the pixel electrodes 17b, 17a, and 17b ′ has a part of the pixel electrode 17b close to the scanning signal line 16x, and a part of the pixel electrode 17b ′ close to the scanning signal line 16y.
- One end of the pixel electrode 17a is disposed close to the scanning signal line 16x, and the other end is disposed close to the scanning signal line 16y.
- at least a part of each of the pixel electrodes 17b and 17b ′ is disposed in proximity to the scanning signal lines 16x and 16y, and the pixel electrode 17a connects the scanning signal lines 16x and 16y. It extends in the row direction.
- the capacitor electrode 37a is disposed so as to overlap the storage capacitor line 18p and the pixel electrodes 17a and 17b, and the capacitor electrode 38a is disposed so as to overlap the storage capacitor line 18r and the pixel electrodes 17a and 17b ′. More specifically, the capacitor electrode 37a extends in the same direction as the extending direction of the storage capacitor line 18p and overlaps the storage capacitor line 18p and the pixel electrodes 17a and 17b.
- the capacitor electrode 38a has a shape substantially coincident with the shape of the capacitor electrode 37a rotated by 180 °, is arranged in parallel with the capacitor electrode 37a, extends in the same direction as the extension direction of the storage capacitor wiring 18r, and holds it. It overlaps with the capacitor wiring 18r and the pixel electrodes 17a and 17b '.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- the capacitor electrode 37a is connected to the pixel electrode 17a through the contact hole 67a and overlaps with the pixel electrode 17b through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab1 (see FIG. 36) is formed.
- the capacitor electrode 38a is connected to the pixel electrode 17a through the contact hole 68a and overlaps with the pixel electrode 17b 'through the interlayer insulating film, and the overlap between the two is provided between the pixel electrodes 17a and 17b'.
- a coupling capacitor Cab2 (see FIG. 36) is formed.
- the capacitor electrode 37a overlaps the storage capacitor wiring 18p through the gate insulating film, and a large part of the storage capacitor Cha1 (see FIG. 36) is formed in the overlapping portion between them, and the capacitor electrode 38a passes through the gate insulating film. It overlaps with the storage capacitor wiring 18r, and most of the storage capacitor Cha2 (see FIG. 36) is formed in the overlapping portion between them.
- the pixel electrode 17b and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and a storage capacitor Chb1 (see FIG. 36) is formed at the overlapping portion between the pixel electrode 17b and the storage capacitor.
- the wiring 18r overlaps with the interlayer insulating film and the gate insulating film, and the storage capacitor Chb2 (see FIG. 36) is formed in the overlapping portion of both.
- the subpixel including the pixel electrode 17a is “bright”, and the subpixel including the pixel electrodes 17b and 17b ′ is “dark”.
- the pixel electrode 17a and the pixel electrodes 17b and 17b ′ are connected (capacitively coupled) by two coupling capacitors (Cab1 and Cab2) in parallel.
- the capacitor electrode 37a and the pixel electrode 17b are short-circuited (in a manufacturing process or the like)
- the pixel electrode is obtained by performing a correction process in which the capacitor electrode 37a is laser-cut between the contact hole 67a and the short-circuited portion.
- Capacitive coupling of 17b, 17a, and 17b ' can be maintained.
- the capacitive coupling of the pixel electrodes 17b, 17a, and 17b ′ can be maintained.
- the capacitor electrode 38a and the pixel electrode 17b 'are short-circuited the capacitor electrode 38a may be laser-cut between the contact hole 68a and the short-circuited portion.
- the capacitor electrode 37a extends in the same direction as the extending direction of the storage capacitor line 18p, overlaps the storage capacitor line 18p and the pixel electrodes 17a and 17b, and the capacitor electrode 38a includes the capacitor electrode 37a. Is formed in the same direction as the extending direction of the storage capacitor line 18r and overlaps the storage capacitor line 18r and the pixel electrodes 17a and 17b '.
- the capacitor electrode 37a overlaps the pixel electrode 17b and the storage capacitor line 18p, and the capacitor electrode 38a overlaps the pixel electrode 17b ′ and the storage capacitor line 18r.
- the aperture ratio can be increased by causing the capacitance electrodes 37a and 38a provided for forming the coupling capacitance to function as electrodes for forming the storage capacitance.
- the capacitor electrodes 37a and 38a have a shape extending in the row direction and are arranged so as to overlap the storage capacitor wires 18p and 18r, the line width of the storage capacitor wires 18p and 18r can be reduced. . Thereby, an aperture ratio can be raised further.
- the holding capacitors Chb1 and Chb2 may be formed by the configuration shown in FIG. That is, as shown in FIG. 38, the storage capacitor electrode 39b formed in the same layer as the capacitor electrode 37a is connected to the pixel electrode 17b through the contact hole 69b, whereby the storage capacitor electrode 39b and the storage capacitor wire 18p are connected.
- the storage capacitor Chb1 is formed between the storage capacitor electrode 39b and the storage capacitor electrode 39b 'formed in the same layer as the capacitor electrode 38a is connected to the pixel electrode 17b' via the contact hole 69b ', whereby the storage capacitor electrode 39b A storage capacitor Chb2 is formed between 'and the storage capacitor line 18r.
- the storage capacitors Chb1 and Chb2 are formed between the pixel electrodes 17b and 17 'and the storage capacitor wirings 18p and 18r as shown in FIG. Can be reduced (thin), so that the retention capacity value can be earned.
- the insulating film for forming the storage capacitors Chb1 and Chb2 can be made thin, the width of the storage capacitor wirings 18p and 18r can be reduced without changing the size of the storage capacitor value, and the opening can be opened without reducing the reliability. The effect that the rate can be improved is also obtained.
- the capacitor electrode is configured to be electrically connected to the pixel electrode corresponding to the sub-pixel serving as the bright sub-pixel, but is not limited thereto.
- the liquid crystal panel may have a configuration in which the capacitor electrode is electrically connected to a pixel electrode corresponding to a sub-pixel that is a dark sub-pixel.
- a specific example 101 of the pixel having this configuration is shown in FIG.
- a transistor 12a is disposed in the vicinity of the intersection of the data signal line 15x and the scanning signal line 16x, and a trapezoidal pixel electrode 17b is formed in a pixel region defined by both signal lines (15x and 16x).
- a pixel electrode 17b ′ having a trapezoidal shape substantially coincident with the shape of the pixel electrode 17b rotated by 180 ° at a position of approximately 315 ° with respect to the row direction of the storage capacitor wiring 18p, and these pixel electrodes 17b and 17b In the region excluding ', the pixel electrode 17a is arranged so as to correspond to (engage with) the shape of the pixel electrodes 17b and 17b'.
- the storage capacitor lines 18p and 18r are arranged in parallel to each other, the storage capacitor line 18p extends in the row direction across the pixel electrodes 17a and 17b, and the storage capacitor line 18r crosses the pixel electrodes 17a and 17b 'in the row direction. Is stretched.
- each of the pixel electrodes 17b, 17a, and 17b ′ has a part of the pixel electrode 17b close to the scanning signal line 16x, and a part of the pixel electrode 17b ′ close to the scanning signal line 16y.
- One end of the pixel electrode 17a is disposed close to the scanning signal line 16x, and the other end is disposed close to the scanning signal line 16y.
- at least a part of each of the pixel electrodes 17b and 17b ′ is disposed in proximity to the scanning signal lines 16x and 16y, and the pixel electrode 17a connects the scanning signal lines 16x and 16y. It extends in the row direction.
- the capacitor electrode 37b is disposed so as to overlap the storage capacitor line 18p and the pixel electrodes 17a and 17b, and the capacitor electrode 38b is disposed so as to overlap the storage capacitor line 18r and the pixel electrodes 17a and 17b ′. More specifically, the capacitor electrode 37b extends in the same direction as the storage capacitor wiring 18p and overlaps the storage capacitor wiring 18p and the pixel electrodes 17a and 17b.
- the capacitor electrode 38b has a shape substantially coinciding with the shape of the capacitor electrode 37b rotated by 180 °, is arranged in parallel with the capacitor electrode 37b, extends in the same direction as the extending direction of the storage capacitor wiring 18r, and holds it. It overlaps with the capacitor wiring 18r and the pixel electrodes 17a and 17b '.
- the source electrode 8a and the drain electrode 9a of the transistor 12a are formed on the scanning signal line 16x, and the source electrode 8a is connected to the data signal line 15x.
- the drain electrode 9a is connected to the drain lead wiring 27a, and the drain lead wiring 27a is connected to the pixel electrode 17a through the contact hole 11a.
- the capacitor electrode 37b is connected to the pixel electrode 17b through the contact hole 67b and overlaps the pixel electrode 17a through the interlayer insulating film, and the coupling capacitance between the pixel electrodes 17a and 17b is overlapped with both of them.
- Cab1 (see FIG. 36) is formed.
- the capacitor electrode 38b is connected to the pixel electrode 17b 'via the contact hole 68b and overlaps with the pixel electrode 17a via an interlayer insulating film, and the overlap between the two is provided between the pixel electrodes 17a and 17b'.
- a coupling capacitor Cab2 (see FIG. 36) is formed.
- the capacitor electrode 37b overlaps the storage capacitor wiring 18p via the gate insulating film, and a large part of the storage capacitor Chb1 (see FIG. 36) is formed in the overlapping portion between them, and the capacitor electrode 38b passes through the gate insulating film. It overlaps with the storage capacitor wiring 18r, and most of the storage capacitor Chb2 (see FIG. 36) is formed in the overlapping portion between them.
- the pixel electrode 17a and the storage capacitor line 18p overlap with each other via the interlayer insulating film and the gate insulating film, and the storage capacitor Cha1 (see FIG. 36) is formed in the overlapping portion between the pixel electrode 17a and the storage capacitor.
- the wiring 18r overlaps with the interlayer insulating film and the gate insulating film, and the storage capacitor Cha2 (see FIG. 36) is formed in the overlapping portion of both.
- the subpixel including the pixel electrode 17a is “bright” and the subpixel including the pixel electrodes 17b and 17b ′ is “dark”.
- the pixel electrode 17a and the pixel electrodes 17b and 17b ′ are connected (capacitively coupled) by two coupling capacitors (Cab1 and Cab2) in parallel.
- the capacitor electrode 37b and the pixel electrode 17a are short-circuited (in the manufacturing process or the like)
- the pixel electrode 17b is subjected to a correction process in which the capacitor electrode 37b is laser-cut between the contact hole 67b and the short-circuited portion. • Capacitive coupling of 17a and 17b ′ can be maintained.
- the capacitor electrode 38b and the pixel electrode 17a are short-circuited, the capacitor electrode 38b may be laser-cut between the contact hole 68b and the short-circuited portion.
- the present liquid crystal display unit and the liquid crystal display device are configured as follows. That is, the two polarizing plates A and B are attached to both surfaces of the liquid crystal panel so that the polarizing axis of the polarizing plate A and the polarizing axis of the polarizing plate B are orthogonal to each other. In addition, you may laminate
- drivers gate driver 202, source driver 201 are connected.
- TCP Tape career Package
- ACF Anisotropic Conductive ⁇ Film
- the TCP on which the driver is placed is punched out of the carrier tape, aligned with the panel terminal electrode, and heated and pressed.
- a circuit board 203 PWB: Printed Wiring Board
- the liquid crystal display unit 200 is completed.
- a display control circuit 209 is connected to each driver (201, 202) of the liquid crystal display unit via the circuit board 203, and integrated with the lighting device (backlight unit) 204. As a result, the liquid crystal display device 210 is obtained.
- the “polarity of the potential” in the present application means a potential not less than a reference potential (plus) or not more than a reference potential (minus).
- the reference potential may be Vcom (common potential) which is the potential of the common electrode (counter electrode) or any other potential.
- FIG. 41 is a block diagram showing a configuration of the present liquid crystal display device.
- the liquid crystal display device includes a display unit (liquid crystal panel), a source driver (SD), a gate driver (GD), and a display control circuit.
- the source driver drives the data signal line
- the gate driver drives the scanning signal line
- the display control circuit controls the source driver and the gate driver.
- the display control circuit controls a display operation from a digital video signal Dv representing an image to be displayed, a horizontal synchronization signal HSY and a vertical synchronization signal VSY corresponding to the digital video signal Dv from an external signal source (for example, a tuner). For receiving the control signal Dc. Further, the display control circuit, based on the received signals Dv, HSY, VSY, and Dc, uses a data start pulse signal SSP and a data clock as signals for displaying an image represented by the digital video signal Dv on the display unit.
- GOE scanning signal output control signal
- the video signal Dv is output as a digital image signal DA from the display control circuit, and a pulse corresponding to each pixel of the image represented by the digital image signal DA.
- a data clock signal SCK is generated as a signal consisting of the above, a data start pulse signal SSP is generated as a signal that becomes high level (H level) for a predetermined period every horizontal scanning period based on the horizontal synchronization signal HSY, and the vertical synchronization signal VSY
- the gate start pulse signal GSP is generated as a signal that becomes H level only for a predetermined period every one frame period (one vertical scanning period)
- the gate clock signal GCK is generated based on the horizontal synchronization signal HSY, and the horizontal synchronization signal HSY and Based on the control signal Dc, the charge share signal sh and the gate dry Generating an output control signal GOE.
- the digital image signal DA the charge share signal sh, the signal POL for controlling the polarity of the signal potential (data signal potential), the data start pulse signal SSP, and the data clock
- the signal SCK is input to the source driver, and the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE are input to the gate driver.
- the source driver corresponds to the pixel value in each scanning signal line of the image represented by the digital image signal DA based on the digital image signal DA, the data clock signal SCK, the charge share signal sh, the data start pulse signal SSP, and the polarity inversion signal POL.
- the analog potential (signal potential) to be generated is sequentially generated every horizontal scanning period, and these data signals are output to the data signal lines (for example, 15x and 15X).
- the gate driver generates a gate-on pulse signal based on the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE, and outputs them to the scanning signal line, thereby selecting the scanning signal line. Drive.
- the data signal line and the scanning signal line of the display unit are driven by the source driver and the gate driver, so that the data is transmitted through the transistor (TFT) connected to the selected scanning signal line.
- TFT transistor
- a signal potential is written from the signal line to the pixel electrode.
- a voltage is applied to the liquid crystal layer of each subpixel, whereby the amount of light transmitted from the backlight is controlled, and an image indicated by the digital video signal Dv is displayed on each subpixel.
- FIG. 42 is a block diagram showing a configuration of a liquid crystal display device 800 for a television receiver.
- the liquid crystal display device 800 includes a liquid crystal display unit 84, a Y / C separation circuit 80, a video chroma circuit 81, an A / D converter 82, a liquid crystal controller 83, a backlight drive circuit 85, a backlight 86, A microcomputer 87 and a gradation circuit 88 are provided.
- the liquid crystal display unit 84 includes a liquid crystal panel and a source driver and a gate driver for driving the liquid crystal panel.
- a composite color video signal Scv as a television signal is input from the outside to the Y / C separation circuit 80, where it is separated into a luminance signal and a color signal.
- These luminance signals and color signals are converted into analog RGB signals corresponding to the three primary colors of light by the video chroma circuit 81, and further, the analog RGB signals are converted into digital RGB signals by the A / D converter 82. .
- This digital RGB signal is input to the liquid crystal controller 83.
- the Y / C separation circuit 80 also extracts horizontal and vertical synchronization signals from the composite color video signal Scv input from the outside, and these synchronization signals are also input to the liquid crystal controller 83 via the microcomputer 87.
- the liquid crystal display unit 84 receives a digital RGB signal from the liquid crystal controller 83 at a predetermined timing together with a timing signal based on the synchronization signal.
- the gradation circuit 88 generates gradation potentials for the three primary colors R, G, and B for color display, and these gradation potentials are also supplied to the liquid crystal display unit 84.
- the backlight drive is performed under the control of the microcomputer 87.
- the circuit 85 drives the backlight 86, so that light is irradiated to the back surface of the liquid crystal panel.
- the microcomputer 87 controls the entire system including the above processing.
- the video signal (composite color video signal) input from the outside includes not only a video signal based on television broadcasting but also a video signal captured by a camera, a video signal supplied via an Internet line, and the like.
- the liquid crystal display device 800 can display images based on various video signals.
- a tuner unit 90 is connected to the liquid crystal display device 800, whereby the present television receiver 601 is configured.
- the tuner unit 90 extracts a signal of a channel to be received from a received wave (high frequency signal) received by an antenna (not shown), converts the signal to an intermediate frequency signal, and detects the intermediate frequency signal, thereby detecting the television.
- a composite color video signal Scv as a signal is taken out.
- the composite color video signal Scv is input to the liquid crystal display device 800 as described above, and an image based on the composite color video signal Scv is displayed by the liquid crystal display device 800.
- FIG. 44 is an exploded perspective view showing a configuration example of the present television receiver.
- the present television receiver 601 includes a first casing 801 and a second casing 806 in addition to the liquid crystal display device 800 as its constituent elements. It is configured to be sandwiched between one housing 801 and a second housing 806.
- the first housing 801 is formed with an opening 801a through which an image displayed on the liquid crystal display device 800 is transmitted.
- the second housing 806 covers the back side of the liquid crystal display device 800, is provided with an operation circuit 805 for operating the display device 800, and a support member 808 is attached below. Yes.
- the present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.
- the active matrix substrate of the present invention and the liquid crystal panel provided with the active matrix substrate are suitable for, for example, a liquid crystal television.
Abstract
Description
図1は実施の形態1にかかる液晶パネルの一部を示す等価回路図である。図1に示すように、本液晶パネルは、列方向(図中上下方向)に延伸するデータ信号線(15x・15y)、行方向(図中左右方向)に延伸する走査信号線(16x・16y)、行および列方向に並べられた画素(101~104)、保持容量配線(18p・18q)、および共通電極(対向電極)comを備え、各画素の構造は同一である。なお、画素101・102が含まれる画素列と、画素103・104が含まれる画素列とが隣接し、画素101・103が含まれる画素行と、画素102・104が含まれる画素行とが隣接している。
図19は実施の形態2にかかる液晶パネルの一部を示す等価回路図である。図19に示すように、本液晶パネルでは、列方向(図中上下方向)に延伸するデータ信号線(15x・15y)、行方向(図中左右方向)に延伸する走査信号線(16x・16y)、行および列方向に並べられた画素(101~104)、保持容量配線(18p・18q)、および共通電極(対向電極)comを備え、各画素の構造は同一である。なお、画素101・102が含まれる画素列と、画素103・104が含まれる画素列とが隣接し、画素101・103が含まれる画素行と、画素102・104が含まれる画素行とが隣接している。
図31は実施の形態3にかかる液晶パネルの一部を示す等価回路図である。図31に示すように、本液晶パネルでは、列方向(図中上下方向)に延伸するデータ信号線(15x・15y)、行方向(図中左右方向)に延伸する走査信号線(16x・16y)、行および列方向に並べられた画素(101~104)、保持容量配線(18p~18s)、および共通電極(対向電極)comを備え、各画素の構造は同一である。なお、画素101・102が含まれる画素列と、画素103・104が含まれる画素列とが隣接し、画素101・103が含まれる画素行と、画素102・104が含まれる画素行とが隣接している。
図36は実施の形態4にかかる液晶パネルの一部を示す等価回路図である。図36に示すように、本液晶パネルでは、列方向(図中上下方向)に延伸するデータ信号線(15x・15y)、行方向(図中左右方向)に延伸する走査信号線(16x・16y)、行および列方向に並べられた画素(101~104)、保持容量配線(18p~18s)、および共通電極(対向電極)comを備え、各画素の構造は同一である。なお、画素101・102が含まれる画素列と、画素103・104が含まれる画素列とが隣接し、画素101・103が含まれる画素行と、画素102・104が含まれる画素行とが隣接している。
12a・12c・12A・12C トランジスタ
15x・15y・15z データ信号線
16x・16y 走査信号線
17a・17b・17c・17d 画素電極
17A・17B・17C・17D 画素電極
17a′・17b′・17c′・17d′ 画素電極
17A′・17B′・17C′・17D′ 画素電極
18p・18q・18r・18s 保持容量配線
21 有機ゲート絶縁膜
22 無機ゲート絶縁膜
24 半導体層
25 無機層間絶縁膜
26 有機層間絶縁膜
27a ドレイン引き出し配線
37a・37b・38a・38b 容量電極
39b・39b′ 保持容量電極
51a 薄膜部
84 液晶表示ユニット
601 テレビジョン受像機
800 液晶表示装置
Claims (32)
- 走査信号線と、データ信号線と、走査信号線およびデータ信号線に接続されたトランジスタとを備え、1つの画素領域に、第1および第2画素電極が設けられたアクティブマトリクス基板であって、
上記第1画素電極は、上記トランジスタを介して上記データ信号線に接続され、
上記第1および第2画素電極のうちの一方の画素電極に電気的に接続された第1および第2容量電極を備え、
上記第1および第2画素電極のうちの他方の画素電極と上記第1容量電極との間で容量が形成され、該他方の画素電極と上記第2容量電極との間で容量が形成されていることを特徴とするアクティブマトリクス基板。 - 上記トランジスタの一方の導通電極と、上記第1容量電極と、上記第2容量電極とが同層に形成されていることを特徴とする請求項1に記載のアクティブマトリクス基板。
- 上記第1容量電極の少なくとも一部が、上記トランジスタのチャネルを覆う層間絶縁膜を介して上記他方の画素電極と重なり、上記第2容量電極の少なくとも一部が、上記層間絶縁膜を介して上記他方の画素電極と重なっていることを特徴とする請求項1または2に記載のアクティブマトリクス基板。
- 上記第1および第2画素電極の外周は複数の辺からなるとともに、上記第1画素電極の一辺と上記第2画素電極の一辺とが隣接しており、上記第1および第2容量電極それぞれが、この隣接する2辺の間隙と上記第1画素電極と上記第2画素電極とに重なるように配されていることを特徴とする請求項1~3のいずれか1項に記載のアクティブマトリクス基板。
- 上記トランジスタの一方の導通電極がコンタクトホールを介して上記第1画素電極に接続されるとともに、該導通電極が、これから引き出された引き出し配線を介して上記第1容量電極に接続され、
上記第1画素電極と上記第2容量電極とがコンタクトホールを介して接続されていることを特徴とする請求項1~4のいずれか1項に記載のアクティブマトリクス基板。 - 上記トランジスタの一方の導通電極と上記第1画素電極とがコンタクトホールを介して接続されるとともに、上記第1画素電極と上記第1容量電極とがコンタクトホールを介して接続され、
上記第1画素電極と上記第2容量電極とがコンタクトホールを介して接続されていることを特徴とする請求項1~4のいずれか1項に記載のアクティブマトリクス基板。 - 上記トランジスタの一方の導通電極がコンタクトホールを介して上記第1画素電極に接続され、
上記第2画素電極と上記第1容量電極とがコンタクトホールを介して接続されるとともに、上記第2画素電極と上記第2容量電極とがコンタクトホールを介して接続されていることを特徴とする請求項1~4のいずれか1項に記載のアクティブマトリクス基板。 - 走査信号線の延伸方向を行方向として、上記第1および第2画素電極が列方向に並べられていることを特徴とする請求項1~7のいずれか1項に記載のアクティブマトリクス基板。
- 行方向に隣り合う2つの画素領域について、その一方の画素領域における上記第1画素電極と、他方の画素領域における上記第2画素電極とが行方向に隣接していることを特徴とする請求項8に記載のアクティブマトリクス基板。
- 上記第1画素電極が上記第2画素電極を取り囲んでいることを特徴とする請求項1~7のいずれか1項に記載のアクティブマトリクス基板。
- 上記第2画素電極が上記第1画素電極を取り囲んでいることを特徴とする請求項1~7のいずれか1項に記載のアクティブマトリクス基板。
- 上記第1画素電極あるいはこれに電気的に接続された導電体と容量を形成するとともに、上記第2画素電極あるいはこれに電気的に接続された導電体と容量を形成する保持容量配線をさらに備えることを特徴とする請求項1~11のいずれか1項に記載のアクティブマトリクス基板。
- 上記保持容量配線は、上記画素領域の中央を横切るように上記走査信号線と同方向に延伸していることを特徴とする請求項12に記載のアクティブマトリクス基板。
- 上記第1容量電極および上記第2容量電極それぞれが、上記保持容量配線と容量を形成していることを特徴とする請求項12に記載のアクティブマトリクス基板。
- 上記層間絶縁膜は無機絶縁膜とこれよりも厚い有機絶縁膜とからなるが、上記第1容量電極と重畳する部分の少なくとも一部と、上記第2容量電極と重畳する部分の少なくとも一部とについては、有機絶縁膜が除去されていることを特徴とする請求項3に記載のアクティブマトリクス基板。
- 上記層間絶縁膜は、上記第1容量電極の一部および上記第2容量電極の一部と重なる領域を含む、上記有機絶縁膜が除去されてなる薄膜部を有し、
上記第1および第2容量電極は、走査信号線の延伸方向に並んで配されるとともに、
上記第1容量電極は上記薄膜部の1辺を跨ぎ、上記第2容量電極は該1辺に対向する辺を跨いでいることを特徴とする請求項15に記載のアクティブマトリクス基板。 - 上記薄膜部は、上記第1および第2画素電極のいずれか一方と重なっていることを特徴とする請求項16に記載のアクティブマトリクス基板。
- 上記第1および第2画素電極の間隙が配向規制構造物として機能することを特徴とする請求項1~17のいずれか1項に記載のアクティブマトリクス基板。
- 上記第1画素電極が上記第2画素電極を取り囲んでおり、
上記第2画素電極の外周には互いに平行な2つの辺が含まれるとともに、上記第1画素電極の外周には上記2つの辺の一方と第1間隙を介して対向する辺と、他方と第2間隙を介して対向する辺とが含まれ、
上記第1容量電極が、上記第1画素電極と上記第1間隙と上記第2画素電極とに重なるように配されるとともに、上記第2容量電極が、上記第2画素電極と上記第2間隙と上記第1画素電極とに重なるように配されることを特徴とする請求項1~3のいずれか1項に記載のアクティブマトリクス基板。 - 走査信号線と、データ信号線と、走査信号線およびデータ信号線に接続されたトランジスタとを備え、1つの画素領域に、第1、第2および第3画素電極が設けられたアクティブマトリクス基板であって、
上記第1画素電極は、上記トランジスタを介して上記データ信号線に接続され、
上記第3画素電極は、上記第1画素電極に電気的に接続され、
上記第1画素電極に電気的に接続された第1容量電極と、上記第3画素電極に電気的に接続された第2容量電極とを備え、
上記第1容量電極と上記第2画素電極との間で容量が形成され、上記第2容量電極と上記第2画素電極との間で容量が形成されていることを特徴とするアクティブマトリクス基板。 - 走査信号線と、データ信号線と、走査信号線およびデータ信号線に接続されたトランジスタとを備え、1つの画素領域に、第1、第2および第3画素電極が設けられたアクティブマトリクス基板であって、
上記第1画素電極は、上記トランジスタを介して上記データ信号線に接続され、
上記第3画素電極は、上記第1画素電極に電気的に接続され、
上記第2画素電極に電気的に接続された第1および第2容量電極を備え、
上記第1容量電極と上記第1画素電極との間で容量が形成され、上記第2容量電極と上記第3画素電極との間で容量が形成されていることを特徴とするアクティブマトリクス基板。 - 走査信号線と、データ信号線と、走査信号線およびデータ信号線に接続されたトランジスタとを備え、1つの画素領域に、第1、第2および第3画素電極が設けられたアクティブマトリクス基板であって、
上記第2画素電極は、上記トランジスタを介して上記データ信号線に接続され、
上記第2画素電極に電気的に接続された第1および第2容量電極を備え、
上記第1容量電極と上記第1画素電極との間で容量が形成され、上記第2容量電極と上記第3画素電極との間で容量が形成されていることを特徴とするアクティブマトリクス基板。 - 走査信号線と、データ信号線と、走査信号線およびデータ信号線に接続されたトランジスタとを備え、1つの画素領域に、第1、第2および第3画素電極が設けられたアクティブマトリクス基板であって、
上記第2画素電極は、上記トランジスタを介して上記データ信号線に接続され、
上記第1画素電極に電気的に接続された第1容量電極と、上記第3画素電極に電気的に接続された第2容量電極とを備え、
上記第1容量電極と上記第2画素電極との間で容量が形成され、上記第2容量電極と上記第2画素電極との間で容量が形成されていることを特徴とするアクティブマトリクス基板。 - 上記画素領域に第1および第2保持容量配線をさらに備え、
上記第1容量電極が上記第1保持容量配線と容量を形成し、上記第2容量電極が上記第2保持容量配線と容量を形成していることを特徴とする請求項20~23のいずれか1項に記載のアクティブマトリクス基板。 - 走査信号線と、データ信号線と、走査信号線およびデータ信号線に接続されたトランジスタとを備え、1つの画素領域に、第1および第2画素電極が設けられ、上記第1画素電極が上記トランジスタを介して上記データ信号線に接続されたアクティブマトリクス基板の製造方法であって、
上記第1および第2画素電極のうちの一方の画素電極に電気的に接続されるとともに、他方の画素電極と容量を形成する第1容量電極と、上記一方の画素電極に電気的に接続されるとともに、上記他方の画素電極と容量を形成する第2容量電極とを形成する工程と、
上記第1容量電極と上記他方の画素電極との短絡、および上記第2容量電極と上記他方の画素電極との短絡の少なくとも一方を検出する工程と、
上記第1容量電極と上記他方の画素電極との短絡が検出された場合には、上記第1容量電極を、上記一方の画素電極との接続箇所および短絡箇所の間で切断し、上記第2容量電極と上記他方の画素電極との短絡が検出された場合には、上記第2容量電極を、上記一方の画素電極との接続箇所および短絡箇所の間で切断する工程とを含むことを特徴とするアクティブマトリクス基板の製造方法。 - 走査信号線と、データ信号線と、走査信号線およびデータ信号線に接続されたトランジスタとを備え、1つの画素領域に、第1および第2画素電極が設けられ、上記第1画素電極が上記トランジスタを介して上記データ信号線に接続されたアクティブマトリクス基板の製造方法であって、
上記第1および第2画素電極のうちの一方の画素電極に電気的に接続されるとともに、他方の画素電極および保持容量配線と容量を形成する第1容量電極と、上記一方の画素電極に電気的に接続されるとともに、上記他方の画素電極および上記保持容量配線と容量を形成する第2容量電極とを形成する工程と、
上記第1容量電極と上記他方の画素電極との短絡、上記第2容量電極と上記他方の画素電極との短絡、上記第1容量電極と上記保持容量配線との短絡、上記第2容量電極と上記保持容量配線との短絡の少なくとも一方を検出する工程と、
上記第1容量電極と上記他方の画素電極との短絡あるいは上記第1容量電極と上記保持容量配線との短絡が検出された場合には、上記第1容量電極を、上記一方の画素電極との接続箇所および短絡箇所の間で切断し、上記第2容量電極と上記他方の画素電極との短絡あるいは上記第2容量電極と上記保持容量配線との短絡が検出された場合には、上記第2容量電極を、上記一方の画素電極との接続箇所および短絡箇所の間で切断する工程とを含むことを特徴とするアクティブマトリクス基板の製造方法。 - 走査信号線と、データ信号線と、走査信号線およびデータ信号線に接続されたトランジスタとを備え、1つの画素に、第1および第2画素電極が設けられ、上記第1画素電極が上記トランジスタを介して上記データ信号線に接続された液晶パネルの製造方法であって、
上記第1および第2画素電極のうちの一方の画素電極に電気的に接続されるとともに、他方の画素電極と容量を形成する第1容量電極と、上記一方の画素電極に電気的に接続されるとともに、上記他方の画素電極と容量を形成する第2容量電極とを形成する工程と、
上記第1容量電極と上記他方の画素電極との短絡、および上記第2容量電極と上記他方の画素電極との短絡の少なくとも一方を検出する工程と、
上記第1容量電極と上記他方の画素電極との短絡が検出された場合には、上記第1容量電極を、上記一方の画素電極との接続箇所および短絡箇所の間で切断し、上記第2容量電極と上記他方の画素電極との短絡が検出された場合には、上記第2容量電極を、上記一方の画素電極との接続箇所および短絡箇所の間で切断する工程とを含むことを特徴とする液晶パネルの製造方法。 - 走査信号線と、データ信号線と、走査信号線およびデータ信号線に接続されたトランジスタとを備え、1つの画素に、第1および第2画素電極が設けられ、上記第1画素電極が上記トランジスタを介して上記データ信号線に接続された液晶パネルの製造方法であって、
上記第1および第2画素電極のうちの一方の画素電極に電気的に接続されるとともに、他方の画素電極および保持容量配線と容量を形成する第1容量電極と、上記一方の画素電極に電気的に接続されるとともに、上記他方の画素電極および上記保持容量配線と容量を形成する第2容量電極とを形成する工程と、
上記第1容量電極と上記他方の画素電極との短絡、上記第2容量電極と上記他方の画素電極との短絡、上記第1容量電極と上記保持容量配線との短絡、上記第2容量電極と上記保持容量配線との短絡の少なくとも一方を検出する工程と、
上記第1容量電極と上記他方の画素電極との短絡あるいは上記第1容量電極と上記保持容量配線との短絡が検出された場合には、上記第1容量電極を、上記一方の画素電極との接続箇所および短絡箇所の間で切断し、上記第2容量電極と上記他方の画素電極との短絡あるいは上記第2容量電極と上記保持容量配線との短絡が検出された場合には、上記第2容量電極を、上記一方の画素電極との接続箇所および短絡箇所の間で切断する工程とを含むことを特徴とする液晶パネルの製造方法。 - 請求項1~24のいずれか1項に記載のアクティブマトリクス基板を備えた液晶パネル。
- 請求項29に記載の液晶パネルとドライバとを備えることを特徴とする液晶表示ユニット。
- 請求項30に記載の液晶表示ユニットと光源装置とを備えることを特徴とする液晶表示装置。
- 請求項31に記載の液晶表示装置と、テレビジョン放送を受信するチューナー部とを備えることを特徴とするテレビジョン受像機。
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CN200980144675.0A CN102209930B (zh) | 2008-12-10 | 2009-07-23 | 有源矩阵基板、有源矩阵基板的制造方法、液晶面板、液晶面板的制造方法、液晶显示装置、液晶显示单元、电视接收机 |
BRPI0922157A BRPI0922157A2 (pt) | 2008-12-10 | 2009-07-23 | substrato de matriz ativa, método de fabricação de substrato de matriz ativa, painel de cristal líquido, método de fabricação de painel de cristal líquido, dispositivo de exibição de cristal líquido, unidade de exibição de cristal líquido, e receptor de televisão |
EP09831745A EP2357520A4 (en) | 2008-12-10 | 2009-07-23 | ACTIVE MATRIX SUBSTRATE, PROCESS FOR PREPARING AN ACTIVE MATRIX SUBSTRATE, LIQUID CRYSTAL SCREEN, METHOD FOR PRODUCING A LIQUID CRYSTAL SCREEN, LIQUID CRYSTAL DISPLAY ARRANGEMENT, LIQUID CRYSTAL DISPLAY UNIT AND TV RECEIVER |
US13/123,718 US8659712B2 (en) | 2008-12-10 | 2009-07-23 | Active matrix substrate, method for manufacturing active matrix substrate, liquid crystal panel, method for manufacturing liquid crystal panel, liquid crystal display device, liquid crystal display unit, and television receiver |
RU2011115222/28A RU2478224C2 (ru) | 2008-12-10 | 2009-07-23 | Подложка активной матрицы, способ изготовления подложки активной матрицы, жидкокристаллическая панель, способ изготовления жидкокристаллической панели, жидкокристаллическое дисплейное устройство, жидкокристаллический дисплей и телевизионный приемник |
JP2010542044A JP5301567B2 (ja) | 2008-12-10 | 2009-07-23 | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 |
KR1020117010869A KR101247092B1 (ko) | 2008-12-10 | 2009-07-23 | 액티브 매트릭스 기판, 액티브 매트릭스 기판의 제조 방법, 액정 패널, 액정 패널의 제조 방법, 액정 표시 장치, 액정 표시 유닛, 텔레비전 수상기 |
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EP (1) | EP2357520A4 (ja) |
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CN (1) | CN102209930B (ja) |
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JP2018195832A (ja) * | 2013-01-30 | 2018-12-06 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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CN102566157B (zh) * | 2010-12-16 | 2014-10-08 | 京东方科技集团股份有限公司 | 阵列基板和液晶显示器 |
JP5806383B2 (ja) * | 2012-02-27 | 2015-11-10 | 京セラ株式会社 | 液晶表示装置 |
JP6335112B2 (ja) * | 2014-03-24 | 2018-05-30 | 株式会社ジャパンディスプレイ | センサ付き表示装置及びセンサ装置 |
US10360864B2 (en) * | 2014-04-22 | 2019-07-23 | Sharp Kabushiki Kaisha | Active-matrix substrate and display device including the same |
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BRPI0922157A2 (pt) | 2015-12-29 |
JPWO2010067639A1 (ja) | 2012-05-17 |
EP2357520A4 (en) | 2012-05-30 |
EP2357520A1 (en) | 2011-08-17 |
CN102209930B (zh) | 2014-07-16 |
JP5301567B2 (ja) | 2013-09-25 |
CN102209930A (zh) | 2011-10-05 |
RU2478224C2 (ru) | 2013-03-27 |
US20110194031A1 (en) | 2011-08-11 |
KR101247092B1 (ko) | 2013-03-25 |
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US8659712B2 (en) | 2014-02-25 |
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