WO2010061653A1 - Pfcコンバータ - Google Patents
Pfcコンバータ Download PDFInfo
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- WO2010061653A1 WO2010061653A1 PCT/JP2009/059750 JP2009059750W WO2010061653A1 WO 2010061653 A1 WO2010061653 A1 WO 2010061653A1 JP 2009059750 W JP2009059750 W JP 2009059750W WO 2010061653 A1 WO2010061653 A1 WO 2010061653A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
- H02M1/0022—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being input voltage fluctuations
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
Definitions
- the present invention relates to an AC-DC converter that inputs an AC power supply and outputs a DC voltage, and more particularly to a PFC converter that suppresses harmonic current.
- a general switching power supply device that uses a commercial AC power supply as an input power supply rectifies and smoothes the commercial AC power supply and converts it to a DC voltage, which is then switched by a DC-DC converter. Is greatly distorted. This is the cause of the harmonic current.
- a PFC converter is provided after the full-wave rectifier circuit and before the smoothing circuit by the smoothing capacitor.
- This PFC converter is composed of a chopper circuit and operates so that the input current waveform is similar to the input voltage waveform and has the same phase as a sine wave. Therefore, the harmonic current is suppressed to a certain level or less, and the power factor is improved.
- P Proportional control
- PI Proportional-integral control
- PID Proportional-Integral-Differential control
- Patent Document 1 is an example of a PFC converter that performs P control.
- FIG. 1 is a circuit diagram of a PFC converter disclosed in Patent Document 1. In FIG. Here, the PFC converter of Patent Document 1 will be described with reference to FIG.
- Fig. 1 shows a so-called step-up voltage converter.
- a voltage Vr obtained by rectifying an AC voltage Va of a commercial power supply by a rectifier circuit 1 is applied to a reactor 2, and a current generated in the reactor 2 is interrupted by a switching transistor 3.
- the output voltage Vo is taken out and is smoothed and stabilized by the capacitor 5.
- the detection value vo of the output voltage Vo by the voltage dividing circuit 6 is given to the error amplification circuit 7, and the error voltage ve indicating the difference from the set value vs is output.
- the multiplication circuit 8 receives the error voltage ve and the rectified voltage Vr, and outputs a voltage error signal Se that is proportional to the error voltage ve and has the same pulsating waveform as that of the rectified voltage Vr.
- the current flowing when the switching transistor 3 is turned on and its waveform are detected by the detection resistor 9, and this current waveform signal Sc and the voltage error signal Se described above are given to the current error detection circuit 10 to express the current difference signal representing the waveform difference between the two signals.
- S1 is output to the non-inverting input of the comparator 20.
- the comparator 20 compares the current error signal S1 with a sawtooth wave period signal S0 that specifies the intermittent period of the switching transistor 3 received from the high-frequency oscillation circuit 21, and compares the on / off command signal Sw that is a PWM signal with the switching transistor. 3 is output.
- the current flowing through the reactor 2 is interrupted at the duty ratio specified by the on / off command Sw.
- the PFC converter disclosed in Patent Document 1 has a high gain in a low frequency region, but a finite gain. That is, there is an error even in a stable state. As the output voltage error ve shown in FIG. 1 increases, the difference between the output voltage Vo and the target voltage vs increases and the output voltage decreases.
- the PFC converter shown in Patent Document 2 has a direct current and an infinite gain, so that the error in the stable state can be made zero. However, in the transient state such as a sudden load change, the capacitor is charged and discharged. Since it takes time, the time until the output voltage converges is longer than that of the P-controlled PFC converter shown in FIG.
- an object of the present invention is to have both P control responsiveness and PI control stability, so that fluctuations in output voltage due to fluctuations in input voltage and load can be suppressed without deteriorating transient responsiveness. It is to provide a PFC converter.
- a PFC converter comprising: a circuit; and switching control means for controlling on / off of the switching element so that an input current input from the AC input power source is similar to the AC voltage, Input voltage detection means for detecting an input voltage input from the AC input power supply; Inductor current detection means for detecting current flowing in the inductor; Output voltage detecting means for detecting the output voltage of the rectifying and smoothing means,
- the switching control means uses a product of an output voltage error, which is an error of a detected value of the output voltage with respect to an output voltage target value, and a detected value of the input voltage as a current reference amplitude value, and the current reference amplitude value and the inductor Is a means for controlling the on-
- the switching control unit and the output voltage control value correction unit are configured by a DSP (Digital Signal Processor) that holds a digital value corresponding to the output voltage target value, and the output voltage control value correction unit includes The digital value is corrected by a proportional value of the current reference amplitude value.
- DSP Digital Signal Processor
- FIG. 2 is a circuit diagram of a PFC converter disclosed in Patent Document 1.
- FIG. 1 is a circuit diagram of a PFC converter according to a first embodiment.
- FIG. It is a wave form diagram of the voltage and current of the PFC converter 101 in the unit of a switching cycle in the state in which control is performed in the current continuous mode.
- FIG. 3 is a diagram showing the processing contents of the digital signal processing circuit 13 shown in FIG. 2 in blocks. It is a block diagram regarding feedback control of output voltage.
- FIG. 5 is a circuit diagram of an output voltage error amplifier according to a second embodiment.
- FIG. 2 is a circuit diagram of the PFC converter according to the first embodiment.
- reference signs P ⁇ b> 11 and P ⁇ b> 12 are input ports of the PFC converter 101
- reference signs P ⁇ b> 21 and P ⁇ b> 22 are output ports of the PFC converter 101.
- An AC input power supply Vac which is a commercial AC power supply, is input to the input ports P11 to P12, and a load circuit 100 is connected to the output ports P21 to P22.
- the load circuit 100 is, for example, a DC-DC converter and a circuit of an electronic device that is supplied with power by the DC-DC converter.
- the input stage of the PFC converter 101 is provided with a diode bridge B1 that full-wave rectifies the AC voltage of the AC input power supply Vac.
- the diode bridge B1 corresponds to the “rectifier circuit” of the present invention.
- a series circuit of an inductor L1, a switching element Q1, and a current detection resistor Rcd is connected to the output side of the diode bridge B1.
- a rectifying / smoothing circuit composed of a diode D1 and a smoothing capacitor C1 is connected in parallel to both ends of the switching element Q1.
- the inductor L1, the switching element Q1, the diode D1, and the smoothing capacitor C1 constitute a so-called boost chopper circuit.
- the current detection resistor Rcd and the input portion of the digital signal processing circuit 13 for inputting the signal correspond to the “inductor current detection means” of the present invention.
- An input voltage detection circuit 11 is provided between both ends on the output side of the diode bridge B1.
- An output voltage detection circuit 12 is provided between the output ports P21 and P22.
- the digital signal processing circuit 13 is constituted by a DSP, and controls the PFC converter 101 by digital signal processing. That is, the digital signal processing circuit 13 receives the output signal of the input voltage detection circuit 11 and detects the phase of the voltage of the AC input power supply. Further, the output signal of the output voltage detection circuit 12 is inputted to detect the output voltage. Further, the switching element Q1 is turned on / off at a predetermined switching frequency.
- the digital signal processing circuit 13 corresponds to the “switching control means” of the present invention.
- the input portion of the input voltage detection circuit 11 and the digital signal processing circuit 13 for inputting the signal corresponds to the “input voltage detection means” of the present invention.
- the output voltage detection circuit 12 and the input part of the digital signal processing circuit 13 for inputting the signal correspond to the “output voltage detection means” of the present invention.
- the digital signal processing circuit 13 includes a port for performing communication with the load circuit 100.
- the digital signal processing circuit 13 performs data communication or signal input / output, and the state of the converter with respect to the load circuit (electronic device). Etc. are always transmitted, input voltage, output voltage, output current, etc. are transmitted, or the load state is received from the load circuit side and reflected in the switching control.
- FIG. 3 is a waveform diagram of the voltage / current of the PFC converter 101 in units of switching periods in a state where control is performed in the continuous current mode.
- the digital signal processing circuit 13 performs switching control so that the input current to the PFC converter 101, that is, the average value of the current flowing through the inductor L1, is similar to the full-wave rectified waveform. In this way, when an input current similar to the input voltage flows, harmonics are suppressed and the power factor is improved.
- (A) is a current waveform of the average value Ii of the current flowing through the inductor L1 in a unit of a half cycle of the commercial power supply frequency
- (B) is an enlarged part of the time axis of the switching cycle.
- (C) is a waveform diagram of the drain-source voltage Vds of the switching element Q1.
- the current IL flows through the inductor L1, and the current IL increases with a slope determined according to the voltage across the inductor L1 and the inductance of the inductor L1. Thereafter, the current IL decreases with an inclination determined by the voltage across the inductor L1 and its inductance during the OFF period Toff of the switching element Q1. As described above, the current IL flowing through the inductor L1 with the width of the current ripple ⁇ IL varies in the switching cycle.
- FIG. 4 is a block diagram showing the processing contents of the digital signal processing circuit 13 shown in FIG.
- the adding element 31 calculates an error ev of the output voltage detection value vo with respect to an output voltage target value Vref described later.
- the output voltage error amplifier 32 obtains a current reference amplitude value vm by multiplying the error ev by a predetermined proportionality coefficient (usually, the error amplifier in the PFC needs to prevent the output voltage from responding to the ripple of the input voltage. Because it has high-frequency cutoff characteristics).
- the multiplier 33 obtains the current reference value ir by multiplying the current reference amplitude value vm by the input voltage detection value vi.
- the adding element 34 obtains an input current error value ei that is a difference between the inductor current detection value iL and the current reference value ir.
- the input current error amplifier 35 multiplies the input current error value ei by a predetermined proportionality coefficient to generate a modulation signal D for the pulse generator.
- the pulse generator 36 Based on the modulation signal D, the pulse generator 36 outputs a pulse signal which is a binary logic signal.
- This pulse signal is a switching control signal for the switching element Q1. That is, the switching control signal is PWM-modulated with a value proportional to the current error value ei. Thereby, the ON time of the switching element Q1 is controlled.
- the coefficient element 38 generates a value obtained by multiplying the current reference amplitude value vm by a predetermined coefficient.
- the adding element 39 adds the value generated by the coefficient element 38 to the reference value vr0 to obtain the output voltage target value Vref.
- the coefficient element 38 and the addition element 39 correspond to the “output voltage control value correcting means” of the present invention.
- the coefficient element 38 changes the output voltage target value Vref according to the output vm of the output voltage error amplifier 32. Therefore, abnormal oscillation may occur depending on conditions. In such a case, the coefficient element 38 has a high-frequency cutoff characteristic. As a result, even when the current reference amplitude value vm changes rapidly, the change in Vref becomes slow, and a transient response can be avoided.
- FIG. 5 is a block diagram relating to feedback control of the output voltage.
- FIG. 5A is a block diagram of a feedback system including the addition element 31, the output voltage error amplifier 32, the coefficient element 38, and the addition element 39 shown in FIG.
- FIG. 5B is a comparative example and is a block diagram when the coefficient element 38 and the addition element 39 shown in FIG. 4 are not provided.
- the error ev of the output voltage detection value vo with respect to the output voltage target value Vref is obtained, and the output voltage error amplifier 32 outputs the current reference amplitude value vm to be controlled (
- the PFC converter 50 controls the output voltage (output voltage detection value vo) based on the current reference amplitude value vm.
- the coefficient element 38 further adds a value obtained by multiplying the current reference amplitude value vm by a coefficient to the reference (fixed) target value vr0 to output the output voltage target value Vref. To correct.
- the residual (the output voltage detection value vo in the steady state and the output voltage target value Vref is basically controlled while being P control). Control without difference is possible.
- condition judgment and condition branching can be performed in a detailed and complicated manner. For example, when the load is large, the target value is also large. When it is detected that the load has suddenly decreased in this state, the output voltage target value Vref is reset to the initial value. This suppresses a jump in the output voltage when the load suddenly decreases.
- Second Embodiment In the first embodiment, as shown in FIGS. 2 and 4, the switching control is performed using the digital signal processing circuit 13 by the DSP. However, in the second embodiment, the output shown in FIG. This is an example in which the voltage error amplifier 32 is composed of analog elements.
- FIG. 6 is a circuit diagram of an output voltage error amplifier according to the second embodiment.
- the input voltage Vref at the non-inverting input terminal (+) of the operational amplifier OP is expressed by the following equation (1).
- vm is an output voltage of the operational amplifier OP (output of the output voltage error amplifier)
- vo is an output voltage detection value
- Vref is an output voltage target value.
- Vref (vr0 / Rr1 + vm / Rr3) / (1 / Rr1 + 1 / Rr2 + 1 / Rr3) (1)
- the capacitor Cref is connected in parallel to the resistor Rr2
- the change in the output voltage target value Vref with the lapse of time decreases as the capacitance of the capacitor Cref increases. That is, it has a function of a low-pass filter.
- the output voltage can be made constant regardless of the input voltage or load without degrading the transient response.
- Switching element Rcd Current detection resistor Toff ... Off period Ton ... On period Vac ... AC input power supply Vds ... Source voltage vi ... Input voltage detection value vm ... Current reference amplitude value vo ... Output voltage detection value vr0 ... Reference value Vref ... Output voltage target value
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Abstract
Description
(1)交流入力電源から入力される交流電圧を整流する整流回路と、前記整流回路の次段に接続された、インダクタ及びスイッチング素子を含む直列回路と、前記スイッチング素子に並列接続された整流平滑回路と、前記交流入力電源から入力される入力電流が前記交流電圧に対して相似形となるように前記スイッチング素子をオン/オフ制御するスイッチング制御手段と、を備えたPFCコンバータであって、
前記交流入力電源から入力される入力電圧を検出する入力電圧検出手段と、
前記インダクタに流れる電流を検出するインダクタ電流検出手段と、
前記整流平滑手段の出力電圧を検出する出力電圧検出手段と、を備え、
前記スイッチング制御手段は、出力電圧目標値に対する前記出力電圧の検出値の誤差である出力電圧誤差と、前記入力電圧の検出値との積を電流基準振幅値とし、この電流基準振幅値と前記インダクタに流れる電流との差に応じて前記スイッチング素子のオン時間を制御する手段であり、
前記出力電圧の目標値または前記出力電圧誤差を前記電流基準振幅値の比例値で補正する出力電圧制御値補正手段を設けたことを特徴とする。
第1の実施形態に係るPFCコンバータについて図2~図6を参照して説明する。
図2は第1の実施形態に係るPFCコンバータの回路図である。図2において符号P11,P12はPFCコンバータ101の入力ポート、符号P21,P22はPFCコンバータ101の出力ポートである。入力ポートP11-P12には商用交流電源である交流入力電源Vacが入力され、出力ポートP21-P22には負荷回路100が接続される。
電流検出用抵抗Rcd及びその信号を入力するディジタル信号処理回路13の入力部は、この発明の「インダクタ電流検出手段」に相当する。
ディジタル信号処理回路13は、PFCコンバータ101に対する入力電流、すなわちインダクタL1に流れる電流の平均値、が全波整流波形に相似形となるようにスイッチング制御を行う。このようにして入力電圧と相似形の入力電流が流れることにより、高調波が抑制され、力率が改善される。
図4において、加算要素31は、後述する出力電圧目標値Vrefに対する出力電圧検出値voの誤差evを求める。出力電圧誤差増幅器32は、誤差evに対して所定の比例係数を乗じて電流基準振幅値vmを求める(通常、PFCにおける誤差増幅器は、出力電圧が入力電圧のリップルに応答しないようにする必要があるため、高域遮断特性を持つ)。乗算器33は、電流基準振幅値vmに対して入力電圧検出値viを乗じて電流基準値irを求める。加算要素34は、電流基準値irに対するインダクタ電流検出値iLの差分である入力電流誤差値eiを求める。入力電流誤差増幅器35は入力電流誤差値eiに対して所定の比例係数を乗じて、パルス生成器に対する変調信号Dを発生する。パルス生成器36は前記変調信号Dに基づいて、二値論理信号であるパルス信号を出力する。このパルス信号はスイッチング素子Q1に対するスイッチング制御信号である。すなわちスイッチング制御信号を前記電流誤差値eiに比例した値でPWM変調する。これによりスイッチング素子Q1のオン時間が制御される。
第1の実施形態では、図2及び図4に示したように、DSPによるディジタル信号処理回路13を用いてスイッチング制御を行うようにしたが、第2の実施形態は、図4に示した出力電圧誤差増幅器32をアナログ素子で構成する例である。
但し、抵抗Rr2に対してコンデンサCrefが並列接続されているので、このコンデンサCrefの容量が大きくなるほど、時間経過あたりの出力電圧目標値Vrefの変化は小さくなる。すなわちローパスフィルタの作用を備えることになる。
11…入力電圧検出回路
12…出力電圧検出回路
13…ディジタル信号処理回路
31…加算要素
32…出力電圧誤差増幅器
33…乗算器
34…加算要素
35…入力電流誤差増幅器
36…パルス生成器
38…係数要素
39…加算要素
B1…ダイオードブリッジ
C1…平滑コンデンサ
Cref…コンデンサ
D…変調信号
D1…ダイオード
ei…入力電流誤差値
ev…誤差
iL…インダクタ電流検出値
ir…電流基準値
L1…インダクタ
OP…オペアンプ
Q1…スイッチング素子
Rcd…電流検出用抵抗
Toff…オフ期間
Ton…オン期間
Vac…交流入力電源
Vds…ソース間電圧
vi…入力電圧検出値
vm…電流基準振幅値
vo…出力電圧検出値
vr0…基準値
Vref…出力電圧目標値
Claims (2)
- 交流入力電源から入力される交流電圧を整流する整流回路と、前記整流回路の次段に接続された、インダクタ及びスイッチング素子を含む直列回路と、前記スイッチング素子に並列接続された整流平滑回路と、前記交流入力電源から入力される入力電流が前記交流電圧に対して相似形となるように前記スイッチング素子をオン/オフ制御するスイッチング制御手段と、を備えたPFCコンバータであって、
前記交流入力電源から入力される入力電圧を検出する入力電圧検出手段と、
前記インダクタに流れる電流を検出するインダクタ電流検出手段と、
前記整流平滑回路の出力電圧を検出する出力電圧検出手段と、を備え、
前記スイッチング制御手段は、出力電圧目標値に対する前記出力電圧の検出値の誤差である出力電圧誤差と、前記入力電圧の検出値との積を電流基準振幅値とし、この電流基準振幅値と前記インダクタに流れる電流との差に応じて前記スイッチング素子のオン時間を制御する手段であり、
前記出力電圧の目標値または前記出力電圧誤差を前記電流基準振幅値の比例値で補正する出力電圧制御値補正手段を設けたPFCコンバータ。 - 前記スイッチング制御手段及び前記出力電圧制御値補正手段は、前記出力電圧目標値に相当するディジタル値を保持するDSP(Digital Signal Processor)で構成され、前記出力電圧制御値補正手段は、前記ディジタル値を前記電流基準振幅値の比例値で補正するようにした、請求項1に記載のPFCコンバータ。
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CN200980140888.6A CN102187559B (zh) | 2008-11-25 | 2009-05-28 | Pfc变换器 |
JP2010540403A JP5273158B2 (ja) | 2008-11-25 | 2009-05-28 | Pfcコンバータ |
US13/108,019 US8179703B2 (en) | 2008-11-25 | 2011-05-16 | Power factor correction converter |
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WO2017056298A1 (ja) * | 2015-10-01 | 2017-04-06 | 三菱電機株式会社 | 電力変換装置及びこれを用いた空気調和装置 |
JP2017112822A (ja) * | 2015-12-15 | 2017-06-22 | 國家中山科學研究院 | 力率改善コンバータ及びその制御方法 |
WO2022168608A1 (ja) * | 2021-02-03 | 2022-08-11 | ソニーグループ株式会社 | 電源装置及び表示装置 |
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- 2009-05-28 CN CN200980140888.6A patent/CN102187559B/zh not_active Expired - Fee Related
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KR101422940B1 (ko) | 2012-12-05 | 2014-07-23 | 삼성전기주식회사 | 역률 보정 장치 및 그를 이용한 역률 보정 제어 방법 |
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JPWO2017056298A1 (ja) * | 2015-10-01 | 2018-02-08 | 三菱電機株式会社 | 電力変換装置及びこれを用いた空気調和装置 |
JP2017112822A (ja) * | 2015-12-15 | 2017-06-22 | 國家中山科學研究院 | 力率改善コンバータ及びその制御方法 |
WO2022168608A1 (ja) * | 2021-02-03 | 2022-08-11 | ソニーグループ株式会社 | 電源装置及び表示装置 |
Also Published As
Publication number | Publication date |
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JP5273158B2 (ja) | 2013-08-28 |
CN102187559A (zh) | 2011-09-14 |
US20110211375A1 (en) | 2011-09-01 |
US8179703B2 (en) | 2012-05-15 |
CN102187559B (zh) | 2014-07-30 |
JPWO2010061653A1 (ja) | 2012-04-26 |
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