WO2015049716A1 - 力率改善回路 - Google Patents
力率改善回路 Download PDFInfo
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- WO2015049716A1 WO2015049716A1 PCT/JP2013/076642 JP2013076642W WO2015049716A1 WO 2015049716 A1 WO2015049716 A1 WO 2015049716A1 JP 2013076642 W JP2013076642 W JP 2013076642W WO 2015049716 A1 WO2015049716 A1 WO 2015049716A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0083—Converters characterised by their input or output configuration
- H02M1/0085—Partially controlled bridges
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to a power factor improvement circuit for improving an input power factor in a power converter for supplying a rectified voltage of an AC power supply voltage to a load.
- boost chopper consisting of an inductor (boost reactor), a semiconductor switch, a rectifier diode, and a smoothing capacitor is connected to the output side of the full-wave rectifier circuit, and distortion of the input current is suppressed by the switching operation of the boost chopper.
- Power factor correction circuits are known in the art.
- FIG. 8 shows a power factor correction circuit of this type, which is described in Patent Document 1.
- 10 is an AC power supply
- 20 is a full wave rectification circuit comprising a diode bridge
- 31 is an inductor
- 32 is a current detection resistor
- 33 is a semiconductor switch
- 34 is a rectifying diode
- 35 is a smoothing capacitor
- 40 is a load.
- the inductor 31, the semiconductor switch 33, the rectifying diode 34 and the smoothing capacitor 35 constitute a step-up chopper, and by turning on and off the semiconductor switch 33, accumulation and release of energy to the inductor 31 are repeated. Is boosted to a DC voltage higher than the output voltage of the full-wave rectifier circuit 20 and supplied to the load 40.
- 50 is a control circuit for controlling the semiconductor switch 33
- 51 is an error amplifier for amplifying an error between the reference voltage 52 and the output voltage of the main circuit
- 53 is an output of the error amplifier 52 and the positive of the full wave rectification circuit 20.
- a multiplier that multiplies the side terminal voltage
- an error amplifier that amplifies an error between the output of the multiplier 53 and the negative side terminal voltage (voltage of one end of the current detection resistor 32) of the full wave rectification circuit 20
- 55 is all Controlled oscillator (VCO) that outputs a triangular wave signal according to the magnitude of the positive side terminal voltage of the wave rectification circuit 20, 56 compares the feedback signal FB output from the error amplifier 54 with the triangular wave signal output from the VCO 55
- VCO Controlled oscillator
- the PWM comparator 56 generates a PWM pulse that continuously compensates for fluctuations in the AC power supply voltage and the DC output voltage, and matches the AC current waveform to the AC voltage waveform to improve the input power factor. .
- the switching frequency f of the semiconductor switch 33 in proportion to the magnitude of the AC power supply voltage v in by the action of the VCO 55, the normal mode noise generated along with the switching is converted to a frequency. It disperses to reduce noise and switching loss.
- the error amplifier 51 amplifies an error between the reference voltage 52 and the DC output voltage of the main circuit, and the error voltage is multiplied by the positive terminal voltage of the full wave rectification circuit 20. The result is input to the noninverting input terminal of the error amplifier 54.
- the error amplifier 54 calculates an error voltage from the multiplication result and the voltage at one end of the current detection resistor 32, and this error voltage is input to the non-inverting input terminal of the PWM comparator 56 as the feedback signal FB.
- VCO 55 as shown in FIG. 10 has a voltage frequency characteristics changing the frequency f from f 1 to f 2 within a range extending from a lower limit E 1 to the upper limit value E 2 of the input voltage E, depending on the magnitude of the input voltage E, for example, a triangular wave signal of the upper limit frequency f 2 shown in the upper part of FIG. 11 (a), the or outputs a triangular wave signal of the lower limit frequency f 1 shown in the upper part of FIG. 11 (b).
- the comparator 56 compares the triangular wave signal with the feedback signal FB output from the error amplifier 54 to generate a PWM pulse shown in the lower part of FIGS. 11 (a) and 11 (b). 33 is switching.
- Patent No. 4363067 (Paragraphs [0026] to [0052], FIGS. 1 to 8 and the like)
- the switching frequency f is lowered to reduce the switching loss, particularly in the range where the AC power supply voltage v in is low, and, as described above, noise associated with switching The noise is suppressed by dispersing.
- this prior art is based on the idea of changing the switching frequency f simply in proportion to the magnitude of the AC power supply voltage v in . Therefore, depending on the magnitude of AC power supply voltage v in, the noise reduction effect may not be sufficiently obtained, and a large filter circuit provided with a normal mode coil or the like must be used in combination to clear predetermined conduction noise regulation. There was a problem of not getting
- the problem to be solved by the present invention is to change the switching frequency of the semiconductor switch for improving the power factor by a method different from that of Patent Document 1, thereby significantly reducing normal mode noise and enabling the filter circuit to be miniaturized. Providing a power factor correction circuit.
- the invention according to claim 1 is that a series circuit including an inductor and a semiconductor switch is connected between output terminals of an AC power supply, and a diode and a smoothing capacitor are connected in series to both ends of the semiconductor switch.
- a circuit connected and a load connected across the smoothing capacitor In a power factor improvement circuit which improves the power factor of the input side of the circuit by the switching operation of the semiconductor switch,
- a control circuit that makes the switching frequency of the semiconductor switch variable; The control circuit controls the switching frequency such that the switching frequency is maximized when the ripple of the current flowing through the inductor is maximized.
- the invention according to claim 2 is a rectifier circuit for rectifying an AC power supply voltage, a series circuit of an inductor and a semiconductor switch connected between output terminals of the rectifier circuit, and a diode connected to both ends of the semiconductor switch.
- the invention according to claim 3 is the power factor correction circuit according to claim 1 or 2, wherein the voltage detection circuit detects an AC power supply voltage as an input voltage, and the voltage detection circuit detects an end voltage of a smoothing capacitor as an output voltage.
- the control circuit controls the switching frequency to the maximum value by detecting when the ripple is maximum based on the ratio of the input voltage to the output voltage.
- the invention according to claim 4 is the power factor correction circuit according to claim 3, wherein the control circuit detects that the ripple is maximum when the ratio of the input voltage to the output voltage is 0.5. .
- a series circuit including an inductor and a semiconductor switch is connected between output terminals of an alternating current power supply, a series circuit of a diode and a smoothing capacitor is connected to both ends of the semiconductor switch, and the smoothing is performed.
- a circuit in which a load is connected across the capacitor In a power factor improvement circuit which improves the power factor of the input side of the circuit by the switching operation of the semiconductor switch, A control circuit that makes the switching frequency of the semiconductor switch variable; The control circuit controls the switching frequency such that the switching frequency is maximized when the third harmonic component of the ripple of the current flowing through the inductor is maximized.
- the invention according to claim 6 is a rectifier circuit for rectifying an AC power supply voltage, a series circuit of an inductor and a semiconductor switch connected between output terminals of the rectifier circuit, and a diode connected to both ends of the semiconductor switch A series circuit with a smoothing capacitor, wherein a load is connected across the smoothing capacitor,
- a control circuit that makes the switching frequency of the semiconductor switch variable; The control circuit controls the switching frequency such that the switching frequency is maximized when the third harmonic component of the ripple of the current flowing through the inductor is maximized.
- the invention according to claim 7 is the power factor correction circuit according to claim 6, comprising: a voltage detection circuit that detects an alternating current power supply voltage as an input voltage; a voltage detection circuit that detects a voltage across a smoothing capacitor as an output voltage; The control circuit controls the switching frequency to the maximum value by detecting when the third harmonic component of the ripple is maximum based on the ratio of the input voltage to the output voltage.
- normal mode noise can be effectively reduced by controlling the switching frequency of the semiconductor switch based on the input / output voltage of the power factor correction circuit, whereby the filter circuit and hence the entire device can be miniaturized.
- FIG. 1 It is a block diagram of the power factor improvement circuit concerning the embodiment of the present invention. It is a graph which shows the relationship between the input-output voltage ratio in FIG. 1, and an inductor electric current ripple. It is a block diagram which shows 1st Example of the control circuit in FIG. It is a figure which shows the relationship between a duty ratio and the 3rd harmonic component of a ripple. It is a block diagram which shows 2nd Example of the control circuit in FIG. It is a figure which shows the relationship between a duty ratio, the 3rd harmonic component of a ripple, and a switching frequency. It is a circuit diagram showing the principal part of other embodiments of the present invention. It is a block diagram of the power factor improvement circuit described in patent document 1. FIG.
- FIG. 9 is an explanatory diagram of voltage frequency conversion characteristics of the VCO in FIG. 8; 9 is a timing chart showing operations of the VCO and the PWM comparator in FIG.
- FIG. 1 is a block diagram of a power factor correction circuit according to this embodiment.
- 10 is an AC power supply
- 15 is a filter circuit consisting of a reactor, a capacitor, etc.
- 20 is a full wave rectification circuit consisting of a diode bridge
- 31 is an inductor (boost reactor)
- 32 is a current detection resistor
- 33 is a MOSFET etc.
- a semiconductor switch 34 is a rectifying diode
- 35 is a smoothing capacitor
- 40 is a load.
- the inductor 31, the semiconductor switch 33, the rectifying diode 34 and the smoothing capacitor 35 constitute a step-up chopper, and the semiconductor switch 33 is turned on and off to repeatedly store and release energy in the inductor 31,
- the voltage 35 is boosted to a DC voltage higher than the output voltage of the full wave rectifier circuit 20 and supplied to the load 40.
- An input voltage (AC power supply voltage) detection circuit 61 is connected between input terminals of the full wave rectification circuit 20, and a current detection circuit 62 is connected to both ends of the current detection resistor 32, and a diode 34 and a smoothing capacitor 35 are provided.
- An output voltage detection circuit 63 is connected to a connection point between the two. The outputs of these detection circuits 61, 62, 63 are input to a control circuit 70 such as a microcomputer that executes voltage control, current control and PWM control. Further, a PWM pulse is inputted from the control circuit 70 to the drive circuit, and the drive circuit 80 is configured to turn on and off the semiconductor switch 33 based on the PWM pulse.
- the normal mode noise has size and the correlation of the ripple contained in the current I L of the inductor 31, the normal mode noise as the ripple of the current I L is greater increases.
- the switching frequency command value F SW * is calculated according to the block diagram shown in FIG.
- the selector 74 selects and outputs the smaller one of the two input values, and the output value and the switching frequency change maximum value “ ⁇ F SWmax ” are multiplied by the multiplication means 75 to change the switching frequency “ ⁇ F SW ”.
- the addition means 76 adds the switching frequency change " ⁇ F SW " and the minimum switching frequency "F SWmin " to obtain the switching frequency command value "F SW * ".
- the switching frequency F SW of the semiconductor switch 33 can be maximized.
- current I L ripple [Delta] I L can be controlled so that the switching frequency F SW when the normal mode noise is maximum is maximized in other words, per unit time it is possible to effectively reduce the normal mode noise by reducing the amount of change in ripple [Delta] I L. Therefore, even when the filter circuit 15 is provided as shown in FIG. 1, a small-sized, small-capacity one can be used as a reactor, a capacitor, etc., and there is no fear that the entire apparatus will be enlarged.
- the frequency subject to restriction of conducted noise is 150 [kHz] or more, and when the switching frequency is about 50 [kHz] to 70 [kHz], the frequency subject to restriction is three times or more the switching frequency. Therefore, if the third harmonic component to the switching frequency is suppressed, a large noise reduction effect may be obtained.
- Equation 2 The magnitude of the nth harmonic component of the ripple of the current I L flowing through the inductor 31 is expressed by Equation 2.
- FIG. 4 shows the relationship between the third harmonic component of the duty ratio D and the ripple [Delta] I L.
- the switching frequency command value F SW * is calculated in the control circuit 70 of FIG. 1 according to the block diagram shown in FIG. Note that FIG. 5 differs from FIG. 3 in the portion from the output side of the dividing means 71 to the constant multiplying means 77g, and the other configuration is the same as in FIG.
- division by the division unit 71 result (v in / v d) the first, second comparison means 77a, is input to the non-inverting input terminal of 77d.
- the first comparison means 77 a outputs a “High” level signal when v in / v d is larger than “1/3”, and the second comparison means 77 d has a v in / v d of “2 /”. If it is larger than 3 ", it outputs a" High "level signal.
- the output signal of the first comparing means 77a is inputted to the first switching means 77b, and when the output signal of the first comparing means 77a is at "High" level, "Low” on the "1/3" side.
- the output signal of the second comparing means 77d is inputted to the second switching means 77e, and when the output signal of the second comparing means 77d is at the "High” level, it is on the "1/3" side, In the case of the "Low” level, it is switched to the "0" side.
- two subtracting means 77c, 77f are connected in series, the division result by subtracting the output of the first switching means 77b from (v in / v d), the subtraction result from the second switching means 77e It is configured to subtract the output of. Then, the constant multiplying means 77g multiplies "6" by the output of the subtracting means 77f, and the multiplication result is inputted to the selector 74, and the subtracting means 73 subtracts the output of the constant multiplying means 77g from "2". A value is configured to be input to the selector 74.
- the configuration after the selector 74 is the same as that shown in FIG.
- the output of the subtraction means 77 f is v in / v d if v in / v d ⁇ 1/3 and if 1/3 ⁇ v in / v d ⁇ 2/3. It becomes v in / v d -1/3, and when v in / v d > 2/3, it becomes v in / v d -2/3.
- the outputs of the constant multiplication means 77g are “6 ⁇ (v in / v d )”, “6 ⁇ (v in / v d ⁇ 1 ⁇ 3)”, and “6 ⁇ (v in / v d ⁇ ,” respectively. 2/3).
- the output of the subtracting means 73 corresponding to the output of the constant multiplication means 77g are examples of the “2-6 ⁇ (v in / v d ) ", “2-6 ⁇ (v in / v d -1 / 3) ”,“ 2-6 ⁇ (v in / v d ⁇ 2/3) ”.
- the selector 74 compares “6 ⁇ (v in / v d )” with “2-6 ⁇ (v in / v d )” to select the smaller one, or “6 ⁇ (v in / v Select the smaller one by comparing d -1/3) and 2-6 ⁇ (v in / v d ⁇ 1/3), or “6 ⁇ (v in / v d ⁇ 2 / 3) Compare “2-6 ⁇ (v in / v d ⁇ 2/3)” with “3)” to select the smaller one and output it to the multiplication means 75.
- the switching frequency F SW of the semiconductor switch 33 can be maximized by adding this ⁇ F SW to the minimum switching frequency “F SWmin ”.
- the switching frequency F SW can be maximized when the third harmonic component of the ripple ⁇ I L of the current I L is maximum, the change amount of the ripple ⁇ I L per unit time can be reduced to reduce normal mode noise. It can be effectively reduced.
- FIG. 6 shows the relationship between the duty ratio D and the third harmonic component of ⁇ I L and the switching frequency F SW in the second embodiment, and the switching frequency F SW has a duty ratio D as shown in FIG.
- the desired noise reduction effect can be obtained by changing it in the shape of a triangular wave in accordance with.
- FIG. 7 (a) and 7 (b) are circuit diagrams showing the main parts of another embodiment of the present invention, in which 31a and 31b are alternately turned on and off by the control circuit, and 31a and 31b are alternately turned on and off.
- the semiconductor switches 34a, 34b, 34c and 34d are diodes.
- the feature of the present invention is that when the ripple of the current flowing through the inductor connected in series to the semiconductor switch is maximized, or when the third harmonic component of the ripple of the current flowing through the inductor is maximized, The purpose is to control the switching frequency so as to maximize the switching frequency.
- the first embodiment (FIG. 3) and the second embodiment (FIG. 5) of the control circuit are not limited to the circuit of FIG. 1, but power factor improvement of the configuration shown in FIGS. 7 (a) and 7 (b), for example It can also be applied to circuits.
- the present invention can be used, for example, in a step-up AC-DC converter that rectifies and boosts an AC power supply, in particular, a vehicle-mounted charger that charges a battery such as an electric vehicle using a commercial power supply.
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Abstract
Description
図8において、10は交流電源、20はダイオードブリッジからなる全波整流回路、31はインダクタ、32は電流検出抵抗、33は半導体スイッチ、34は整流用ダイオード、35は平滑コンデンサ、40は負荷である。ここで、インダクタ31、半導体スイッチ33、整流用ダイオード34及び平滑コンデンサ35は昇圧チョッパを構成しており、半導体スイッチ33のオン、オフによりインダクタ31へのエネルギーの蓄積、放出を繰り返し、平滑コンデンサ35の電圧を全波整流回路20の出力電圧よりも高い直流電圧に昇圧して負荷40に供給する。
同時に、VCO55の作用により、図9に示すごとく、交流電源電圧vinの大きさに比例させて半導体スイッチ33のスイッチング周波数fを変化させることにより、スイッチングに伴って発生するノーマルモードノイズを周波数に対して分散させ、ノイズやスイッチング損失を低減させている。
コンパレータ56は、上記の三角波信号と、誤差増幅器54から出力されるフィードバック信号FBとを比較して図11(a),(b)の下段に示すPWMパルスを生成し、このPWMパルスによって半導体スイッチ33をスイッチングしている。
しかしながら、この従来技術は、単純に交流電源電圧vinの大きさに比例させてスイッチング周波数fを変化させるという着想に基づいている。従って、交流電源電圧vinの大きさによってはノイズ低減効果が十分に得られない恐れがあり、所定の伝導ノイズ規制をクリアするためにノーマルモードコイル等を備えた大型のフィルタ回路を併用せざるを得ないという問題があった。
前記半導体スイッチのスイッチング動作により前記回路の入力側の力率を改善する力率改善回路において、
前記半導体スイッチのスイッチング周波数を可変とする制御回路を備え、
前記制御回路は、前記インダクタを流れる電流のリプルが最大となる時に前記スイッチング周波数が最大になるように前記スイッチング周波数を制御するものである。
前記半導体スイッチのスイッチング動作により前記整流回路の入力側の力率を改善する力率改善回路において、
前記半導体スイッチのスイッチング周波数を可変とする制御回路を備え、
前記制御回路は、前記インダクタを流れる電流のリプルが最大となる時に前記スイッチング周波数が最大になるように前記スイッチング周波数を制御するものである。
前記半導体スイッチのスイッチング動作により前記回路の入力側の力率を改善する力率改善回路において、
前記半導体スイッチのスイッチング周波数を可変とする制御回路を備え、
前記制御回路は、前記インダクタを流れる電流のリプルの3次高調波成分が最大となる時に前記スイッチング周波数が最大になるように前記スイッチング周波数を制御するものである。
前記半導体スイッチのスイッチング動作により前記整流回路の入力側の力率を改善する力率改善回路において、
前記半導体スイッチのスイッチング周波数を可変とする制御回路を備え、
前記制御回路は、前記インダクタを流れる電流のリプルの3次高調波成分が最大となる時に前記スイッチング周波数が最大になるように前記スイッチング周波数を制御するものである。
図1において、10は交流電源、15はリアクトルやコンデンサ等からなるフィルタ回路、20はダイオードブリッジからなる全波整流回路、31はインダクタ(昇圧リアクトル)、32は電流検出抵抗、33はMOSFET等の半導体スイッチ、34は整流用ダイオード、35は平滑コンデンサ、40は負荷である。前記同様に、インダクタ31、半導体スイッチ33、整流用ダイオード34及び平滑コンデンサ35は昇圧チョッパを構成しており、半導体スイッチ33のオン、オフによりインダクタ31へのエネルギーの蓄積、放出を繰り返し、平滑コンデンサ35の電圧を全波整流回路20の出力電圧よりも高い直流電圧に昇圧して負荷40に供給する。
これらの検出回路61,62,63の出力は、電圧制御、電流制御及びPWM制御を実行するマイコン等の制御回路70に入力されている。また、制御回路70からは駆動回路にPWMパルスが入力されており、駆動回路80はこのPWMパルスに基づいて半導体スイッチ33をオン、オフするように構成されている。
そこで、本発明の第1実施例では、図1の制御回路70において、図3に示すブロック図によりスイッチング周波数指令値FSW *を演算することとした。
このスイッチング周波数指令値「FSW *」に基づいてPWM制御に用いるキャリア波の周波数を変化させることにより、図1における半導体スイッチ33のスイッチング周波数FSWを変化させる。
図3(a)の構成によってスイッチング周波数FSWを制御することにより、vin/vd=0.5の時にセレクタ74の出力は常に「1」となり、ΔFSW=ΔFSWmaxとなる。このΔFSWを最小スイッチング周波数「FSWmin」に加算することにより、半導体スイッチ33のスイッチング周波数FSWを最大化することができる。
なお、スイッチング周波数指令値FSW *を決定するに当たっては、半導体スイッチ33の定格やスイッチング損失等を勘案する必要があるのは言うまでもない。
よって、図1に示したようにフィルタ回路15を設ける場合でも、リアクトルやコンデンサ等に小型かつ小容量の物を用いることができ、装置全体が大型化するおそれがない。
伝導ノイズの規制対象となる周波数は150[kHz]以上であり、スイッチング周波数を50[kHz]~70[kHz]程度にする場合、規制対象となる周波数はスイッチング周波数の3倍以上となる。このため、スイッチング周波数に対する3次高調波成分を抑制すれば、大きなノイズ低減効果が得られることがある。
ここで、前述した数式1により、TON/TSW=(vd-vin)/vd=デューティ比Dであるから、「デューティ比D=1/6,3/6,5/6の時」とは、「(vd-vin)/vd=1/6,3/6,5/6の時、言い換えれば、vin/vd=5/6,3/6,1/6の時」に等しい。
第1の比較手段77aの出力信号は第1の切替手段77bに入力されており、第1の比較手段77aの出力信号が「High」レベルの場合には「1/3」側に、「Low」レベルの場合には「0」側に切り替わる。また、第2の比較手段77dの出力信号は第2の切替手段77eに入力されており、第2の比較手段77dの出力信号が「High」レベルの場合には「1/3」側に、「Low」レベルの場合には「0」側に切り替わる。
このため、定数乗算手段77gの出力は、それぞれ「6×(vin/vd)」,「6×(vin/vd-1/3)」,「6×(vin/vd-2/3)」となる。また、これらの定数乗算手段77gの出力に応じた減算手段73の出力は、それぞれ、「2-6×(vin/vd)」,「2-6×(vin/vd-1/3)」,「2-6×(vin/vd-2/3)」となる。
セレクタ74は、「6×(vin/vd)」と「2-6×(vin/vd)」とを比較して小さい方を選択し、または、「6×(vin/vd-1/3)」と「2-6×(vin/vd-1/3)」とを比較して小さい方を選択し、または、「6×(vin/vd-2/3)」と「2-6×(vin/vd-2/3)」とを比較して小さい方を選択して乗算手段75に出力する。
つまり、電流ILのリプルΔILの3次高調波成分が最大の時にスイッチング周波数FSWを最大化することができるので、単位時間当たりのリプルΔILの変化量を少なくしてノーマルモードノイズを効果的に低減することができる。
本発明の特徴は、半導体スイッチに直列に接続されたインダクタを流れる電流のリプルが最大となる時に、または、上記インダクタを流れる電流のリプルの3次高調波成分が最大となる時に、半導体スイッチのスイッチング周波数が最大になるようにスイッチング周波数を制御することにある。このため、制御回路の第1実施例(図3)や第2実施例(図5)は、図1の回路に限らず、例えば図7(a),(b)に示す構成の力率改善回路にも適用することができる。
15:フィルタ回路
20:全波整流回路
31:インダクタ(昇圧リアクトル)
31a,31b:インダクタ
32:電流検出抵抗
33:半導体スイッチ
33a,33b:半導体スイッチ
34:ダイオード
34a,34b,34c,34d:ダイオード
35:平滑コンデンサ
40:負荷
61:入力電圧検出回路
62:電流検出回路
63:出力電圧検出回路
70:制御回路
71:除算手段
72:定数乗算手段
73:減算手段
74:セレクタ
75:乗算手段
76:加算手段
77a,77d:比較手段
77b,77e:切替手段
77c,77f:減算手段
77g:定数乗算手段
80:駆動回路
Claims (9)
- 交流電源の出力端子間に、インダクタと半導体スイッチとを含む直列回路が接続され、 前記半導体スイッチの両端に、ダイオードと平滑コンデンサとの直列回路が接続され、前記平滑コンデンサの両端に負荷が接続される回路であって、
前記半導体スイッチのスイッチング動作により前記回路の入力側の力率を改善する力率改善回路において、
前記半導体スイッチのスイッチング周波数を可変とする制御回路を備え、
前記制御回路は、前記インダクタを流れる電流のリプルが最大となる時に前記スイッチング周波数が最大になるように前記スイッチング周波数を制御することを特徴とする力率改善回路。 - 交流電源電圧を整流する整流回路と、前記整流回路の出力端子間に接続されるインダクタと半導体スイッチとの直列回路と、前記半導体スイッチの両端に接続されるダイオードと平滑コンデンサとの直列回路と、を備え、前記平滑コンデンサの両端に負荷が接続される回路であって、
前記半導体スイッチのスイッチング動作により前記整流回路の入力側の力率を改善する力率改善回路において、
前記半導体スイッチのスイッチング周波数を可変とする制御回路を備え、
前記制御回路は、前記インダクタを流れる電流のリプルが最大となる時に前記スイッチング周波数が最大になるように前記スイッチング周波数を制御することを特徴とする力率改善回路。 - 請求項1または2に記載した力率改善回路において、
交流電源電圧を入力電圧として検出する電圧検出回路と、前記平滑コンデンサの両端電圧を出力電圧として検出する電圧検出回路と、を備え、
前記制御回路は、前記出力電圧に対する前記入力電圧の比に基づき前記リプルが最大となる時を検出して前記スイッチング周波数を最大値に制御することを特徴とする力率改善回路。 - 請求項3に記載した力率改善回路において、
前記制御回路は、前記出力電圧に対する前記入力電圧の比が0.5である時に前記リプルが最大であることを検出することを特徴とする力率改善回路。 - 交流電源の出力端子間に、インダクタと半導体スイッチとを含む直列回路が接続され、前記半導体スイッチの両端に、ダイオードと平滑コンデンサとの直列回路が接続され、前記平滑コンデンサの両端に負荷が接続される回路であって、
前記半導体スイッチのスイッチング動作により前記回路の入力側の力率を改善する力率改善回路において、
前記半導体スイッチのスイッチング周波数を可変とする制御回路を備え、
前記制御回路は、前記インダクタを流れる電流のリプルの3次高調波成分が最大となる時に前記スイッチング周波数が最大になるように前記スイッチング周波数を制御することを特徴とする力率改善回路。 - 交流電源電圧を整流する整流回路と、前記整流回路の出力端子間に接続されるインダクタと半導体スイッチとの直列回路と、前記半導体スイッチの両端に接続されるダイオードと平滑コンデンサとの直列回路と、を備え、前記平滑コンデンサの両端に負荷が接続される回路であって、
前記半導体スイッチのスイッチング動作により前記整流回路の入力側の力率を改善する力率改善回路において、
前記半導体スイッチのスイッチング周波数を可変とする制御回路を備え、
前記制御回路は、前記インダクタを流れる電流のリプルの3次高調波成分が最大となる時に前記スイッチング周波数が最大になるように前記スイッチング周波数を制御することを特徴とする力率改善回路。 - 請求項5または6に記載した力率改善回路において、
交流電源電圧を入力電圧として検出する電圧検出回路と、前記平滑コンデンサの両端電圧を出力電圧として検出する電圧検出回路と、を備え、
前記制御回路は、前記出力電圧に対する前記入力電圧の比に基づき前記リプルの3次高調波成分が最大となる時を検出して前記スイッチング周波数を最大値に制御することを特徴とする力率改善回路。 - 請求項7に記載した力率改善回路において、
前記制御回路は、前記出力電圧に対する前記入力電圧の比が5/6または3/6または1/6である時に前記リプルの3次高調波成分が最大であることを検出することを特徴とする力率改善回路。 - 請求項7に記載した力率改善回路において、
前記制御回路は、前記半導体スイッチをスイッチングするパルスのデューティ比が1/6または3/6または5/6である時に前記リプルの3次高調波成分が最大であることを検出することを特徴とする力率改善回路。
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