WO2010052962A1 - アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 - Google Patents
アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 Download PDFInfo
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- WO2010052962A1 WO2010052962A1 PCT/JP2009/064488 JP2009064488W WO2010052962A1 WO 2010052962 A1 WO2010052962 A1 WO 2010052962A1 JP 2009064488 W JP2009064488 W JP 2009064488W WO 2010052962 A1 WO2010052962 A1 WO 2010052962A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
- G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
Definitions
- the present invention relates to an active matrix substrate in which a plurality of pixel electrodes are provided in one pixel region, and a liquid crystal display device (pixel division method) using the same.
- a plurality of subpixels provided in one pixel are controlled to have different luminances, and the area level of these subpixels.
- a liquid crystal display device pixel division method, for example, see Patent Document 1 that displays a halftone by a tone.
- two pixel electrodes 190a and 190b are arranged in one pixel region, the source electrode 178 of the transistor is connected to the data line 171 and the drain electrode 175 is in contact.
- the pixel electrode 190a is connected through a hole 185.
- the coupling electrode 176 is connected to the drain electrode 175 of the transistor through the extension portion 177.
- the coupling electrode 176 and the pixel electrode 190b overlap each other, and a coupling capacitor is formed in this overlapping portion (capacitive coupling type pixel division method).
- the sub-pixel corresponding to the pixel electrode 190a can be a bright sub-pixel
- the sub-pixel corresponding to the pixel electrode 190b can be a dark sub-pixel.
- a halftone can be displayed according to the area gradation of the pixel.
- Japanese Patent Publication Japanese Patent Laid-Open No. 2006-221174 (Publication Date: August 24, 2006)”
- An object of the present invention is to increase the aperture ratio of an active matrix substrate of a capacitively coupled pixel division type.
- the active matrix substrate of the present invention includes a first pixel electrode connected to a data signal line through a transistor and a second pixel electrode connected to the first pixel electrode through a capacitor in one pixel region.
- An active matrix substrate provided, comprising: a first capacitor electrode electrically connected to the second pixel electrode; and a second capacitor electrode electrically connected to the first pixel electrode, wherein the second capacitor The electrode is disposed in a layer between the first capacitor electrode and the second pixel electrode, and the first capacitor electrode and the second capacitor are overlapped with each other via the first insulating film.
- a capacitor is formed between the electrodes, and a capacitor is formed between the second capacitor electrode and the second pixel electrode by overlapping the second capacitor electrode and the second pixel electrode with the second insulating film interposed therebetween.
- two coupling capacitors (a capacitor formed between the first capacitor electrode and the second capacitor electrode, and a capacitor formed between the second capacitor electrode and the second pixel electrode) in the thickness direction of the substrate.
- the two coupling capacitors can be formed in parallel, and the first and second pixel electrodes can be connected via the two parallel coupling capacitors. Therefore, the area of the second capacitor electrode is reduced without changing the value of the coupling capacitance, thereby increasing the aperture ratio, or without changing the area of the second capacitor electrode (that is, without changing the aperture ratio). Can be increased.
- the second pixel electrode and the first capacitor electrode may be connected by a contact hole that penetrates the first and second insulating films.
- One conductive electrode of the transistor and the first pixel electrode are connected via a contact hole, and the first pixel electrode and the second capacitor electrode are connected via a contact hole different from the contact hole. It can also be configured.
- the active matrix substrate of the present invention includes a first pixel electrode connected to a data signal line via a transistor in one pixel region, and a second pixel electrode connected to the first pixel electrode via a capacitor.
- An active matrix substrate provided with a first capacitor electrode electrically connected to the first pixel electrode, and a second capacitor electrode electrically connected to the second pixel electrode, The second capacitor electrode is disposed in a layer between the first capacitor electrode and the first pixel electrode, and the first capacitor electrode and the second capacitor electrode overlap with each other with the first insulating film interposed therebetween.
- a capacitor is formed between the second capacitor electrode and the second capacitor electrode.
- the capacitor is formed between the second capacitor electrode and the first pixel electrode by overlapping the second capacitor electrode and the first pixel electrode via the second insulating film. It is characterized by that.
- two coupling capacitors (a capacitor formed between the first capacitor electrode and the second capacitor electrode and a capacitor formed between the second capacitor electrode and the first pixel electrode) in the thickness direction of the substrate.
- the two coupling capacitors can be formed in parallel, and the first and second pixel electrodes can be connected via the two parallel coupling capacitors. Therefore, the area of the second capacitor electrode is reduced without changing the value of the coupling capacitance, thereby increasing the aperture ratio, or without changing the area of the second capacitor electrode (that is, without changing the aperture ratio). Can be increased.
- the first pixel electrode and the first capacitor electrode may be connected by a contact hole penetrating the first and second insulating films.
- the first capacitor electrode may be formed in the same layer as the scanning signal line.
- the second capacitor electrode may be formed in the same layer as the data signal line.
- the thickness of the second insulating film may be equal to or less than the thickness of the first insulating film.
- the first insulating film may be a gate insulating film.
- the second insulating film may be an interlayer insulating film that covers the channel of the transistor.
- the first capacitor electrode has two parallel edges
- the second capacitor electrode also has two parallel edges.
- both of the second capacitor electrodes It is also possible to adopt a configuration in which both edges of the first capacitor electrode are located inside the edge.
- the first capacitor electrode has two parallel edges, and the second capacitor electrode also has two parallel edges.
- both the first capacitor electrodes It is also possible to adopt a configuration in which both edges of the second capacitor electrode are located inside the edge.
- the present active matrix substrate may be configured to include a storage capacitor wiring that overlaps each of the first and second pixel electrodes.
- the active matrix substrate includes, in one pixel region, a first pixel electrode electrically connected to the transistor, a second pixel electrode, a first capacitor electrode electrically connected to the second pixel electrode, A second capacitor electrode electrically connected to the transistor, and the second capacitor electrode is disposed in a layer between the first capacitor electrode and the second pixel electrode, and the first capacitor electrode and the second capacitor A capacitance is formed between the first capacitor electrode and the second capacitor electrode by overlapping the electrode via the first insulating film, and the second capacitor electrode and the second pixel electrode are overlapped via the second insulating film. A capacitor is formed between the second capacitor electrode and the second pixel electrode.
- the above configuration may include a third capacitance electrode connected in the same layer as the second capacitance electrode, and a storage capacitance wiring that forms a capacitance with the third capacitance electrode.
- This liquid crystal panel includes the above active matrix substrate.
- the present liquid crystal panel includes the above active matrix substrate and a counter substrate having alignment regulating linear protrusions, and at least a part of the first capacitor electrode is arranged below the linear protrusions. You can also The liquid crystal panel includes the active matrix substrate and a counter substrate having a common electrode (counter electrode).
- the common electrode is provided with a slit for regulating alignment, and at least a part of the first capacitor electrode. It can also be set as the structure arrange
- This liquid crystal display unit includes the liquid crystal panel and a driver.
- the present liquid crystal display device includes the liquid crystal display unit and a light source device.
- a television receiver includes the liquid crystal display device and a tuner unit that receives a television broadcast.
- two coupling capacitances are formed in the thickness direction of the substrate, the two coupling capacitances are paralleled, and the first and second pixel electrodes are arranged in parallel.
- the area of the second capacitor electrode can be reduced without changing the value of the coupling capacitance to increase the aperture ratio, or the area of the second capacitor electrode can be increased without changing the area of the second capacitor electrode (that is, without changing the aperture ratio). The value can be increased.
- FIG. 2 is a cross-sectional view of the liquid crystal panel of FIG. 3 is a timing chart illustrating a driving method of a liquid crystal display device including the liquid crystal panel of FIG. 1.
- FIG. 5 is a schematic diagram showing a display state for each frame when the driving method of FIG. 4 is used. It is a top view which shows the correction method of the liquid crystal panel of FIG.
- FIG. 7 is a cross-sectional view of the liquid crystal panel of FIG. It is a top view which shows the modification of the liquid crystal panel shown in FIG. It is a top view which shows the other structure of this liquid crystal panel.
- FIG. 1 is a cross-sectional view of the liquid crystal panel of FIG. 3 is a timing chart illustrating a driving method of a liquid crystal display device including the liquid crystal panel of FIG. 1.
- FIG. 5 is a schematic diagram showing a display state for each frame when the driving method of FIG. 4 is used. It is a top view which shows the correction method of the liquid crystal panel of FIG.
- FIG. 7
- FIG. 10 is a cross-sectional view of the liquid crystal panel of FIG. It is a top view which shows the modification of the liquid crystal panel shown in FIG. It is arrow sectional drawing of the liquid crystal panel of FIG. It is a top view which shows the modification of the liquid crystal panel shown in FIG. It is arrow sectional drawing of the liquid crystal panel of FIG. It is a top view which shows the modification of the liquid crystal panel shown in FIG. It is arrow sectional drawing of the liquid crystal panel of FIG. It is a top view which shows the modification of the liquid crystal panel shown in FIG. It is a top view which shows the other modification of the liquid crystal panel shown in FIG. It is a top view which shows the further another modification of the liquid crystal panel shown in FIG. It is a top view which shows the other modification of the liquid crystal panel shown in FIG.
- FIG. 16 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 15. FIG.
- FIG. 10 is a plan view illustrating still another modification example of the liquid crystal panel illustrated in FIG. 8.
- FIG. 21 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 20.
- FIG. 10 is a plan view illustrating another modification of the liquid crystal panel illustrated in FIG. 9. It is a top view which shows other structure of this liquid crystal panel.
- FIG. 24 is a plan view showing a modification of the liquid crystal panel shown in FIG. 23.
- FIG. 24 is a plan view showing another modification of the liquid crystal panel shown in FIG. 23.
- FIG. 27 is a plan view illustrating a specific example of the liquid crystal panel illustrated in FIG. 26.
- FIG. 26 is a block diagram illustrating functions of the present television receiver. It is a disassembled perspective view which shows the structure of this television receiver. It is a top view which shows the other structural example of this liquid crystal panel.
- FIG. 35 is a cross-sectional view of the liquid crystal panel of FIG. It is a top view which shows the structure of the conventional liquid crystal panel.
- the extending direction of the scanning signal lines is hereinafter referred to as the row direction.
- the scanning signal line may extend in the horizontal direction or in the vertical direction. Needless to say, it is good.
- alignment regulating structures for example, slits formed on the pixel electrodes of the active matrix substrate and ribs formed on the color filter substrate
- FIG. 2 is an equivalent circuit diagram showing a part of the liquid crystal panel (for example, normally black mode) according to the present embodiment.
- this liquid crystal panel includes data signal lines 15x and 15y extending in the column direction (up and down direction in the figure), scanning signal lines 16x and 16y extending in the row direction (left and right direction in the figure), rows, and
- Each pixel includes the pixels (101 to 104) arranged in the column direction, the storage capacitor lines 18p and 18q, and the common electrode (counter electrode) com, and the structure of each pixel is the same.
- the pixel column including the pixels 101 and 102 and the pixel column including the pixels 103 and 104 are adjacent to each other, and the pixel row including the pixels 101 and 103 and the pixel row including the pixels 102 and 104 are adjacent to each other. is doing.
- one data signal line, one scanning signal line, and one storage capacitor line are provided corresponding to one pixel, and two pixel electrodes are arranged in the column direction in one pixel. It has been.
- the pixel electrode 17a is connected to the data signal line 15x via the transistor 12a connected to the scanning signal line 16x, and the pixel electrode 17a and the pixel electrode 17b are connected via the coupling capacitors Cab1 and Cab2.
- a storage capacitor Cha is formed between the pixel electrode 17a and the storage capacitor line 18p
- a storage capacitor Chb is formed between the pixel electrode 17b and the storage capacitor line 18p
- the pixel electrode 17a and the common electrode com are between.
- a liquid crystal capacitor Cla is formed, and a liquid crystal capacitor Clb is formed between the pixel electrode 17b and the common electrode com.
- the coupling capacitors Cab1 and Cab2 are parallel.
- the pixel electrode 17a is connected to the data signal line 15x (via the transistor 12a).
- the pixel electrode 17a and the pixel electrode 17b are coupled via the coupling capacitors Cab1 and Cab2
- the potential of the pixel electrode 17a after the transistor 12a is turned off is Va, and the pixel electrode after the transistor 12a is turned off.
- FIG. 1 shows a specific example of the pixel 101 in FIG.
- members on the color filter substrate (counter substrate) side are omitted, and only members of the active matrix substrate are shown.
- a transistor 12a is arranged near the intersection of the data signal line 15x and the scanning signal line 16x, the source electrode 8 of the transistor 12a is connected to the data signal line 15x, and the gate electrode of the transistor 12a is scanned.
- the signal electrode 16x also serves as the drain electrode 9 of the transistor 12a is connected to the drain lead electrode 27, and the pixel electrode 17a (first pixel electrode) adjacent to the transistor 12a is formed in the pixel region defined by both signal lines (15x and 16x).
- the pixel electrode 17b (second pixel electrode) are arranged in the column direction.
- the drain lead electrode 27 is connected to the pixel electrode 17a through the contact hole 11a and is connected to the upper capacitor electrode 37 (second capacitor electrode) of the same layer, and the upper capacitor electrode 37 overlaps the pixel electrode 17b. So that it is stretched. Further, a lower capacitor electrode 77 (first capacitor electrode) is provided so as to overlap with the upper capacitor electrode 37 and the pixel electrode 17b, and the lower capacitor electrode 77 is connected to the pixel electrode 17b through a contact hole 11f.
- the upper-layer capacitor electrode 37 has two edges along the column direction below the pixel electrode 17b, and the lower-layer capacitor electrode 77 also has two edges along the column direction below the pixel electrode 17b. When viewed in plan, both edges of the lower layer capacitor electrode 77 are located inside both edges of the upper layer capacitor electrode 37.
- the lower layer capacitor electrode 77 is formed in the same layer as the scanning signal line 16x
- the upper layer capacitor electrode 37 is formed in the same layer as the data signal line 15x
- the lower layer capacitor electrode 77, the upper layer capacitor electrode 37, and the pixel electrode 17b In the overlapping portion, a gate insulating film is disposed between the lower capacitive electrode 77 and the upper capacitive electrode 37, and an interlayer insulating film is disposed between the upper capacitive electrode 37 and the pixel electrode 17b.
- a coupling capacitor Cab1 is formed at the overlapping portion between the lower layer capacitive electrode 77 and the upper layer capacitive electrode 37
- a coupling capacitor Cab2 is formed at the overlapping portion between the upper layer capacitive electrode 37 and the pixel electrode 17b. Is formed.
- a storage capacitor line 18p is arranged so as to cross the pixel region, and the storage capacitor line 18p overlaps with the pixel electrode 17a and the pixel electrode 17b through the gate insulating film and the interlayer insulating film.
- the storage capacitor Cha (see FIG. 2) is formed at the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17a
- the storage capacitor Chb (see FIG. 2) is formed at the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17b. It is formed.
- FIG. 3 is a cross-sectional view taken along the line XY in FIG.
- the present liquid crystal panel includes an active matrix substrate 3, a color filter substrate 30 facing the active matrix substrate 3, and a liquid crystal layer 40 disposed between both substrates (3, 30).
- the scanning signal line 16x, the storage capacitor line 18p, and the lower layer capacitor electrode 77 are formed on the glass substrate 31, and the gate insulating film 22 is formed so as to cover them.
- a drain lead electrode 27 and an upper capacitor electrode 37 are formed on the upper layer of the gate insulating film 22 .
- a semiconductor layer i layer and n + layer
- a source electrode 8 and a drain electrode 9 in contact with the n + layer, and a data signal line 15x are formed in the upper layer of the gate insulating film 22.
- an interlayer insulating film 25 (inorganic interlayer insulating film) is formed so as to cover the metal layer.
- Pixel electrodes 17a and 17b are formed on the interlayer insulating film 25, and an alignment film 7 is formed so as to cover the pixel electrodes.
- the contact hole 11a the interlayer insulating film 25 is penetrated, whereby the pixel electrode 17a and the upper capacitor electrode 37 are connected.
- the gate insulating film 22 and the interlayer insulating film 25 are penetrated, whereby the pixel electrode 17b and the lower-layer capacitor electrode 77 are connected.
- the lower capacitive electrode 77 overlaps the upper capacitive electrode 37 with the gate insulating film 22 interposed therebetween, and the coupling capacitance Cab1 (see FIG. 2) is formed in the overlapping portion of both (77, 37).
- the upper capacitor electrode 37 overlaps the pixel electrode 17b with the interlayer insulating film 25 interposed therebetween, and a coupling capacitor Cab2 (see FIG. 2) is formed at the overlapping portion of both (37, 17b).
- the storage capacitor line 18p overlaps the pixel electrode 17a via the gate insulating film 22 and the interlayer insulating film 25, and a storage capacitor Cha (see FIG. 2) is formed at the overlapping portion of both (18p, 17a). .
- the storage capacitor line 18p overlaps the pixel electrode 17b through the gate insulating film 22 and the interlayer insulating film 25, and the storage capacitor Chb (see FIG. 2) is formed at the overlapping portion of both (18p and 17b).
- the material and thickness of the gate insulating film 22 and the material and thickness of the interlayer insulating film 25 are the function of the gate insulating film 22 as a gate insulating film, the function of the interlayer insulating film 25 as a channel protective film of the transistor, and It may be determined in consideration of the value of the required coupling capacity.
- silicon nitride (SiNx) is used for each of the gate insulating film 22 and the interlayer insulating film 25, and the interlayer insulating film 25 is formed thinner than the gate insulating film 22.
- a colored layer (color filter layer) 14 is formed on a glass substrate 32, a common electrode (com) 28 is formed thereon, and an alignment film 19 is formed so as to cover this. ing.
- FIG. 4 is a timing chart showing a driving method of the present liquid crystal display device (normally black mode liquid crystal display device) provided with the liquid crystal panel shown in FIGS.
- Sv and SV indicate signal potentials supplied to the data signal lines 15x and 15y (see FIG. 2)
- Gx and Gy indicate gate-on pulse signals supplied to the scanning signal lines 16x and 16y
- Va Vd represents the potentials of the pixel electrodes 17a to 17d
- VA and AB represent the potentials of the pixel electrodes 17A and 17B, respectively.
- the scanning signal lines are sequentially selected, the polarity of the signal potential supplied to the data signal lines is inverted every horizontal scanning period (1H), and the same number in each frame.
- the polarity of the signal potential supplied in the horizontal scanning period is inverted in units of one frame, and in the same horizontal scanning period, a signal potential having a reverse polarity is supplied to two adjacent data signal lines.
- scanning signal lines are sequentially selected, and one of the two adjacent data signal lines has a first horizontal scanning period (for example, the pixel electrode 17a).
- a positive polarity signal potential is supplied during the second horizontal scanning period, a negative polarity signal potential is supplied during the second horizontal scanning period, and the other of the two data signal lines is negative during the first horizontal scanning period.
- a polar signal potential is supplied, and a positive polarity signal potential is supplied in the second horizontal scanning period.
- As a result, as shown in FIG. 4,
- the subpixel including the pixel electrode 17a is a bright subpixel (hereinafter, “bright”).
- a sub-pixel including the pixel electrode 17b (positive polarity) includes a dark sub-pixel (hereinafter “dark”)
- a sub-pixel including the pixel electrode 17c (negative polarity) includes “bright” and a pixel electrode 17d (negative polarity).
- the sub-pixel is “dark”, and the whole is as shown in FIG.
- the scanning signal line is sequentially selected, and a negative polarity signal potential is applied to one of the two adjacent data signal lines in the first horizontal scanning period (for example, the writing period of the pixel electrode 17a).
- a positive polarity signal potential is supplied during the second horizontal scanning period, and a positive polarity signal potential is supplied during the first horizontal scanning period to the other of the two data signal lines.
- a negative-polarity signal potential is supplied during the horizontal scanning period. Accordingly, as shown in FIG.
- each pixel electrode is provided with an alignment regulating slit, and a color filter
- the substrate is provided with orientation regulating ribs.
- an orientation regulating slit may be provided in the common electrode of the color filter substrate.
- the coupling capacitance Cab1 (coupling capacitance of the overlapping portion of the lower layer capacitance electrode 77 and the upper layer capacitance electrode 37) and Cab2 (coupling capacitance of the overlapping portion of the upper layer capacitance electrode 37 and the pixel electrode 17b).
- the coupling capacitors Cab1 and Cab2 are parallelized, and the pixel electrodes 17a and 17b can be connected via the paralleled coupling capacitors Cab1 and Cab2. Therefore, the aperture ratio is improved by reducing the area of the upper capacitive electrode 37 without changing the value of the coupling capacitance, or the coupling capacitance value is changed without changing the area of the upper capacitive electrode 37 (without changing the aperture ratio). It can be enlarged.
- silicon nitride SiNx
- the interlayer insulating film 25 is formed thinner than the gate insulating film 22.
- the thickness of the gate insulating film 22 has a great influence on the transistor characteristics, and it is not preferable to greatly change the thickness because of the above effects such as improving the aperture ratio or increasing the value of the coupling capacitance.
- the thickness of the interlayer insulating film 25 channel protective film
- the thickness of the interlayer insulating film 25 is set to be smaller than that of the gate insulating film 22 as in the present liquid crystal panel. It is preferable to make it small.
- both edges of the lower layer capacitor electrode 77 are located inside both edges of the upper layer capacitor electrode 37, the lower layer capacitor electrode 77 and the upper layer capacitor electrode 37 are aligned. Even if it deviates in the direction, the coupling capacitance value hardly changes (strong against misalignment).
- it can be configured such that both edges of the upper capacitor electrode 37 are positioned inside both edges of the lower capacitor electrode 77.
- the width of the upper capacitor electrode 37 that forms the coupling capacitance with both the pixel electrode 17b is increased, the above-described effect of improving the aperture ratio or increasing the value of the coupling capacitance can be further enhanced.
- the pixel electrode 17a and the pixel electrode 17b are short-circuited.
- the pixel electrode 17b By trimming and removing the portion in the contact hole 11f, the short circuit can be corrected while leaving the coupling capacitance Cab2 (coupling capacitance between the upper layer capacitive electrode 37 and the pixel electrode 17b).
- the method for manufacturing a liquid crystal panel includes an active matrix substrate manufacturing process, a color filter substrate manufacturing process, and an assembly process in which both substrates are bonded to each other and filled with liquid crystal.
- a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, or copper, an alloy film thereof, or a laminated film thereof (thickness: 1000 mm to 3000 mm) is sputtered onto a substrate such as glass or plastic. Then, patterning is performed by a photolithography technique (Photo Engraving Process, referred to as “PEP technique”) to form a scanning signal line (gate electrode of a transistor), a storage capacitor wiring, and a lower layer capacitor electrode.
- PEP technique Photo Engraving Process
- an inorganic insulating film such as silicon nitride or silicon oxide is formed on the entire substrate on which the scanning signal lines and the like are formed by a CVD (Chemical Vapor Deposition) method to form a gate insulating film.
- CVD Chemical Vapor Deposition
- an intrinsic amorphous silicon film (thickness 1000 to 3000 mm) and an n + amorphous silicon film (thickness 400 to 700 mm) doped with phosphorus are continuously formed on the gate insulating film (whole substrate) by CVD.
- patterning is performed by the PEP technique, and a silicon laminated body including an intrinsic amorphous silicon layer and an n + amorphous silicon layer is formed in an island shape on the gate electrode.
- a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, or copper, an alloy film thereof, or a stacked film thereof (thickness 1000 to 3000 mm) is formed on the entire substrate on which the silicon laminate is formed. Then, patterning is performed by a PEP technique to form data signal lines, transistor source / drain electrodes, drain lead electrodes, and upper capacitor electrodes (formation of a metal layer).
- the n + amorphous silicon layer constituting the silicon stacked body is removed by etching to form a transistor channel.
- the semiconductor layer may be formed of an amorphous silicon film as described above.
- a polysilicon film may be formed, or a laser annealing treatment is performed on the amorphous silicon film and the polysilicon film to form a crystal. May be improved. Thereby, the moving speed of the electrons in the semiconductor layer is increased, and the characteristics of the transistor (TFT) can be improved.
- an inorganic insulating film such as silicon nitride or silicon oxide is formed by CVD on the entire substrate on which the data signal lines and the like are formed, thereby forming an interlayer insulating film.
- the PEP technique is used to etch away the interlayer insulating film or the interlayer insulating film and the gate insulating film to form a contact hole.
- the interlayer insulating film is removed at the location where the contact hole 11a is formed in FIGS. 1 and 3, and the interlayer insulating film and the gate insulating film are removed at the location where the contact hole 11f is formed.
- a transparent conductive film (thickness 1000 to 2000 mm) made of ITO (Indium / Tin / Oxide), IZO (Indium / Zinc / Oxide), zinc oxide, tin oxide or the like is formed on the entire substrate on the interlayer insulating film in which the contact holes are formed. Is formed by sputtering, and then patterned by PEP technology to form each pixel electrode.
- polyimide resin is printed on the entire substrate on the pixel electrode with a thickness of 500 to 1000 mm, and then fired and rubbed in one direction with a rotating cloth to form an alignment film.
- the active matrix substrate is manufactured as described above.
- the color filter substrate manufacturing process will be described below.
- a chromium thin film or a resin containing a black pigment is formed on a glass or plastic substrate (entire substrate), and then patterned by PEP technology to form a black matrix.
- red, green and blue color filter layers are formed in a pattern in the gap of the black matrix by using a pigment dispersion method or the like.
- a transparent conductive film made of ITO, IZO, zinc oxide, tin oxide or the like is formed on the entire substrate on the color filter layer to form a common electrode (com).
- polyimide resin is printed on the entire substrate on the common electrode with a thickness of 500 to 1000 mm, and then fired and rubbed in one direction with a rotating cloth to form an alignment film.
- a color filter substrate can be manufactured as described above.
- a seal material made of a thermosetting epoxy resin or the like is applied to one of the active matrix substrate and the color filter substrate by screen printing in a frame-like pattern lacking the liquid crystal inlet portion, and the liquid crystal layer is applied to the other substrate.
- a spherical spacer having a diameter corresponding to the thickness and made of plastic or silica is dispersed.
- the active matrix substrate and the color filter substrate are bonded together, and the sealing material is cured.
- the liquid crystal panel is manufactured.
- an organic interlayer insulating film 26 thicker than this is provided on the interlayer insulating film (inorganic interlayer insulating film) 25 of FIG. 3, and as shown in FIG. ) Structure.
- the organic interlayer insulating film 26 penetrates a portion Kx that overlaps the upper capacitor electrode 37 and the pixel electrode 17b. In this way, the above effect can be obtained while sufficiently securing the value of the coupling capacitance.
- the organic interlayer insulating film 26 is penetrated through a portion Ky that overlaps the storage capacitor wiring 18p. In this way, the above effect can be obtained while sufficiently securing the value of the storage capacity.
- the pixel electrode is connected to the data signal line or the scanning signal line as shown in FIGS. It is possible to increase the aperture ratio.
- the interlayer insulating film (inorganic interlayer insulating film) 25, the organic interlayer insulating film 26, and the contact holes 11a and 11f in FIG. 7 can be formed as follows, for example. That is, after forming transistors and data signal lines, a mixed gas of SiH 4 gas, NH 3 gas, and N 2 gas is used to cover the entire surface of the substrate, and an interlayer insulating film 25 made of SiNx having a thickness of about 3000 mm ( A passivation film) is formed by CVD. Thereafter, an organic interlayer insulating film 26 made of a positive photosensitive acrylic resin having a thickness of about 3 ⁇ m is formed by spin coating or die coating.
- photolithography is performed to form a penetrating portion of the organic interlayer insulating film 26 and various contact patterns. Further, using the patterned organic interlayer insulating film 26 as a mask, CF 4 gas and O 2 gas are mixed.
- the interlayer insulating film 25 is dry etched using a mixed gas. Specifically, for example, the penetration portion of the organic interlayer insulating film is half-exposed in the photolithography process so that the organic interlayer insulating film remains thin when development is completed, while the contact hole portion is By performing full exposure in the photolithography process, an organic interlayer insulating film is not left when development is completed.
- the remaining film (of the organic interlayer insulating film) is removed from the penetrated portion of the organic interlayer insulating film, and the contact hole 11a portion is removed.
- the interlayer insulating film 25 under the organic interlayer insulating film is removed, and the interlayer insulating film 25 and the gate insulating film 22 under the organic interlayer insulating film are removed from the contact hole 11f. That is, the interlayer insulating film 25 is removed in the contact hole 11a portion, and the surface of the drain lead electrode 27 (for example, an Al film) is exposed to stop etching.
- the organic interlayer insulating film 26 may be, for example, an insulating film made of an SOG (spin-on glass) material, and the organic interlayer insulating film 26 may be an acrylic resin, an epoxy resin, a polyimide resin, a polyurethane resin, or a novolac resin. , And at least one of siloxane resins may be included.
- the upper capacitor electrode 37 extends from the drain lead electrode 27 to the pixel electrode 17b, but the upper capacitor electrode 37 can be shortened as shown in FIG. Specifically, the drain lead electrode 27 is connected to the pixel electrode 17a through the contact hole 11a, while the upper capacitor electrode 37 is connected to a portion of the pixel electrode 17a adjacent to the pixel electrode 17b through the contact hole 11i. Connecting. In this way, the upper capacitive electrode 37 can be shortened and the aperture ratio can be increased.
- FIG. 9 shows another specific example of the pixel 101 shown in FIG.
- a transistor 12a is arranged near the intersection of the data signal line 15x and the scanning signal line 16x, the source electrode 8 of the transistor 12a is connected to the data signal line 15x, and the scanning signal line 16x is connected to the gate electrode of the transistor 12a.
- the drain electrode 9 of the transistor 12a is connected to the drain lead electrode 27.
- the pixel electrode 17a first pixel electrode
- the pixel Electrodes 17b second pixel electrodes
- the upper capacitor electrode 47 connected to the pixel electrode 17b through the contact hole 11j extends so as to overlap the pixel electrode 17a, and the lower capacitor electrode 87 so as to overlap the upper capacitor electrode 47 and the pixel electrode 17a.
- the lower capacitor electrode 87 and the pixel electrode 17a are connected via a contact hole 11g.
- the pixel electrode 17a is connected to the drain lead electrode 27 through the contact hole 11a.
- the upper layer capacitive electrode 47 has two edges along the column direction below the pixel electrode 17a, and the lower layer capacitive electrode 87 also has two edges along the column direction below the pixel electrode 17a. When viewed in plan, both edges of the lower layer capacitive electrode 87 are located inside both edges of the upper layer capacitive electrode 47.
- the lower layer capacitor electrode 87 is formed in the same layer as the scanning signal line 16x
- the upper layer capacitor electrode 47 is formed in the same layer as the data signal line 15x
- the lower layer capacitor electrode 87, the upper layer capacitor electrode 47, and the pixel electrode 17a In the overlapping portion, a gate insulating film is disposed between the lower capacitor electrode 87 and the upper capacitor electrode 47, and an interlayer insulating film is disposed between the upper capacitor electrode 47 and the pixel electrode 17a.
- the coupling capacitance Cab1 is formed at the overlapping portion between the lower layer capacitance electrode 87 and the upper layer capacitance electrode 47
- the coupling capacitance Cab2 is formed at the overlapping portion between the upper layer capacitance electrode 47 and the pixel electrode 17a.
- a storage capacitor line 18p is arranged so as to cross the pixel region, and the storage capacitor line 18p overlaps with the pixel electrode 17a and the pixel electrode 17b through the gate insulating film and the interlayer insulating film.
- the storage capacitor Cha is formed in the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17a
- the storage capacitor Chb is formed in the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17b.
- FIG. 10 is a cross-sectional view taken along the line XY in FIG.
- the present liquid crystal panel includes an active matrix substrate 3, a color filter substrate 30 facing the active matrix substrate 3, and a liquid crystal layer 40 disposed between both substrates (3, 30).
- the storage capacitor wiring 18p and the lower layer capacitor electrode 87 are formed on the glass substrate 31, and the gate insulating film 22 is formed so as to cover them.
- An upper capacitor electrode 47 and a drain lead electrode 27 are formed on the gate insulating film 22.
- an interlayer insulating film 25 is formed so as to cover the metal layer.
- Pixel electrodes 17a and 17b are formed on the interlayer insulating film 25, and an alignment film 7 is formed so as to cover the pixel electrodes.
- the interlayer insulating film 25 is penetrated, whereby the pixel electrode 17b and the upper capacitor electrode 47 are connected. Further, in the contact hole 11a, the interlayer insulating film 25 is penetrated, whereby the drain extraction electrode 27 and the pixel electrode 17a are connected. Further, in the contact hole 11g, the interlayer insulating film 25 and the gate insulating film 22 are penetrated, whereby the lower-layer capacitor electrode 87 and the pixel electrode 17a are connected.
- the lower capacitor electrode 87 overlaps with the upper capacitor electrode 47 through the gate insulating film 22, and a coupling capacitor Cab1 (see FIG. 2) is formed at the overlapping portion of both (87, 47).
- the upper capacitor electrode 47 overlaps the pixel electrode 17a with the interlayer insulating film 25 interposed therebetween, and a coupling capacitor Cab2 (see FIG. 2) is formed at the overlapping portion of both (47, 17a).
- the storage capacitor line 18p overlaps the pixel electrode 17a via the gate insulating film 22 and the interlayer insulating film 25, and a storage capacitor Cha (see FIG. 2) is formed at the overlapping portion of both (18p, 17a).
- the storage capacitor line 18p overlaps the pixel electrode 17b through the gate insulating film 22 and the interlayer insulating film 25, and the storage capacitor Chb (see FIG. 2) is formed at the overlapping portion of both (18p and 17b).
- the lower capacitor electrode 87 is electrically connected to the pixel electrode 17a instead of the pixel electrode 17b. There is an advantage that image sticking of the floating pixel electrode 17b can be suppressed.
- the liquid crystal panel of FIG. 9 can also be configured as shown in FIG. That is, the lower layer capacitor electrode 87 is extended to a position where it overlaps the drain lead electrode 27, and the lower layer capacitor electrode 87, the drain lead electrode 27, and the pixel electrode 17a are connected by the contact hole 11s. In this way, the two contact holes (11a and 11g) in FIG. 9 can be combined into one contact hole (11s).
- the liquid crystal alignment is likely to be disturbed due to the level difference at the contact hole formation location, and this may be visually recognized.
- the region where the liquid crystal alignment is disturbed can be reduced and the display quality can be improved. it can.
- the light shielding region is reduced by combining the contact holes into one,
- the aperture ratio can be increased.
- FIG. 12 is a cross-sectional view taken along the line XY in FIG.
- the interlayer insulating film 25 is penetrated, whereby the pixel electrode 17b and the upper capacitor electrode 47 are connected.
- the interlayer insulating film 25 and the gate insulating film 22 are penetrated, and thereby the lower-layer capacitor electrode 87, the drain lead electrode 27, and the pixel electrode 17a are connected.
- the gate insulating film 22 is etched away by, for example, the PEP technique before the drain lead electrode 27 is formed.
- a penetrating portion 99 is formed in the drain lead electrode 27 so as to overlap a part of the opening of the contact hole 11s.
- the through-hole 99 and the contact hole 11 s are formed so that the outer periphery of the through-hole 99 is located inside the outer periphery of the opening of the contact hole 11 s in plan view.
- the contact holes 11s and 11j can be formed simultaneously without performing the etching of the gate insulating film 22 by the PEP technique (before the formation of the drain lead electrode 27) required in the configuration of FIGS.
- the interlayer insulating film 25 is removed at the location where the contact hole 11j is formed, and the surface of the drain lead electrode 27 (for example, Al) is formed.
- This step also removes the gate insulating film and interlayer insulating film located above the end of the scanning signal line to expose the end of the scanning signal line (the end of the scanning signal line is used as an external connection terminal).
- BHF buffered hydrofluoric acid
- NH 4 F ammonium fluoride
- the liquid crystal panel shown in FIG. 8 can also be configured as shown in FIG. That is, although not shown in FIG. 8, in the MVA liquid crystal panel, as shown in FIG. 15, the pixel electrode of the active matrix substrate is provided with the alignment regulating slit SL, and the color filter substrate is provided with the alignment regulating slit. Ribs Li (linear protrusions) are provided.
- the aperture ratio can be increased.
- the alignment regulating slit SL is provided in the pixel electrode of the active matrix substrate, and the alignment regulating slit sl is provided in the common electrode (counter electrode) of the color filter substrate. It may be provided.
- the aperture ratio may be increased by disposing the upper layer capacitor electrode 37 and the lower layer capacitor electrode 77 under the slit s1 of the common electrode.
- the storage capacitor line 18p is disposed close to the scanning signal line 16x.
- the storage capacitor line 18p overlaps only the pixel electrode 17a via the gate insulating film and the interlayer insulating film, and a storage capacitor between the two (18p ⁇ 17a) is formed in this overlapping portion.
- the drain extraction electrode 27 may be extended so as to overlap with the storage capacitor wiring 18p in order to secure the storage capacitor.
- the liquid crystal panel of FIG. 8 can be modified as shown in FIG. That is, the storage capacitor line 18p is disposed close to the scanning signal line 16x.
- the storage capacitor line 18p overlaps only the pixel electrode 17a through the gate insulating film and the inorganic interlayer insulating film, and a storage capacitor between the two (18p ⁇ 17a) is formed in this overlapping portion.
- the liquid crystal panel of FIG. 15 can be modified as shown in FIG. That is, the storage capacitor line 18p is disposed close to the scanning signal line 16x. In this configuration, the drain extraction electrode 27 is extended so as to overlap with the storage capacitor line 18p in order to secure the storage capacitor. In this case, the storage capacitor line 18p and the drain lead electrode 27 overlap with each other only through the gate insulating film, and a large part of the storage capacitor between the storage capacitor line 18p and the pixel electrode 17a is formed in this overlapping portion.
- the liquid crystal panel of FIG. 8 can be modified as shown in FIG.
- the pixel electrode 17b is formed in a V shape when viewed in the row direction, and the pixel electrode 17a is configured to surround the pixel electrode 17b.
- the pixel electrode 17b includes two edges E1 and E2 that form 45 degrees with respect to the row direction, and two edges E3 and E4 that form 315 degrees with respect to the row direction.
- Each of the gaps between the pixel electrode 17a and the edge of the pixel electrode 17a is parallel to the alignment regulating slits SL1 to SL4.
- the drain lead electrode 27 is connected to the pixel electrode 17a through the contact hole 11a, and the upper layer capacitor electrode 37 connected to the pixel electrode 17a through the contact hole 11i extends so as to pass under the slit SL3.
- a lower capacitor electrode 77 is provided so as to overlap with the upper capacitor electrode 37 and the pixel electrode 17b, and the lower capacitor electrode 77 is connected to the pixel electrode 17b through a contact hole 11f.
- the upper capacitor electrode 37 has two edges forming 315 degrees with respect to the row direction under the pixel electrode 17b, and the lower capacitor electrode 77 also has 315 degrees with respect to the row direction under the pixel electrode 17b.
- both edges of the lower layer capacitive electrode 77 are positioned inside both edges of the upper layer capacitive electrode 37.
- the coupling capacitor Cab1 is formed in the overlapping portion between the lower layer capacitive electrode 77 and the upper layer capacitive electrode 37
- the coupling capacitor Cab2 is formed in the overlapping portion between the upper layer capacitive electrode 37 and the pixel electrode 17b.
- a storage capacitor line 18p is arranged so as to cross the pixel region, and the storage capacitor line 18p overlaps with the pixel electrode 17a and the pixel electrode 17b through the gate insulating film and the interlayer insulating film. As a result, a storage capacitor is formed at the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17a, and a storage capacitor is formed at the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17b.
- the pixel electrode 17b includes two edges E1 and E2 that form 315 degrees with respect to the row direction and two edges E3 and E4 that form 45 degrees with respect to the row direction.
- the gap between E1 and the edge of the pixel electrode 17a parallel to this, and the gap between the edge E3 and the edge of the pixel electrode 17a parallel to this are slits SL1 and SL3 for regulating the orientation.
- the drain lead electrode 27 is connected to the upper capacitor electrode 37 in the same layer, and the upper capacitor electrode 37 extends in the column direction, passes through the slit SL1, and further changes direction on the pixel electrode 17b to form the color filter substrate. As seen in a plan view, it extends between the edges E1 and E2 of the pixel electrode 17b so as to form 315 degrees with respect to the row direction so as to crawl under the rib Li.
- annular storage capacitor extending portion 18px that extends over the outer periphery of the pixel electrode 17b extends from the storage capacitor wiring 18p.
- the storage capacitor extending portion 18px extends through the gate insulating film and the interlayer insulating film to form the pixel electrode 17a.
- the pixel electrode 17b As a result, a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17a, and a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17b.
- the pixel electrode 17a is formed in a triangular shape when viewed in the row direction, and the pixel electrode 17b is configured to surround the pixel electrode 17a.
- the pixel electrode 17a includes an edge E1 that forms 45 degrees with respect to the row direction and an edge E2 that forms 315 degrees with respect to the row direction, and the pixel electrode 17b that is parallel to the edge E1.
- Each of the gap between the edge E2 and the gap between the edge E2 and the edge of the pixel electrode 17b parallel to the edge E2 is an alignment regulating slit SL1 and SL2.
- the drain lead wiring 57 led out from the drain electrode 9 is connected to the pixel electrode 17a through the contact hole 11a, and the upper capacitor electrode 47 connected to the pixel electrode 17b through the contact hole 11j is below the slit SL2.
- a lower capacitor electrode 87 is provided so as to overlap the upper capacitor electrode 47 and the pixel electrode 17a, and the lower capacitor electrode 87 is connected to the pixel electrode 17a through a contact hole 11g.
- the upper capacitor electrode 47 has two edges that form 45 degrees with respect to the row direction under the pixel electrode 17a, and the lower capacitor electrode 87 also has 45 degrees with respect to the row direction under the pixel electrode 17a. When viewed in plan, both edges of the lower layer capacitor electrode 87 are located inside the both edges of the upper layer capacitor electrode 47.
- a gate insulating film is disposed between the lower layer capacitive electrode 87 and the upper layer capacitive electrode 47 in the overlapping portion of the lower layer capacitive electrode 87, the upper layer capacitive electrode 47, and the pixel electrode 17a.
- An interlayer insulating film is disposed between the pixel electrode 17a.
- an annular storage capacitor extending portion 18px that extends over the outer periphery of the pixel electrode 17a extends, and the storage capacitor extending portion 18px extends through the gate insulating film and the interlayer insulating film to form the pixel electrode 17a. And the pixel electrode 17b.
- a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17a, and a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17b.
- the retention capacity extending portion 18px is overlapped on the outer periphery of the pixel electrode 17a, so that the aperture ratio can be increased while the retention capacity is secured, and the alignment regulating force can be further enhanced.
- This liquid crystal panel can also be configured as shown in FIG.
- a transistor 12a is arranged near the intersection of the data signal line 15x and the scanning signal line 16x, the source electrode 8 of the transistor 12a is connected to the data signal line 15x, and the gate electrode of the transistor 12a is scanned with the scanning signal.
- the line 16x also serves as the drain electrode 9 of the transistor 12a is connected to the drain lead electrode 27.
- the pixel electrode 17au adjacent to the transistor 12a, the pixel electrode 17b, A pixel electrode 17av having the same shape as the pixel electrode 17au is provided.
- the pixel electrode 17au is an isosceles trapezoidal shape having an edge E1 forming 315 degrees with respect to the row direction and an edge E2 forming 45 degrees with respect to the row direction and having a base along the column direction.
- the pixel electrode 17av includes The leg E is an isosceles trapezoidal shape having a base along the column direction, with an edge E3 forming 45 degrees with respect to the row direction and an edge E4 forming 315 degrees with respect to the row direction.
- the pixel electrodes 17au and 17av are arranged so as to coincide with the pixel electrode 17av when the pixel electrode 17au is rotated 180 degrees around the center of the pixel region, and the pixel electrode 17b fits with the pixel electrodes 17au and 17av.
- a gap between the edge of the pixel electrode 17b parallel to the edge and a gap between the edge E4 of the pixel electrode 17av and the edge of the pixel electrode 17b parallel to the edge are slits SL1 to SL4 for regulating the orientation.
- the drain lead electrode 27 is connected to the pixel electrode 17au via the contact hole 11a, and the upper-layer capacitor electrode 37 connected to the pixel electrode 17au via the contact hole 11u extends in the column direction and passes under the slit SL2.
- the direction is changed 90 degrees under the pixel electrode 17b to reach the pixel electrode 17av, and the end of the upper capacitor electrode 37 and the pixel electrode 17av are connected via the contact hole 11v.
- a lower capacitor electrode 77 is provided so as to overlap with the upper capacitor electrode 37 and the pixel electrode 17b, and the lower capacitor electrode 77 is connected to the pixel electrode 17b through a contact hole 11f.
- the upper-layer capacitor electrode 37 has two edges along the column direction below the pixel electrode 17b, and the lower-layer capacitor electrode 77 also has two edges along the column direction below the pixel electrode 17b. When viewed in a plan view, both edges of the lower layer capacitor electrode 37 are positioned inside both edges of the upper layer capacitor electrode 77. In this configuration, a coupling capacitance is formed at an overlapping portion between the lower layer capacitive electrode 77 and the upper layer capacitive electrode 37, and a coupling capacitance is formed at an overlapping portion between the upper layer capacitive electrode 37 and the pixel electrode 17b. Are parallelized.
- an annular storage capacitor extending portion 18px extending over the outer periphery of the pixel region extends, and the storage capacitor extending portion 18px is connected to the pixel electrode 17a and the interlayer insulating film via the gate insulating film and the interlayer insulating film. It overlaps with each pixel electrode 17b.
- a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17a, and a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17b.
- FIG. 23 by superimposing the storage capacitor extension portion 18px on the outer periphery of the pixel region, it is possible to suppress burn-in of the pixel electrode 17b that is electrically floating while securing the storage capacitor.
- the storage capacitor extending portion 18px is overlaid on the outer periphery of the pixel electrode 17b, and the upper capacitor electrode 37 is extended in the row direction.
- the upper capacitor electrode 37 connected to the pixel electrode 17au through the contact hole 11u extends in the row direction in the center of the pixel, first passes under the slit SL2 and reaches the pixel electrode 17b, and further passes through the slit SL3. It reaches under the pixel electrode 17av, and the end portion of the upper capacitor electrode 37 and the pixel electrode 17av are connected via the contact hole 11v.
- FIG. 24 shows that is, the storage capacitor extending portion 18px is overlaid on the outer periphery of the pixel electrode 17b, and the upper capacitor electrode 37 is extended in the row direction.
- the upper capacitor electrode 37 connected to the pixel electrode 17au through the contact hole 11u extends in the row direction in the center of the pixel, first passes under the slit SL2 and reaches the pixel electrode 17b, and further passes
- the aperture ratio can be increased while the storage capacity is secured, and the alignment regulating force can be further increased. Further, an effect of suppressing the burn-in of the pixel electrode 17b that is electrically floating can be obtained.
- the liquid crystal panel of FIG. 23 can be modified as shown in FIG. In FIG. 25, the upper-layer capacitor electrode 37 connected to the pixel electrode 17au via the contact hole 11u extends in the row direction and is divided into two hands under the pixel electrode 17b. One of them extends from the edges E2 and E3 of the pixel electrode 17b so as to form 315 degrees with respect to the row direction in plan view so as to crawl under the rib Li formed on the color filter substrate, and the other Passes through the slit SL3 and reaches below the pixel electrode 17av, and the other end is connected to the pixel electrode 17av through the contact hole 11v.
- a storage capacitor line 18p is arranged so as to cross the pixel region, a storage capacitor electrode 67b is provided so as to overlap the storage capacitor line 18p and the pixel electrode 17b, and a storage capacitor is overlapped with the storage capacitor line 18p and the pixel electrode 17av.
- An electrode 67av is provided.
- the storage capacitor electrodes 67b and 67av are both formed in the same layer as the data signal line 15x, the pixel electrode 17b and the storage capacitor electrode 67b are connected through the contact hole 11i, and the pixel electrode 17av and the storage capacitor electrode 67av. Are connected via a contact hole 11j.
- the upper-layer capacitor electrode 37 is configured to crawl under the ribs Li, so that the aperture ratio and the alignment regulating force can be improved.
- a slit may be provided in the common electrode of the CF substrate instead of the rib Li.
- the storage capacitor electrodes 67b and 67av the storage capacitor between the storage capacitor line 18p and the pixel electrodes 17au and 17av and the storage capacitor between the storage capacitor line 18p and the pixel electrode 17b can be increased. it can.
- each pixel In the liquid crystal panel of FIG. 2, the structure of each pixel is the same, but it is not limited to this.
- the connection relationship between the pixel electrode and the transistor may be changed between pixels adjacent in the row direction.
- the pixel electrode 17a is connected to the data signal line 15x via the transistor 12a connected to the scanning signal line 16x, and the pixel electrode 17a and the pixel electrode 17b are connected via the coupling capacitors Cab1 and Cab2.
- a storage capacitor Cha is formed between the pixel electrode 17a and the storage capacitor line 18p
- a storage capacitor Chb is formed between the pixel electrode 17b and the storage capacitor line 18p
- the pixel electrode 17a and the common electrode com are between.
- a liquid crystal capacitor Cla is formed, and a liquid crystal capacitor Clb is formed between the pixel electrode 17b and the common electrode com.
- the coupling capacitors Cab1 and Cab2 are parallel.
- the pixel electrode 17B adjacent to the pixel electrode 17b in the row direction is connected to the data signal line 15y via the transistor 12A connected to the scanning signal line 16x.
- the pixel electrode 17A and the pixel electrode 17B adjacent to the electrode 17a in the row direction are connected via the coupling capacitors CAB1 and CAB2, and the storage capacitor ChA is formed between the pixel electrode 17A and the storage capacitor wiring 18p, and the pixel electrode 17B Is formed between the pixel electrode 17A and the common electrode com, and a liquid crystal capacitor ClB is formed between the pixel electrode 17B and the common electrode com.
- the coupling capacitors CAB1 and CAB2 are in parallel.
- FIG. 27 shows a specific example of the pixels 101 and 103 in FIG.
- the configuration of the pixel 101 is the same as that in FIG.
- the transistor 12A is arranged near the intersection of the data signal line 15y and the scanning signal line 16x, the source electrode of the transistor 12A is connected to the data signal line 15y, and the gate electrode of the transistor 12A is connected to the scanning signal line 16x.
- the drain electrode of the transistor 12A is connected to the drain lead electrode 127, and the pixel electrode 17A adjacent to the transistor 12A and the pixel electrode 17B are arranged in the column direction in the pixel region defined by both signal lines (15y and 16x). Are listed.
- the drain lead electrode 127 is connected to the pixel electrode 17B via the contact hole 11B, and the upper capacitor electrode 137 connected to the pixel electrode 17B via the contact hole 11J extends so as to overlap the pixel electrode 17A.
- a lower capacitor electrode 277 is provided so as to overlap with the upper capacitor electrode 137 and the pixel electrode 17A, and the lower capacitor electrode 277 is connected to the pixel electrode 17A through the contact hole 11F.
- the upper layer capacitor electrode 137 has two edges along the column direction below the pixel electrode 17A, and the lower layer capacitor electrode 277 also has two edges along the column direction below the pixel electrode 17A. When viewed in a plan view, both edges of the lower layer capacitor electrode 277 are located inside both edges of the upper layer capacitor electrode 137.
- the lower layer capacitor electrode 277 is formed in the same layer as the scanning signal line 16x
- the upper layer capacitor electrode 137 is formed in the same layer as the data signal line 15y
- the lower layer capacitor electrode 277, the upper layer capacitor electrode 137, and the pixel electrode 17A In the overlapping portion, a gate insulating film is disposed between the lower capacitor electrode 277 and the upper capacitor electrode 137, and an interlayer insulating film is disposed between the upper capacitor electrode 137 and the pixel electrode 17A.
- the coupling capacitor CAB1 is formed in the overlapping portion between the lower layer capacitive electrode 277 and the upper layer capacitive electrode 137
- the coupling capacitor CAB2 is formed in the overlapping portion between the upper layer capacitive electrode 137 and the pixel electrode 17A.
- the storage capacitor wiring 18p overlaps each of the pixel electrode 17A and the pixel electrode 17B through the gate insulating film and the interlayer insulating film.
- the storage capacitor ChA is formed in the overlapping portion between the storage capacitor wiring 18p and the pixel electrode 17A
- the storage capacitor ChB is formed in the overlapping portion between the storage capacitor wiring 18p and the pixel electrode 17B.
- the sub-pixel including the pixel electrode 17a is a bright sub-pixel and the sub-pixel including the pixel electrode 17b is a dark sub-pixel during halftone display.
- the sub-pixel including the pixel electrode 17A can be a dark sub-pixel
- the sub-pixel including the pixel electrode 17B can be a bright sub-pixel.
- bright subpixels do not adjoin in the row direction, and therefore there is less unevenness than a configuration in which bright subpixels (or dark subpixels) are arranged in the row direction. High-quality display is possible.
- FIG. 34 shows another configuration of the present liquid crystal panel
- FIG. 35 shows a cross-sectional view of FIG.
- the active matrix substrate of the liquid crystal panel shown in FIG. 34 includes transistors 12a and 12b connected to the scanning signal line 16x, and a transistor 112 connected to the scanning signal line 16y that is the next stage of the scanning signal line 16x, and data In the pixel region defined by the signal line 15x and the scanning signal line 16x, the pixel electrodes 17au, 17av, and 17b, the storage capacitor electrodes 67b and 67av, and the upper capacitor electrodes 87 and 97 that are formed in the same layer as the data signal line 15x.
- connection wiring 57 and a lower layer capacitor electrode 77 formed in the same layer as the scanning signal line 16x are provided.
- the shape and arrangement of the pixel electrodes 17au, 17av, and 17b are the same as those in FIG.
- the pixel electrode 17au and the pixel electrode 17av are connected through the contact holes 11u and 11v and the connection wiring 57
- the storage capacitor electrode 67b is connected to the pixel electrode 17b through the contact hole 11i
- the storage capacitor electrode 67av is
- the contact hole 11j is connected to the pixel electrode 17av
- the lower capacitor electrode 77 is connected to the pixel electrode 17b via the contact hole 11f.
- the common source electrode 8 of the transistors 12a and 12b is connected to the data signal line 15x, the drain electrode 9a of the transistor 12a is connected to the pixel electrode 17au via the contact hole 11a, and the drain electrode 9b of the transistor 12b is connected to the contact hole 11b.
- the source electrode 108 of the transistor 112 is connected to the storage capacitor electrode 67av (connected in the same layer)
- the drain electrode 109 of the transistor 112 is connected to the upper capacitor electrode 87 (connected in the same layer)
- the upper capacitor electrode 87 is connected.
- the storage capacitor electrode 67b overlaps the storage capacitor line 18p via the gate insulating film 22, and the storage capacitor electrode 67av and the storage capacitor line 18p pass through the gate insulating film 22.
- the upper capacitor electrode 97 overlaps with the storage capacitor wiring 18p through the gate insulating film 22, and the pixel through the channel protective film (a laminated film of the inorganic interlayer insulating film 25 and the organic interlayer insulating film 26 thicker than this).
- the upper capacitor electrode 87 overlaps with the pixel electrode 17b via a channel protective film (a laminated film of the inorganic interlayer insulating film 25 and the organic interlayer insulating film 26 thicker than this), and the lower capacitor electrode 77 is gated. It overlaps with the upper capacitive electrode 87 through the insulating film 22.
- a storage capacitor between the pixel electrode 17av and the storage capacitor line 18p is formed in an overlapping part between the storage capacitor electrode 67av and the storage capacitor line 18p
- a pixel electrode 17b is formed in an overlap part between the storage capacitor electrode 67b and the storage capacitor line 18p.
- a storage capacitor between the storage capacitor wiring 18p is formed, and most of the coupling capacitance between the pixel electrodes 17au and 17av and the pixel electrode 17b is formed at the overlapping portion of the lower layer capacitor electrode 77 and the upper layer capacitor electrode 87, and the remainder of the coupling capacitor Are formed at the overlapping portion of the upper-layer capacitor electrode 87 and the pixel electrode 17b and the overlapping portion of the upper-layer capacitor electrode 97 and the pixel electrode 17b.
- the same data signal potential is written to the pixel electrodes 17au, 17av, and 17b during scanning of the scanning signal line 16x, but the pixel electrode 17av is scanned during (next stage) scanning of the scanning signal line 16y.
- 17au and the pixel electrode 17b are connected via the coupling capacitance.
- dark subpixels formed by the pixel electrodes 17au and 17av and bright subpixels formed by the pixel electrode 17b are formed.
- the present liquid crystal display unit and the liquid crystal display device are configured as follows. That is, the two polarizing plates A and B are attached to both surfaces of the liquid crystal panel so that the polarizing axis of the polarizing plate A and the polarizing axis of the polarizing plate B are orthogonal to each other. In addition, you may laminate
- drivers gate driver 202, source driver 201 are connected.
- ACF is temporarily pressure-bonded to the terminal portion of the liquid crystal panel.
- the TCP on which the driver is placed is punched out of the carrier tape, aligned with the panel terminal electrode, and heated and pressed.
- the circuit board 209 (PWB) for connecting the driver TCPs and the input terminal of the TCP are connected by ACF.
- the display control circuit 209 is connected to each driver (201, 202) of the liquid crystal display unit via the circuit board 201, and integrated with the lighting device (backlight unit) 204.
- the liquid crystal display device 210 is obtained.
- FIG. 30 is a block diagram showing a configuration of the present liquid crystal display device.
- the liquid crystal display device includes a display unit (liquid crystal panel), a source driver (SD), a gate driver (GD), and a display control circuit.
- the source driver drives the data signal line
- the gate driver drives the scanning signal line
- the display control circuit controls the source driver and the gate driver.
- the display control circuit controls a display operation from a digital video signal Dv representing an image to be displayed, a horizontal synchronization signal HSY and a vertical synchronization signal VSY corresponding to the digital video signal Dv from an external signal source (for example, a tuner). For receiving the control signal Dc. Further, the display control circuit, based on the received signals Dv, HSY, VSY, and Dc, uses a data start pulse signal SSP and a data clock as signals for displaying an image represented by the digital video signal Dv on the display unit.
- Signal SCK digital image signal DA (signal corresponding to video signal Dv) representing an image to be displayed
- gate start pulse signal GSP gate start pulse signal GSP
- gate clock signal GCK gate driver output control signal (scanning signal output control signal) GOE is generated and these are output.
- the video signal Dv is output as a digital image signal DA from the display control circuit, and a pulse corresponding to each pixel of the image represented by the digital image signal DA.
- a data clock signal SCK is generated as a signal consisting of the above, a data start pulse signal SSP is generated as a signal that becomes high level (H level) for a predetermined period every horizontal scanning period based on the horizontal synchronization signal HSY, and the vertical synchronization signal VSY
- the gate start pulse signal GSP is generated as a signal that becomes H level only for a predetermined period every one frame period (one vertical scanning period), and the gate clock signal GCK is generated based on the horizontal synchronization signal HSY, and the horizontal synchronization signal HSY and
- a gate driver output control signal GOE is generated based on the control signal Dc.
- the digital image signal DA the polarity inversion signal POL for controlling the polarity of the signal potential (data signal potential)
- the data start pulse signal SSP the data start pulse signal SSP
- the data clock signal SCK the data clock signal SCK
- the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE are input to the gate driver.
- the source driver is based on the digital image signal DA, the data clock signal SCK, the data start pulse signal SSP, and the polarity inversion signal POL, and an analog potential (signal corresponding to the pixel value in each scanning signal line of the image represented by the digital image signal DA. Potential) is sequentially generated every horizontal scanning period, and these data signals are output to the data signal lines.
- the gate driver generates a gate-on pulse signal based on the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE, and outputs them to the scanning signal line, thereby selecting the scanning signal line. Drive.
- the data signal line and the scanning signal line of the display unit are driven by the source driver and the gate driver, so that the data is transmitted through the transistor (TFT) connected to the selected scanning signal line.
- TFT transistor
- a signal potential is written from the signal line to the pixel electrode.
- a voltage is applied to the liquid crystal layer of each subpixel, whereby the amount of light transmitted from the backlight is controlled, and an image indicated by the digital video signal Dv is displayed on each subpixel.
- FIG. 31 is a block diagram showing a configuration of a liquid crystal display device 800 for a television receiver.
- the liquid crystal display device 800 includes a liquid crystal display unit 84, a Y / C separation circuit 80, a video chroma circuit 81, an A / D converter 82, a liquid crystal controller 83, a backlight drive circuit 85, a backlight 86, A microcomputer 87 and a gradation circuit 88 are provided.
- the liquid crystal display unit 84 includes a liquid crystal panel and a source driver and a gate driver for driving the liquid crystal panel.
- a composite color video signal Scv as a television signal is input from the outside to the Y / C separation circuit 80, where it is separated into a luminance signal and a color signal.
- These luminance signals and color signals are converted into analog RGB signals corresponding to the three primary colors of light by the video chroma circuit 81, and further, the analog RGB signals are converted into digital RGB signals by the A / D converter 82. .
- This digital RGB signal is input to the liquid crystal controller 83.
- the Y / C separation circuit 80 also extracts horizontal and vertical synchronization signals from the composite color video signal Scv input from the outside, and these synchronization signals are also input to the liquid crystal controller 83 via the microcomputer 87.
- the liquid crystal display unit 84 receives a digital RGB signal from the liquid crystal controller 83 at a predetermined timing together with a timing signal based on the synchronization signal.
- the gradation circuit 88 generates gradation potentials for the three primary colors R, G, and B for color display, and these gradation potentials are also supplied to the liquid crystal display unit 84.
- the backlight drive is performed under the control of the microcomputer 87.
- the circuit 85 drives the backlight 86, so that light is irradiated to the back surface of the liquid crystal panel.
- the microcomputer 87 controls the entire system including the above processing.
- the video signal (composite color video signal) input from the outside includes not only a video signal based on television broadcasting but also a video signal captured by a camera, a video signal supplied via an Internet line, and the like.
- the liquid crystal display device 800 can display images based on various video signals.
- a tuner unit 90 is connected to the liquid crystal display device 800, thereby configuring the television receiver 601.
- the tuner unit 90 extracts a signal of a channel to be received from a received wave (high frequency signal) received by an antenna (not shown), converts the signal to an intermediate frequency signal, and detects the intermediate frequency signal to thereby detect the television.
- a composite color video signal Scv as a signal is taken out.
- the composite color video signal Scv is input to the liquid crystal display device 800 as described above, and an image based on the composite color video signal Scv is displayed by the liquid crystal display device 800.
- FIG. 33 is an exploded perspective view showing a configuration example of the present television receiver.
- the present television receiver 601 includes a first casing 801 and a second casing 806 in addition to the liquid crystal display device 800 as its constituent elements. It is configured to be sandwiched between one housing 801 and a second housing 806.
- the first housing 801 is formed with an opening 801a through which an image displayed on the liquid crystal display device 800 is transmitted.
- the second housing 806 covers the back side of the liquid crystal display device 800, is provided with an operation circuit 805 for operating the display device 800, and a support member 808 is attached below. Yes.
- the present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.
- the active matrix substrate of the present invention and the liquid crystal panel provided with the active matrix substrate are suitable for, for example, a liquid crystal television.
- Pixel 12a Transistor 15x Data signal line 16x Scanning signal line 17a Pixel electrode (first pixel electrode) 17b Pixel electrode (second pixel electrode) 18p storage capacitor wiring 22 gate insulating film 25 interlayer insulating film 37 47 upper layer capacitor electrode (second capacitor electrode) 77 Lower layer capacitor electrode (first capacitor electrode) 84 Liquid crystal display unit 601 Television receiver 800 Liquid crystal display device
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Abstract
Description
該第2容量電極が上記第1容量電極と第1画素電極との間の層に配され、第1容量電極と第2容量電極とが第1絶縁膜を介して重なることで第1容量電極および第2容量電極間に容量が形成され、第2容量電極と第1画素電極とが第2絶縁膜を介して重なることで第2容量電極および第1画素電極間に容量が形成されていることを特徴とする。
12a トランジスタ
15x データ信号線
16x 走査信号線
17a 画素電極(第1画素電極)
17b 画素電極(第2画素電極)
18p 保持容量配線
22 ゲート絶縁膜
25 層間絶縁膜
37 47 上層容量電極(第2容量電極)
77 下層容量電極(第1容量電極)
84 液晶表示ユニット
601 テレビジョン受像機
800 液晶表示装置
Claims (23)
- 1つの画素領域に、トランジスタを介してデータ信号線に接続された第1画素電極と、該第1画素電極に容量を介して接続された第2画素電極とが設けられたアクティブマトリクス基板であって、
第2画素電極に電気的に接続された第1容量電極と、第1画素電極に電気的に接続された第2容量電極とを備え、
該第2容量電極は、上記第1容量電極と第2画素電極との間の層に配され、
第1容量電極と第2容量電極とが第1絶縁膜を介して重なることで第1容量電極および第2容量電極間に容量が形成され、第2容量電極と第2画素電極とが第2絶縁膜を介して重なることで第2容量電極および第2画素電極間に容量が形成されていることを特徴とするアクティブマトリクス基板。 - 1つの画素領域に、データ信号線にトランジスタを介して接続された第1画素電極と、該第1画素電極に容量を介して接続された第2画素電極とが設けられたアクティブマトリクス基板であって、
第1画素電極に電気的に接続された第1容量電極と、第2画素電極に電気的に接続された第2容量電極とを備え、
該第2容量電極は、上記第1容量電極と第1画素電極との間の層に配され、
第1容量電極と第2容量電極とが第1絶縁膜を介して重なることで第1容量電極および第2容量電極間に容量が形成され、第2容量電極と第1画素電極とが第2絶縁膜を介して重なることで第2容量電極および第1画素電極間に容量が形成されていることを特徴とするアクティブマトリクス基板。 - 第1容量電極は走査信号線と同層に形成されていることを特徴とする請求項1または2記載のアクティブマトリクス基板。
- 第2容量電極はデータ信号線と同層に形成されていることを特徴とする請求項1~3のいずれか1項に記載のアクティブマトリクス基板。
- 第2絶縁膜の厚さは第1絶縁膜の厚さ以下であることを特徴とする請求項1~4のいずれか1項に記載のアクティブマトリクス基板。
- 第1絶縁膜はゲート絶縁膜であることを特徴とする請求項1~5のいずれか1項に記載のアクティブマトリクス基板。
- 第2絶縁膜はトランジスタのチャネルを覆う層間絶縁膜であることを特徴とする請求項1~6のいずれか1項に記載のアクティブマトリクス基板。
- 第1容量電極が平行な2本のエッジを有するとともに、第2容量電極も平行な2本のエッジを有し、平面的に視たときに、第2容量電極の両エッジの内側に第1容量電極の両エッジが位置していることを特徴とする請求項1~7のいずれか1項に記載のアクティブマトリクス基板。
- 第1容量電極が平行な2本のエッジを有するとともに、第2容量電極も平行な2本のエッジを有し、平面的に視たときに、第1容量電極の両エッジの内側に第2容量電極の両エッジが位置していることを特徴とする請求項1~7のいずれか1項に記載のアクティブマトリクス基板。
- 第1および第2画素電極それぞれと重なる保持容量配線を備えることを特徴とする請求項1または2記載のアクティブマトリクス基板。
- 第2画素電極と第1容量電極とが、第1および第2絶縁膜を貫くコンタクトホールによって接続されていることを特徴とする請求項1記載のアクティブマトリクス基板。
- 上記トランジスタの1つの導通電極と第1画素電極とがコンタクトホールを介して接続され、第1画素電極と第2容量電極とが上記コンタクトホールとは異なるコンタクトホールを介して接続されていることを特徴とする請求項1記載のアクティブマトリクス基板。
- 第1画素電極と第1容量電極とが、第1および第2絶縁膜を貫くコンタクトホールによって接続されていることを特徴とする請求項2記載のアクティブマトリクス基板。
- 上記第1容量電極と、トランジスタの一方の導通電極から引き出されたドレイン引き出し電極と、第1画素電極とが、第1および第2絶縁膜を貫く同一のコンタクトホールによって接続されていることを特徴とする請求項2記載のアクティブマトリクス基板。
- 上記ドレイン引き出し電極には、上記コンタクトホールの開口および第1容量電極に重なる刳り貫き部あるいは切り欠き部が設けられていることを特徴とする請求項14記載のアクティブマトリクス基板。
- 1つの画素領域に、トランジスタに電気的に接続された第1画素電極と、第2画素電極と、第2画素電極に電気的に接続された第1容量電極と、上記トランジスタに電気的に接続された第2容量電極とを備え、
該第2容量電極は、上記第1容量電極と第2画素電極との間の層に配され、
第1容量電極と第2容量電極とが第1絶縁膜を介して重なることで第1容量電極および第2容量電極間に容量が形成され、第2容量電極と第2画素電極とが第2絶縁膜を介して重なることで第2容量電極および第2画素電極間に容量が形成されていることを特徴とするアクティブマトリクス基板。 - 上記第2容量電極と同層にて接続された第3容量電極と、該第3容量電極と容量を形成する保持容量配線とを備えることを特徴とする請求項16記載のアクティブマトリクス基板。
- 請求項1~17のいずれか1項に記載のアクティブマトリクス基板を備えることを特徴とする液晶パネル。
- 請求項1~17のいずれか1項に記載のアクティブマトリクス基板と、配向規制用の線状突起を有する対向基板とを備え、
第1容量電極の少なくとも一部がこの線状突起の下に配されていることを特徴とする液晶パネル。 - 請求項1~17のいずれか1項に記載のアクティブマトリクス基板と、共通電極を有する対向基板とを備え、上記対向電極には配向規制用のスリットが設けられ、
第1容量電極の少なくとも一部がこのスリットの下に配されていることを特徴とする液晶パネル。 - 請求項18~20のいずれか1項に記載の液晶パネルとドライバとを備えることを特徴とする液晶表示ユニット。
- 請求項21記載の液晶表示ユニットと光源装置とを備えることを特徴とする液晶表示装置。
- 請求項22記載の液晶表示装置と、テレビジョン放送を受信するチューナ部とを備えることを特徴とするテレビジョン受像機。
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EP09824662A EP2352062A4 (en) | 2008-11-05 | 2009-08-19 | ACTIVE MATRIX SUBSTRATE, LIQUID CRYSTAL PANEL, LIQUID CRYSTAL DISPLAY UNIT, LIQUID CRYSTAL DISPLAY DEVICE AND TV RECEIVER |
BRPI0919943A BRPI0919943A2 (pt) | 2008-11-05 | 2009-08-19 | substrato de matriz, painel de cristal líquido, unidade de exibição de cristal líquido, dispositivo de exibição de cristal líquido e receptor de televisão |
RU2011122275/28A RU2488152C2 (ru) | 2008-11-05 | 2009-08-19 | Подложка активной матрицы, жидкокристаллическая панель, модуль жидкокристаллического дисплея, жидкокристаллическое устройство отображения и телевизионный приемник |
JP2010536717A JP5107439B2 (ja) | 2008-11-05 | 2009-08-19 | アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 |
CN2009801431083A CN102197336A (zh) | 2008-11-05 | 2009-08-19 | 有源矩阵基板、液晶面板、液晶显示单元、液晶显示装置、电视接收机 |
US13/126,571 US8441590B2 (en) | 2008-11-05 | 2009-08-19 | Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device, and television receiver |
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Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BRPI0917158A2 (pt) * | 2008-08-27 | 2015-11-17 | Sharp Kk | substrato de matriz ativa, painel de cristal líquido, unidade de exibição de cristal líquido, dispositivo de exibição de cristal líquido, receptor de televisão e método de fabricação de substrato de matriz ativa |
KR101240115B1 (ko) * | 2008-08-27 | 2013-03-11 | 샤프 가부시키가이샤 | 액티브 매트릭스 기판, 액정 패널, 액정 표시 장치, 액정 표시 유닛, 텔레비전 수상기 |
US8976209B2 (en) | 2009-03-05 | 2015-03-10 | Sharp Kabushiki Kaisha | Active matrix substrate, method for producing active matrix substrate, liquid crystal panel, method for producing liquid crystal panel, liquid crystal display device, liquid crystal display unit, and television receiver |
WO2010100790A1 (ja) * | 2009-03-05 | 2010-09-10 | シャープ株式会社 | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 |
CN102998855B (zh) * | 2012-11-16 | 2015-06-17 | 京东方科技集团股份有限公司 | 像素单元、薄膜晶体管阵列基板及液晶显示器 |
KR102124025B1 (ko) * | 2013-12-23 | 2020-06-17 | 엘지디스플레이 주식회사 | 유기발광다이오드 표시장치 및 그 제조방법 |
CN105242469A (zh) * | 2015-11-02 | 2016-01-13 | 深圳市华星光电技术有限公司 | 一种分担电容器、包括该分担电容器的像素及阵列基板 |
CN109755258B (zh) * | 2017-11-08 | 2021-02-19 | 元太科技工业股份有限公司 | 画素阵列基板与显示装置 |
CN109884828B (zh) * | 2019-04-17 | 2022-01-11 | 京东方科技集团股份有限公司 | 显示面板及移动终端 |
RU2763690C1 (ru) * | 2019-11-15 | 2021-12-30 | Боэ Текнолоджи Груп Ко., Лтд. | Подложка матрицы и устройство отображения |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0728091A (ja) * | 1993-07-14 | 1995-01-31 | Nec Corp | 液晶表示装置 |
JP2006163389A (ja) * | 2004-12-03 | 2006-06-22 | Au Optronics Corp | 薄膜トランジスタ液晶ディスプレイ、積層蓄積コンデンサ構造及びその形成方法 |
JP2006221174A (ja) | 2005-02-07 | 2006-08-24 | Samsung Electronics Co Ltd | 液晶表示装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5777700A (en) * | 1993-07-14 | 1998-07-07 | Nec Corporation | Liquid crystal display with improved viewing angle dependence |
US5953088A (en) * | 1997-12-25 | 1999-09-14 | Kabushiki Kaisha Toshiba | Liquid crystal display with shield electrodes arranged to alternately overlap adjacent pixel electrodes |
JP2002333870A (ja) * | 2000-10-31 | 2002-11-22 | Matsushita Electric Ind Co Ltd | 液晶表示装置、el表示装置及びその駆動方法、並びに副画素の表示パターン評価方法 |
FR2826766B1 (fr) * | 2001-06-29 | 2003-10-31 | Thales Avionics Lcd | Matrice active de transistors en couches minces ou tft pour capteur optique ou ecran de visualisation |
KR100961945B1 (ko) * | 2003-03-26 | 2010-06-08 | 삼성전자주식회사 | 액정 표시 장치 및 그에 사용되는 표시판 |
KR101112539B1 (ko) * | 2004-07-27 | 2012-02-15 | 삼성전자주식회사 | 다중 도메인 액정 표시 장치 및 그에 사용되는 표시판 |
KR101189266B1 (ko) * | 2004-09-24 | 2012-10-09 | 삼성디스플레이 주식회사 | 액정 표시 장치 |
KR20070074130A (ko) * | 2006-01-06 | 2007-07-12 | 삼성전자주식회사 | 표시패널 |
JP2008039982A (ja) * | 2006-08-03 | 2008-02-21 | Toshiba Matsushita Display Technology Co Ltd | 液晶表示素子およびその画素欠陥修復方法 |
KR101442147B1 (ko) * | 2008-01-30 | 2014-11-03 | 삼성디스플레이 주식회사 | 액정 표시 장치 |
WO2009130826A1 (ja) * | 2008-04-25 | 2009-10-29 | シャープ株式会社 | 液晶表示装置、テレビジョン受像機 |
WO2010089922A1 (ja) * | 2009-02-03 | 2010-08-12 | シャープ株式会社 | アクティブマトリクス基板、液晶パネル、液晶表示装置、液晶表示ユニット、テレビジョン受像機 |
US8976209B2 (en) * | 2009-03-05 | 2015-03-10 | Sharp Kabushiki Kaisha | Active matrix substrate, method for producing active matrix substrate, liquid crystal panel, method for producing liquid crystal panel, liquid crystal display device, liquid crystal display unit, and television receiver |
WO2010100790A1 (ja) * | 2009-03-05 | 2010-09-10 | シャープ株式会社 | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 |
-
2009
- 2009-08-19 EP EP09824662A patent/EP2352062A4/en not_active Withdrawn
- 2009-08-19 WO PCT/JP2009/064488 patent/WO2010052962A1/ja active Application Filing
- 2009-08-19 US US13/126,571 patent/US8441590B2/en not_active Expired - Fee Related
- 2009-08-19 CN CN2009801431083A patent/CN102197336A/zh active Pending
- 2009-08-19 BR BRPI0919943A patent/BRPI0919943A2/pt not_active IP Right Cessation
- 2009-08-19 JP JP2010536717A patent/JP5107439B2/ja not_active Expired - Fee Related
- 2009-08-19 RU RU2011122275/28A patent/RU2488152C2/ru not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0728091A (ja) * | 1993-07-14 | 1995-01-31 | Nec Corp | 液晶表示装置 |
JP2006163389A (ja) * | 2004-12-03 | 2006-06-22 | Au Optronics Corp | 薄膜トランジスタ液晶ディスプレイ、積層蓄積コンデンサ構造及びその形成方法 |
JP2006221174A (ja) | 2005-02-07 | 2006-08-24 | Samsung Electronics Co Ltd | 液晶表示装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2352062A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP2352062A1 (en) | 2011-08-03 |
RU2011122275A (ru) | 2012-12-10 |
JPWO2010052962A1 (ja) | 2012-04-05 |
EP2352062A4 (en) | 2012-05-09 |
CN102197336A (zh) | 2011-09-21 |
RU2488152C2 (ru) | 2013-07-20 |
JP5107439B2 (ja) | 2012-12-26 |
BRPI0919943A2 (pt) | 2016-02-16 |
US20110211130A1 (en) | 2011-09-01 |
US8441590B2 (en) | 2013-05-14 |
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