WO2010024240A1 - Dispositif semi-conducteur en carbure de silicium bipolaire - Google Patents

Dispositif semi-conducteur en carbure de silicium bipolaire Download PDF

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Publication number
WO2010024240A1
WO2010024240A1 PCT/JP2009/064770 JP2009064770W WO2010024240A1 WO 2010024240 A1 WO2010024240 A1 WO 2010024240A1 JP 2009064770 W JP2009064770 W JP 2009064770W WO 2010024240 A1 WO2010024240 A1 WO 2010024240A1
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region
base
resistance layer
emitter
silicon carbide
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PCT/JP2009/064770
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English (en)
Japanese (ja)
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賢一 野中
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本田技研工業株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Definitions

  • the present invention relates to a bipolar silicon carbide semiconductor device and a method for manufacturing the same, and in particular, is a bipolar silicon carbide semiconductor device having a normal four-layer structure, in which a main current flowing between main electrodes and a control current flowing through a control electrode are
  • the present invention relates to a bipolar silicon carbide semiconductor device suitable for suppressing recombination between the two and increasing the current amplification factor, and a method for manufacturing the same.
  • SiC Silicon carbide
  • junction SiC power devices include static induction transistors (Static Induction Transistor, “SIT”), junction field effect transistors (Junction Field Effect Transistor, “JFET”), or bipolar transistors (Bipolar Junction Transistor, “BJT”). and so on.
  • SIT Static Induction Transistor
  • JFET Junction Field Effect Transistor
  • BJT Bipolar Junction Transistor
  • BJT is stacked on the low resistance n + -type 4H-SiC (0001) plane 8 degree off substrate in the order of n ⁇ -type high resistance region, p-type base region, and n + -type emitter region from the bottom. It is formed.
  • the emitter region is composed of a number of elongated regions. Electrodes for establishing electrical connection to the outside are formed in the emitter region, base region, and collector region.
  • FIG. 13 shows a cross section of the BJT disclosed in Non-Patent Document 1.
  • the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region.
  • the base contact region 505 of the p-type low resistance region is formed.
  • a collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503 (base contact region 505), and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.
  • Patent Document 1 As an example of a conventional BJT with improved device characteristics (current amplification factor), there is one having a structure described in Patent Document 1.
  • the BJT disclosed in Patent Document 1 has a first n-type high resistance layer, a p-type base region, and a second n-type layer on the n + -type 4H—SiC (0001) surface substrate serving as a collector region from below.
  • a type high resistance layer and an n + type emitter region are stacked in this order.
  • the emitter region is separated and formed by etching in a predetermined planar pattern shape from the upper surface to the middle of the n + -type emitter region and the second n-type high resistance layer in the stacked structure. .
  • the BJT has a plurality of emitter regions separated on the upper surface based on a predetermined pattern shape. In the region between the separated emitter regions, an Al ion implantation process is subsequently performed to form a p-type base contact region in contact with the base region. Each of the plurality of separated emitter regions is surrounded by a base contact region when viewed in a BJT planar shape.
  • the BJT disclosed in Patent Document 1 has a structure in which the SiC surface of the BJT is covered with a surface recombination suppressing semiconductor layer between the emitter region and the base contact region.
  • the surface recombination suppressing semiconductor layer has a function of suppressing recombination between electrons flowing out from the emitter region and holes flowing out from the base contact region. This suppresses recombination of electrons from the emitter region and holes from the base contact region, and achieves an improvement in the current amplification factor of the junction type semiconductor layer device.
  • a control electrode portion called a base is formed by a pn junction.
  • Ic main current
  • control current Ib control current
  • recombination of holes flowing from the control electrode (carrier of the control current Ib) and electrons flowing between the main electrodes (carrier of the main current Ic) can be mentioned.
  • the value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.
  • the SiC surface is known as a site where recombination is likely to occur.
  • various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1.
  • a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface.
  • a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered.
  • the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration.
  • a surface recombination suppressing semiconductor layer By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.
  • the emitter region is etched until the surface of the base region is exposed. At this time, the base region layer needs to be slightly shaved. For this reason, since the base region becomes thin, the resistance increases, and the base resistance varies due to variations in the etching substrate surface. In order to improve the current amplification factor of the BJT, it is desirable to reduce the thickness of the base region. However, if the thickness of the base region is reduced, the increase or variation in the base resistance due to the above-described etching process of the emitter region becomes remarkable. Become. For a conventional BJT having a four-layer structure, a device that achieves both a high current gain and a small and stable base resistance has not been realized.
  • an object of the present invention is a conventional BJT having a four-layer structure, which reduces the recombination probability of electrons and holes, and controls the main current flowing between the main electrodes and the control electrode.
  • An object of the present invention is to provide a bipolar silicon carbide semiconductor device capable of suppressing recombination between currents, improving a current amplification factor, and realizing a small and stable base resistance, and a method for manufacturing the same.
  • a first bipolar silicon carbide semiconductor device (corresponding to claim 1) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer.
  • a base region formed thereon, an emitter region formed of a low-resistance layer and bonded to the base region; a low-resistance base contact region formed around the emitter region and bonded to the base region; and a base contact region Near the surface between the emitter region, a recombination suppression region having the same conductivity type as the base region and higher than its resistivity, or a recombination suppression region having the same conductivity type as the emitter region and higher than its resistivity It is characterized by having.
  • a second bipolar silicon carbide semiconductor device (corresponding to claim 2) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer.
  • the base region formed above, an emitter region composed of a low resistance layer, joined to the base region, a low resistance base contact region formed around the emitter region and joined to the base region, and the base region, It is characterized by having a buried region that is in contact with the base contact region and has the same conductivity type as the base region and has a resistivity equal to or lower than the resistivity.
  • a third bipolar silicon carbide semiconductor device (corresponding to claim 3) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer.
  • a base region formed on the base region, an emitter region joined to the base region, a low resistance base contact region formed around the emitter region and joined to the base region, and a high resistance layer A buried region that is in contact with the base region and has the same conductivity type as that of the base region and has a resistivity higher than that of the base region, or a recombination suppression region that has the same conductivity type as that of the high resistance region and has a resistivity higher than that of the base region. It is characterized by having.
  • the collector region is a low-resistance layer of the first conductivity type and the emitter region is a low-resistance layer of the first conductivity type in the above configuration.
  • the high resistance layer is of the first conductivity type, and the base region is of the second conductivity type.
  • a first bipolar silicon carbide semiconductor device manufacturing method includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer
  • a recombination suppression region having the same conductivity type as the base region and higher in resistivity than the base region exposed by etching, or having the same conductivity type as the emitter region and its resistance
  • a second bipolar silicon carbide semiconductor device manufacturing method includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer And a fifth step of forming a buried region in the base region in contact with the base contact region and having the same conductivity type as the base region and having a resistivity equal to or lower than the resistivity. And a sixth step of forming a base contact region bonded to the base region.
  • a third bipolar silicon carbide semiconductor device manufacturing method includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer And a fourth step of contacting the base region with the high-resistance layer and having the same conductivity type as that of the base region and higher than its resistivity, or having the same conductivity type as that of the emitter region and the resistivity thereof. A fifth step of forming a higher buried region and a sixth step of forming a base contact region bonded to the base region.
  • a collector electrode, an emitter electrode, and a base electrode are formed in each of the collector region, the emitter region, and the base contact region. And a step of forming an upper layer electrode above the emitter electrode and the base electrode.
  • the bipolar silicon carbide semiconductor device has the following effects. First, since the recombination suppression region is formed on the base surface from the base region to the emitter region, it prevents the electron or hole from approaching the recombination level formed on the surface of the silicon carbide semiconductor, thereby increasing the current amplification factor. Can be increased.
  • the base region or the buried region having a higher resistance than the high resistance layer is formed in the high resistance layer, electrons from the high resistance layer can be prevented from approaching the base region, and the current amplification factor can be increased. .
  • the base resistance value can be reduced and variations can be suppressed, and the device characteristics of BJT can be made uniform. can do.
  • the bipolar silicon carbide semiconductor device is provided with the layered recombination suppressing semiconductor region at a required location as described above, and therefore, electrons flowing from the emitter and Recombination of holes flowing from the base can be suppressed, and a bipolar silicon carbide semiconductor device having a high current gain can be easily and reliably manufactured.
  • FIG. 3 is a partial longitudinal sectional view of a bipolar semiconductor device (BJT) according to a first embodiment of the present invention, and is an enlarged sectional view taken along line AA of FIG. 1 is a plan view of a part of a bipolar semiconductor device according to a first embodiment. It is a fragmentary longitudinal cross-section explaining the problem of operation
  • movement of the bipolar type semiconductor device by 1st Example. 3 is a flowchart illustrating a method for manufacturing a bipolar semiconductor device according to the first embodiment.
  • FIG. 5 is a partial longitudinal sectional view of a bipolar semiconductor device according to a second embodiment of the present invention. It is a fragmentary longitudinal cross-sectional view explaining operation
  • FIG. 6 is a longitudinal sectional view of a bipolar semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 6 is a longitudinal sectional view of a bipolar semiconductor device according to a fifth embodiment of the present invention. It is the longitudinal cross-sectional view which showed the structure of the conventional bipolar type semiconductor device.
  • FIGS. 1 to 6B A first embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS. 1 to 6B.
  • This bipolar semiconductor device shows an example of a conventional BJT having a general four-layer structure.
  • the BJT 10 includes, for example, five emitter electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device. These emitter electrodes 19 are surrounded by a base electrode 20.
  • the BJT 10 has a collector region 11 formed of an n-type low resistance layer (n + layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal.
  • An emitter region 12 made of an n-type low resistance layer (n + layer) formed on the upper side surface portion is provided.
  • a layer forming the collector region 11 is a substrate.
  • a base electrode 20 is formed around each of the plurality of emitter electrodes 19 so as to surround the emitter electrode 19. This means that the periphery of the emitter region 12 located below the emitter electrode 19 is surrounded by the p-type base contact region 13 located below the base electrode 20.
  • the base contact region 13 is formed up to a predetermined depth position.
  • BJT 10 between the upper emitter region 12 and a lower collector region 11, n-type high-resistance layer from the lower side (n - layer) and 14 and p-type base region 15 is formed by stacking Yes.
  • the base region 15 is formed so as to be in contact with and electrically connected to the base contact region 13. In other words, the base contact region 13 is formed so as to be embedded at a predetermined position on the base region 15.
  • n-type is “first conductivity type” and the “p-type” is “second conductivity type”.
  • the p + type base region 15 is further interposed between the p + type base contact region 13 formed on a part of the surface of the layered p type base region 15 and the emitter region 12.
  • a layered recombination suppression region 16 is provided on the exposed surface portion so as to cover the surface portion.
  • the depth of the recombination suppression region 16 is substantially equal to the depth of the base contact region 13.
  • the recombination suppression region 16 is a high-resistance semiconductor and is “p ⁇ ” or “n ⁇ ”.
  • the base contact region 13 is formed so as to come into contact with the surface of the base region 15 and further enter the inside of the base region 15 from the surface.
  • the collector electrode 18 is bonded to the lower surface of the collector region 11
  • the emitter electrode 19 is bonded to the upper surface of the emitter region 12
  • the base contact region 13 A base electrode 20 is joined to the upper surface.
  • the exposed surface between the emitter electrode 19 and the base electrode 20 is covered with a surface protective film 17 and is protected thereby.
  • an upper layer electrode 21 is provided above each of the emitter electrode 19 and the base electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.
  • the main current is an electron flow that flows from the emitter region 12 (or the emitter electrode 19) to the collector region 11 (or the collector electrode 18).
  • the emitter region 12 and the collector region 11 are main electrode regions for flowing a main current.
  • Energization (ON) and non-energization (OFF) of the main current are based on a base voltage applied to the base electrode 20, that is, a control signal applied between the base contact region 13 and the base region 15 and the emitter region 12. Be controlled.
  • the applied voltage between the base and the emitter is 0 V or less, the BJT 10 does not flow main current and is turned off.
  • the BJT 10 When a voltage of a certain level or higher is applied between the base and the emitter, the BJT 10 is turned on due to the main current flowing. In the ON state, the pn junction formed between the base region 15 and the emitter region 12 is forward-biased, and a hole current that is a control current flows from the base region 15 to the emitter region 12.
  • FIG. 3 shows a BJT 10A having a conventional structure.
  • the same elements as those described in FIG. In the structure of the BJT 10A, in the base region 15, a large number of recombination levels 22 are formed in the vicinity of the SiC surface between the base contact region 13 and the emitter region 12. Therefore, some of the electrons 23 of the main current I1 flowing from the emitter region 12 toward the collector region 11 and the holes 24 flowing from the base contact region 13 are recombined at the recombination level 22. Such recombination of electrons 23 and holes 24 occurs frequently at the interface between the base region 15 and the high resistance layer 14. As a result, an invalid base current that does not contribute to the operation of the BJT 10A flows, and the current amplification factor of the BJT 10A is reduced.
  • a layer-like layer is formed on the surface of the base region 15 exposed between the base contact region 13 and the emitter region 12 and its vicinity.
  • a coupling suppression region 16 is formed.
  • the recombination suppressing region 16 is formed of a “p ⁇ ” or “n ⁇ ” semiconductor region, and forms a high potential barrier against the electrons 23 or the holes 24 and also has a high resistance layer having a low hole or electron concentration. It has become. Due to the existence of the recombination suppression region 16, holes 24 flowing from the base contact region 13 to the base region 15 do not easily flow into the recombination suppression region 16 in FIG.
  • Electrons flowing from the region 12 are also difficult to flow near the SiC surface. As a result, as shown in FIG. 4, the electrons 23 flowing out from the emitter region 12 flow toward the collector region 11 as the main current I2 without recombining with the holes, thereby improving the current amplification factor of the BJT 10. Can do.
  • the implantation concentration is extremely low and the energy required for ion implantation is low compared to the ion implantation for forming the base contact region 13. Therefore, in the ion implantation for forming the recombination suppression region 16, the density of recombination levels can be suppressed low.
  • the BJT 10 is designed with a target of a blocking voltage of 600V, for example.
  • a low resistance n-type 4H—SiC substrate turned off by 8 degrees from the (0001) plane is used as the substrate portion.
  • the substrate portion becomes the collector region 11.
  • the n-type high resistance layer 14 on the substrate is a layer for blocking a high voltage applied between the emitter and the collector.
  • the high resistance layer 14 is set to have a thickness of 10 ⁇ m and an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 , for example, so as to block a voltage of 600 V or higher.
  • the p-type base region 15 on the high resistance layer 14 has a thickness and an impurity concentration so as not to be depleted when a high voltage is applied between the emitter and the collector.
  • the p-type base region 15 has a thickness of 0.2 to 0.5 ⁇ m and an impurity concentration of about 4 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3 .
  • a low resistance n-type emitter region 12 having a thickness of 0.5 to 2.0 ⁇ m and an impurity concentration of 1 to 5 ⁇ 10 19 cm ⁇ 3 is provided.
  • a low-resistance base contact region 13 is formed around the emitter region 12.
  • the planar shape of the emitter region 12 is an elongated island shape.
  • One BJT 10 includes a plurality of emitter regions 12.
  • the dimensions of one emitter region 12 are about 3 to 10 ⁇ m in width and about 100 to 1000 ⁇ m in length.
  • the period of the unit structure including the base contact region 13 and the emitter region 12 is about 10 to 30 ⁇ m.
  • FIG. 5 is a flowchart showing each process of the manufacturing method.
  • 6A and 6B are longitudinal sectional views showing structures manufactured by each process.
  • the manufacturing method of the BJT 10 includes the following processes (1) to (10) (steps S11 to S20). As shown in FIG. 5, each process is executed in the order from step S11 to step S20.
  • step S11 High resistance layer forming process
  • step S12 Base region formation process
  • step S13 Low resistance layer formation process
  • step S14 Emitter etching process
  • step S15 Recombination suppression region formation process
  • step S17 Base contact region formation process
  • step S18 Surface protective film formation process
  • step S19 Electrode formation process
  • step S20 Upper layer electrode formation process
  • the structure shown in (a) of FIG. 6A is formed by performing the above steps S11 to S13.
  • step S11 nitrogen having a thickness of 10 ⁇ m and a concentration of 1 ⁇ 10 16 cm ⁇ 3 is doped as an impurity on the n-type substrate 40 formed of SiC by an epitaxial growth method.
  • a high resistance layer 41 is grown. “4H—SiC (0001) 8 ° off” is used for the substrate 40.
  • the substrate 40 becomes the collector region 11 of the n-type low resistance layer described above.
  • step S12 an epitaxial growth method is performed on the n-type high resistance layer 41 with aluminum (Al) as an impurity at a concentration of 4 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3 to 0.2 to A 0.5 ⁇ m p-type base region 42 is grown.
  • Al aluminum
  • step S13 nitrogen having a thickness of 0.5 to 2.0 ⁇ m and a concentration of 1 to 5 ⁇ 10 19 cm ⁇ 3 is formed as an impurity on the n-type base region 42 by an epitaxial growth method.
  • a doped n-type low resistance layer 43 is grown.
  • the low resistance layer 43 is a portion for forming the emitter region 12 described above.
  • step S14 in the structure shown in FIG. 6A (a), a silicon oxide film 51 is deposited on the upper surface by CVD, photolithography is performed, and then silicon oxide is formed by RIE. The film 51 is etched. Thus, a mask is formed. Then, using this silicon oxide film 51, SiC etching is performed on the low resistance layer 43 by RIE, and the emitter region 12 is formed using the low resistance layer 43. SF 6 gas or the like is used for RIE of SiC etching. The resulting structure is shown in FIG. 6A (b).
  • the recombination suppression region 16 is formed using the mask 51 shown in FIG. 6A (b) as it is. .
  • the recombination suppression region 16 is formed by performing ion implantation of nitrogen as an impurity (ion species). Ions are implanted into all regions etched by the emitter etching process (step S15).
  • the ion implantation amount is set to a value approximately equal to or around the impurity concentration of the base region 42.
  • the ion implantation amount is desirably about 3 to 5 ⁇ 10 17 cm ⁇ 3 .
  • the recombination suppression region 16 since the recombination suppression region 16 only needs to include a recombination level in the vicinity of the surface, its depth may be about 0.1 to 0.2 ⁇ m. Therefore, the implantation energy can be suppressed to as low as about 100 keV, and the generation of crystal defects in the ion implantation process can be suppressed.
  • step S16 In the base contact region forming process (step S16), first, as shown in FIG. 6A (d), a mask 52 is formed so that the surface portion for forming the base contact region 13 is exposed.
  • the mask 52 is formed by depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, ion implantation is performed to form the base contact region 13.
  • the implanted ions are aluminum (Al), and the depth of implantation is, for example, 0.2 ⁇ m.
  • the ion implantation amount is 1 ⁇ 10 18 to 10 20 cm ⁇ 3 , and the energy required for ion implantation is approximately 200 KeV.
  • the recombination suppression region 16 is formed on the surface of the base region 15 between the base contact region 13 and the emitter region 12 by the above steps S15 and S16.
  • the purpose of providing the recombination suppression region 16 is to keep electrons coming from the emitter region 12 away from the SiC surface of the recombination suppression region 16.
  • step S17 in the process of activating the ion implantation layer (step S17), after the ion implantation, the implanted ions are electrically activated in the semiconductor, and a heat treatment is performed to eliminate crystal defects generated by the ion implantation ( FIG. 6B (e)).
  • a heat treatment is performed to eliminate crystal defects generated by the ion implantation ( FIG. 6B (e)).
  • both the implanted ions in the base contact region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time.
  • heat treatment is performed at a high temperature of about 1700 to 1800 ° C. for about 10 minutes.
  • argon gas (Ar) is used as the atmospheric gas.
  • step S18 In the process of forming the surface protective film (step S18), as shown in FIG. 6B (f), first, in order to remove the surface layer generated in the ion implantation process and the activation process, the oxide film is removed after the thermal oxidation. Perform sacrificial oxidation.
  • the oxidation condition is, for example, 1100 ° C. for 20 hours in dry oxygen. Hydrofluoric acid is used to remove the oxide film.
  • thermal oxidation is performed again to form an oxide film 53.
  • the temperature is 1100 ° C.
  • the time is 5 hours
  • the atmosphere is wet.
  • POA Post Oxidation Anneal
  • heat treatment is performed to reduce the impurity level at the interface of the SiC oxide film.
  • POA is performed in a hydrogen, nitrogen oxide (NO, N 2 O) or argon atmosphere at a high temperature of about 800 to 1300 ° C. for about 10 to 30 minutes.
  • a CVD oxide film or a CVD nitride film is formed.
  • the emitter electrode 19, the base electrode 20, and the collector electrode 18 are formed on the surfaces of the emitter region 12 (low resistance layer 43), the base contact region 13, and the collector region 11 (substrate 40), respectively. It forms (FIG. 6B (g)).
  • the remaining oxide film 53 becomes the surface protective film 17 described above.
  • the emitter electrode 19 and the collector electrode 18 are made of nickel or titanium, and the base electrode 20 is made of titanium or aluminum.
  • Each electrode 18, 19, 20 is formed by vapor deposition or sputtering. For the formation of the electrode pattern, dry etching, wet etching, lift-off method or the like is used.
  • heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion.
  • the heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.
  • step S20 the upper layer electrode formation process (step S20) is executed.
  • an upper layer electrode 54 for taking out a plurality of separated emitter electrodes 19 as one electrode is formed (FIG. 6B (h)).
  • the silicon oxide film or the like in the emitter electrode 19 is removed by photolithography and etching.
  • the upper layer electrode 54 is deposited.
  • aluminum (Al) is used as the material of the upper electrode 54.
  • the BJT 10 shown in FIGS. 1 and 2 is manufactured.
  • the BJT 10 is a high-performance semiconductor device having normally-off characteristics.
  • the combinations of the first and second conductivity types such as the collector region, the emitter region, the high resistance layer, the base region, the base contact region, and the recombination suppression region can be reversed. . This also applies to the other embodiments described below.
  • FIG. 7 A second embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS.
  • the bipolar semiconductor device of the second embodiment is also BJT.
  • elements that are substantially the same as those described in FIG. 1 are given the same reference numerals.
  • the emitter region 12 is etched until the surface of the base region 15 is exposed.
  • the thickness of the base layer is reduced, and as a result, the resistance value of the base is increased.
  • the base resistance value varies between wafers or between wafers due to variations in etching depth within a wafer or between wafers.
  • a p-type semiconductor having a resistivity equal to or lower than that of the base region in a region corresponding to the region of the base surface exposed by etching in the base region 15 formed in a layer shape A low resistance buried region 61 made of p + or p ⁇ ) is provided.
  • the surface recombination suppression region 16 is not formed as in the first embodiment.
  • Other structures are the same as those of the first embodiment.
  • the hole current flowing from the base contact region 13 to the base region 15 flows near the surface in the conventional example shown in FIG. 3, whereas the resistance value as shown in FIG. It flows to the lower low resistance buried region 61. Therefore, recombination near the surface of base region 15 is reduced, and the current amplification factor is improved.
  • the resistance of the base region 15 is determined by the resistance value of the low-resistance buried region 61. As a result, it is possible to increase the resistance and variation of the base region 15 caused by the etching.
  • the impurity concentration of the p-type base region 15 are as 4 ⁇ 10 17 ⁇ 2 ⁇ 10 18 cm -3 as described above, the concentration of more than the same level as the base region 15 the impurity concentration of the low-resistance buried region 61
  • the impurity concentration of the p-type base region 15 is, for example, 4 ⁇ 10 17 cm ⁇ 3
  • the impurity concentration of the low-resistance buried region 61 is set to 2 ⁇ 10 18 cm ⁇ 3 and the thickness thereof is set as the base. If the thickness of the region 61 is the same, the resistivity of the low-resistance buried region 61 can be reduced to 1/3 of the resistivity of the base region 15.
  • the low resistance buried region 61 can be formed by applying a multi-stage ion implantation method in the manufacturing method of the BJT 10 of the first embodiment described above.
  • a third embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS.
  • the bipolar semiconductor device of the third embodiment is also a BJT. 9, elements that are substantially the same as those described in FIG. 1 are denoted by the same reference numerals.
  • the BJT 10A having the conventional structure has a characteristic that the holes flowing through the base region 15 and the electrons flowing through the collector region 11 are recombined near the base-collector interface.
  • the base region 15 is a region corresponding to the region of the base surface exposed by the etching described above on the lower side (on the high resistance layer 14 side) of the base region 15 formed in layers.
  • a high resistance buried region made of a p-type semiconductor (p ⁇ ) having a higher resistance than the base region 15 or a high resistance buried region 63 made of an n-type semiconductor (n ⁇ ) having a higher resistance than the high resistance layer 14 in contact with the base region 15.
  • the recombination suppression region 16 on the base surface is not formed as in the first embodiment. Other structures are the same as those of the first embodiment.
  • the electron / hole concentration in the high resistance buried region / high resistance layer in the third embodiment is lower than that in the base region / high resistance layer vicinity in the BJT 10A having the conventional structure. Therefore, recombination can be reduced, thereby improving the current amplification factor. Even in the case of the n ⁇ layer, recombination can be suppressed by substantially the same principle, and the current amplification factor can be improved.
  • the impurity concentration of the p-type base region 15 is 4 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3 , whereas the impurity concentration of the high-resistance buried region 63 is less than or equal to that of the base region 15.
  • the impurity concentration of the p-type base region 15 is, for example, 4 ⁇ 10 17 cm ⁇ 3
  • the impurity concentration of the high-resistance buried region 63 is set to 1 ⁇ 10 17 cm ⁇ 3 or less.
  • a bipolar semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. 11, elements that are substantially the same as those described in FIGS. 7 and 9 are denoted by the same reference numerals.
  • the BJT 300 of the fourth embodiment is configured by combining the characteristic structures of the second and third embodiments.
  • the high resistance buried region 63 is formed so as to be in contact with the lower surface of the low resistance buried region 61.
  • Other configurations are the same as those of the second or third embodiment. The same effect as described above is also exhibited by the BJT 300 of the present embodiment.
  • FIG. 12 A fifth embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIG. 12, elements that are substantially the same as those described in FIGS. 1, 7, and 9 are denoted by the same reference numerals.
  • the BJT 400 of the fifth embodiment is configured by combining the characteristic structures of the first, second and third embodiments.
  • a recombination suppression region 16, a low-resistance buried region 61, and a high-resistance buried region 63 formed so as to be in contact with the lower surface of the low-resistance buried region 61 are provided.
  • Other configurations are the same as those of the first, second, or third embodiment. The same effect as described above is also exhibited by the BJT 400 of the present embodiment.
  • a reverse polarity type in which the polarities of p and n in the description of the process of the manufacturing method are reversed may be used.
  • SiC has been described, but the present invention can also be applied to other semiconductors in which surface recombination is a problem.
  • the present invention relates to a conventional general bipolar silicon carbide semiconductor device having a four-layer structure, which suppresses recombination of electrons of a main current with holes of a control current and improves a current amplification factor, and Even if the base layer is thinned, it is used for improving an increase or variation in the base resistance value, and further used for a method of manufacturing a bipolar silicon carbide semiconductor device having such characteristics.
  • BJT Bipolar semiconductor devices
  • SYMBOLS 11 Collector area
  • region 12 Emitter area
  • region 13 Base contact area
  • region 14 High resistance layer 15
  • region 17 Surface protective film 18
  • Collector electrode 19 Emitter electrode 20
  • Upper layer electrode 40 Substrate 41 High resistance layer 42
  • Base area 43 Low resistance Layer 61 Low resistance buried region 63 High resistance buried region 100 BJT 200 BJT 300 BJT 400 BJT

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

La présente invention concerne un dispositif semi-conducteur en carbure de silicium bipolaire qui est un BJT comportant une structure à quatre couches et qui obtient un facteur d’amplification de courant amélioré et une résistance de base faible et stable par la réduction de la probabilité d’une recombinaison d’électrons et de trous et, de ce fait, qui supprime la recombinaison entre un courant principal et un courant de commande. Le dispositif semi-conducteur comprend une région de suppression de recombinaison (16) présentant le même type de conductivité qu’une région de base (15) et une résistivité supérieure à celle-ci ou une région de suppression de recombinaison (16) ayant le même type de conductivité qu’une région d’émetteur (12) et une résistivité supérieure à celle-ci, qui est formée près de la surface entre une région de contact de base (13) et la région d’émetteur (12).
PCT/JP2009/064770 2008-08-26 2009-08-25 Dispositif semi-conducteur en carbure de silicium bipolaire WO2010024240A1 (fr)

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WO2012105899A1 (fr) * 2011-01-31 2012-08-09 Fairchild Semiconductor Corporation Transistor bipolaire à jonctions à base de carbure de silicium avec émetteur formé par recouvrement
JP2013041985A (ja) * 2011-08-16 2013-02-28 Shindengen Electric Mfg Co Ltd 炭化珪素半導体装置
JP2015018859A (ja) * 2013-07-09 2015-01-29 国立大学法人京都大学 半導体装置、半導体装置の製造方法および熱処理装置
US9478629B2 (en) 2010-07-14 2016-10-25 Fairchild Semiconductor Corporation Conductivity modulation in a silicon carbide bipolar junction transistor

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JP2006351621A (ja) * 2005-06-13 2006-12-28 Honda Motor Co Ltd バイポーラ型半導体装置およびその製造方法
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JP2015018859A (ja) * 2013-07-09 2015-01-29 国立大学法人京都大学 半導体装置、半導体装置の製造方法および熱処理装置

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