WO2009146588A1 - Méthode de liaison de piles de tranches en 3d à base de vias traversants le silicium - Google Patents

Méthode de liaison de piles de tranches en 3d à base de vias traversants le silicium Download PDF

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Publication number
WO2009146588A1
WO2009146588A1 PCT/CN2008/071203 CN2008071203W WO2009146588A1 WO 2009146588 A1 WO2009146588 A1 WO 2009146588A1 CN 2008071203 W CN2008071203 W CN 2008071203W WO 2009146588 A1 WO2009146588 A1 WO 2009146588A1
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Prior art keywords
wafer
vias
wafers
stack
layer
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PCT/CN2008/071203
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English (en)
Inventor
Chi Kuen Leung
Peng Sun
Xunqing Shi
Chang Hwa Chung
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Hong Kong Applied Science And Technology Research Institute Co., Ltd..
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Application filed by Hong Kong Applied Science And Technology Research Institute Co., Ltd.. filed Critical Hong Kong Applied Science And Technology Research Institute Co., Ltd..
Priority to CN200880000042.8A priority Critical patent/CN101542702B/zh
Priority to PCT/CN2008/071203 priority patent/WO2009146588A1/fr
Publication of WO2009146588A1 publication Critical patent/WO2009146588A1/fr

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Definitions

  • This invention relates to a bonding method for through-silicon-via based 3D wafer stacking.
  • the invention relates to methods for forming a wafer stack and to the wafer stack.
  • TSV through-silicon-via
  • the bonding method is an important aspect of the fabrication of stacked electronic components.
  • An ideal bonding method should be reliable and cost-effective.
  • wire bonding eg US 6,933,172
  • wire-bonding requires greater in-plane size and is inconsistent with the objective of maximizing the component density.
  • TSV interconnects As an alternative to wire-bonding the use of TSV interconnects has been proposed, and methods including diffusion bonding, soldering and adhesive bonding can be used to bond wafers/chips with TSV interconnects. With each new component being added to the stack the soldering process causes the potential of failure of previously created solder joints that undermines their reliability.
  • a thin metal bonding layer (formed for example preferably from copper but also possibly tin, indium, gold, nickel, silver, palladium, palladium-nickel alloy or titanium) is applied to the respective surface of semiconductor components that are to be bonded.
  • the two metal bonding layers diffuse into each other to form the bond.
  • Diffusion bonding produces a good quality bond that is reliable, but disadvantages of this method include the requirement for very good coplanarity of the two semiconductor components and the need for a high bonding temperature. The method is therefore difficult to implement and is expensive.
  • a typical example of a diffusion bonding method is shown in US 7,157,787.
  • Adhesive bonding is a low cost option in which an adhesive layer is provided on the surfaces to be bonded together.
  • An example of adhesive bonding is shown in US 6,593,645.
  • US 6,448,661 shows an example of the prior art in which chips are bonded using conductive adhesives such as anisotropic conductive film (ACF) or anisotropic conductive adhesive (ACA).
  • ACF anisotropic conductive film
  • ACA anisotropic conductive adhesive
  • Another example of adhesive bonding is shown in US 4,897,708 where wafers are bonded by adhesive and electrical connections are made by a conductive liquid.
  • adhesive bonding is low cost and does not present significant manufacturing problems, it provides a low bonding strength, is not suitable for high current use and is unreliable.
  • solder is applied at the junctions of vias on semiconductor components to be stacked.
  • soldering does not require such high temperatures as diffusion bonding and can still produce a good reliable bond.
  • soldering encounters problems as the number of components being stacked increases. With each new component being added to the stack the soldering process causes the potential of failure of previously created solder joints that undermines their reliability. In particular repeated reflow processes may cause the growth of intermetallic compounds at previously formed joints that lead to brittle joints that are more likely to fail.
  • TSV-based 3D stacking methods Another problem with TSV-based 3D stacking methods is that the via filling step can introduce voids into the metal filling the vias which in turn can cause reliability issues.
  • a method of forming a wafer stack comprising the steps of, assembling a plurality of wafers, wherein each said wafers is provided with at least one via and wherein a channel is provided at an interface between two wafers connecting a via formed in one of said two wafers with a via formed in the other of said wafers, placing said plurality of wafers in a soldering chamber, and applying a vacuum to a first of said wafers defining a first side of said wafer stack to draw molten solder from a second side of said wafers through said vias and channel until said vias and channel are filled with solder.
  • the soldering chamber is provided with a vacuum tunnel that connects to openings that correspond with the openings of the vias formed in the first wafer, and molten solder is drawn through the vias and channel until it extends into the openings in the soldering chamber.
  • the wafer stack is allowed to cool and a part of the stack (eg the solder joint at the top of the stack where it contacts the soldering chamber) is then locally re-heated to enable removal of the wafer stack from the soldering chamber.
  • a part of the stack eg the solder joint at the top of the stack where it contacts the soldering chamber
  • the wafer stack is preferably formed on a wafer holder that is removed before placing the wafer stack in the soldering chamber.
  • the wafer stack may be formed by the steps of (a) depositing a first layer of photoresist on a first wafer and then patterning a first surface of said first layer of photoresist to define vias to be formed in the first wafer, (b) etching openings in the first wafer corresponding to the vias but not extending all the way through the first layer, (c) forming a metal layer on the interior of the openings and on the surface of the first wafer surrounding the openings, (d) fixing the first wafer to a wafer holder such that the first surface of the first wafer faces the wafer holder and a second surface of the wafer faces away from the wafer holder, (e) grinding the second surface of the first wafer until the openings extend all the way through the first wafer and become vias, (f) applying a layer of adhesive to the second surface and patterning the layer of adhesive
  • the adhesive layer is patterned to define a channel extending from a via in the first wafer to a via in the second wafer.
  • a method of forming a wafer stack comprising the steps of (a) depositing a first layer of photoresist on a first wafer and then patterning a first surface of the first layer of photoresist to define vias to be formed in the first wafer, (b) etching openings in the first wafer corresponding to the vias but not extending all the way through the first layer, (c) forming a metal layer on the interior of the openings and on the surface of the first wafer surrounding the openings, (d) fixing the first wafer to a wafer holder such that the first surface of the first wafer faces the wafer holder and a second surface of the wafer faces away from the wafer holder, (e) grinding the second surface of the first wafer until the openings extend all the way through the first wafer and become vias, (f) applying a layer of adhesive to the second surface and patterning the layer of adhesive to remove adhesive at least in the regions of the vias, attaching to the layer
  • the adhesive layer is patterned to define a channel extending from a via in the first wafer to a via in the second wafer.
  • a method of filling vias in a wafer stack with solder comprising the steps of, placing the wafer stack in a soldering chamber at a first temperature, allowing molten solder to fill the vias in the wafer stack, allowing the wafer stack to cool such that the molten solder is allowed to cool and solidify, and then locally heating a part of the wafer stack to a second temperature lower than the first temperature to enable the wafer stack to be removed from the soldering chamber.
  • a wafer stack comprising a plurality of wafers, at least one wafer being provided with at least one via extending therethrough, the wafer stack including at least one pair of adjacent wafers having vias that are laterally displaced relative to each other and the laterally displaced wafers being connected by a channel extending along an interface between the adjacent wafers.
  • the vias and channel are filled with a solder material.
  • apparatus for filling vias in a wafer stack with solder comprising, a chamber for receiving a wafer stack, the chamber being formed with a first part that in use contacts a first surface of the wafer stack and a second part that in use contacts a second surface of the wafer stack, the first part being formed with openings that are coincident with vias that open to the first surface of the wafer stack and the second part being formed with openings that are coincident with vias that open to the second surface of the wafer stack, and wherein the first part of the apparatus is connected to a vacuum and the second part of the apparatus is connected to a source of solder.
  • the apparatus is provided with means to control the temperature of said apparatus.
  • Figs. 1 to 22 show in sequence one embodiment of a method for forming a wafer stack
  • Fig.23 is a sectional view showing the wafer stack placed in a soldering chamber according to an embodiment of the invention.
  • Fig.24 shows the provision of a solder pool for use in the soldering process in an embodiment of the invention
  • Fig.25 shows the effect of applying vacuum to the soldering chamber drawing solder through the wafer stack
  • Fig.26 shows the soldering chamber according to an embodiment of the invention with the vias and microchannels filled with solder and the solder pool removed
  • Fig.27 shows the re-heating of the soldering chamber to enable removal of the wafer stack
  • Fig.28 shows in detail the localaised reheating that enables removal of the wafer stack
  • Fig.29 shows the completed wafer assembly
  • Fig.30 shows an example of three wafers connected by a combination of vertical TSVs and horizontal microchannels with selective electrical connections of circuits formed on wafers,
  • Fig.31 is the same as Fig.30 but with all circuits connected
  • Fig.32 shows an example of three wafers connected by vertical TSVs alone and with selective electrical connections of circuits formed on wafers
  • Fig.33 is the same as Fig.32 but with all circuits connected.
  • the starting point is a wafer 1 as shown in Fig.l.
  • the wafer 1 may be a silicon wafer and may have a thickness in the range of 100-500 ⁇ m.
  • a layer of photoresist 2 is then applied to the upper surface of the wafer 1 by means of a spinning process (Fig.2), and then the photoresist 2 is exposed to form a desired pattern (Fig.3) including openings 3 that are then extended into the wafer 1 by a deep reactive-ion etching (DRIE) process (Fig.4), and then the remaining photoresist is removed (Fig.5).
  • DRIE deep reactive-ion etching
  • a metal plating step is performed (Fig.6). Firstly a layer of SiO 2 is formed on the surface of the silicon wafer by a plasma-enhanced chemical vapour deposition process, and then layers 4 of Ti/W (to a depth of 0.1 ⁇ m- 2 ⁇ m), and Cu (again to a depth of 0.1 ⁇ m-2 ⁇ m) are deposited in sequence. A layer of film-type photoresist 5 is then laminated on the top surface (Fig.7), and then patterned so as to leave portions 5' covering the openings 3 (Fig.8).
  • the metal layer 4 that is not protected by the photoresist portions 5' is then etched away (Fig.9), and then the remaining photoresist portions 5' are removed (Fig.10) such that the metal layer 4 is left covering only the bottom and side walls of the openings 3, together with a region of the top surface of the wafer 1 surrounding the openings 3.
  • a mounting film 6 is then attached to the top surface of wafer 1 (Fig.11), and a wafer holder 7 is then placed on top of the mounting film 6 (Fig.12). With the wafer 1 secured on the wafer holder 7, a back grinding process involving grinding, chemical mechanical polishing (CMP) and etching is then carried out (Fig.13) to reduce the thickness of the wafer 1 until the openings 3 extend all the way through the wafer 1 and become vias. A layer of film-type adhesive 8 is then applied to the back side of the wafer 1 (Fig.14).
  • CMP chemical mechanical polishing
  • etching is then carried out to reduce the thickness of the wafer 1 until the openings 3 extend all the way through the wafer 1 and become vias.
  • a layer of film-type adhesive 8 is then applied to the back side of the wafer 1 (Fig.14).
  • the adhesive layer 8 is then patterned and areas of the adhesive layer 8 are removed using a laser (of any suitable type and power) (Fig.15) so that the adhesive layer 8 is removed to expose the vias 3 leaving adhesive portions 8' and partially defining microchannels 9 where future electrical connections are to be made between different chips.
  • a second wafer 10 constructed similarly but at a stage prior to the back-grinding is then attached to the underside of the initial wafer 1 by the remaining adhesive portions 8' (Fig.16) such that the microchannels 9 are fully formed by a grinding, CMP and etching process.
  • the advantage of stacking the wafers on a wafer holder is that this enables unlimited numbers of very thin wafers to be stacked while mitigating the problems that can occur with the handling of thin wafers.
  • the second wafer 10 is then subject to back-grinding such that the openings in the second wafer extend all the way through the second wafer and become vias 13 (Fig.17).
  • a layer of adhesive film 14 is laminated to the exposed underside of the second layer 10 (Fig.18) and is patterned to expose at least the vias 13 (Fig.19).
  • a third wafer 15 may then be attached to the underside of the second wafer by means of the adhesive film 14 (Fig.20), and the back-grinding process is repeated to open the vias in the third wafer (Fig.21), and then the mounting film and the wafer holder are removed (Fig.22) leaving three wafers secured together by adhesive films and allowing electrical interconnections by vias 3 and microchannels 9.
  • the combined three wafers are then placed in a soldering chamber comprising upper and lower halves 20,21 (Fig.23).
  • the upper half 20 is formed with openings 22 that are coincident with the vias 3 in the first wafer 1 and which connect to a vacuum tunnel 23.
  • the lower half 21 is formed with openings 24 that are coincident with the vias formed in the third wafer and which enable a fluid connection between molten solder 25, provided in a solder pool 26 (Fig.24).
  • An interposing layer may be provided to protect the wafers from direct contact with the solder.
  • Vacuum is then applied as shown by the arrows in Fig.25 and solder is drawn from the solder pool 26 through the vias and microchannels in the three wafers until the level of the solder is above the top surface of the first wafer and all vias and all microchannels are filled with molten solder.
  • the solder pool 26 is removed the solder allowed to cool (Fig.26).
  • the chamber temperature is then increased again to about 230 0 C in a local region, in particular the regions where the solder fills openings in the soldering chamber adjacent the wafer stack, which is just sufficient to soften the solder in the openings of the chamber (Fig.27).
  • Fig.28 shows in detail the structure of the openings in the upper and lower halves 20, 21 of the soldering chamber.
  • each opening is provided with a heating element 35 formed around the inner surface of the opening and a power supply 36 leading to the heating element 35.
  • the heating element 35 is capable of heating the solder 37 through a thermal conductor 38.
  • This design allows the solder 37 in the localized region of the openings to be softened and to allow the three stacked wafers to be removed from the solder chamber (Fig.29).
  • the tooling forming the upper and lower halves 20, 21 of the soldering chamber may be provided with a polymer coating the facilitate removal of the completed wafer stack from the soldering chamber.
  • the soldering chamber 20, 21 is provided with an integral heating means that enables the temperature of the chamber to be controlled between 150 0 C and 350 0 C such that a range of solder materials can be used including soft solders such as SnPb and hard solders such as SnAgCu and SnAu. It will also be understood that the space between the two halves of the soldering chamber can be varied to accept wafer stack assemblies of different thicknesses and with different numbers of wafer, and different diameter wafers (eg from 4" to 12").
  • the vacuum can be applied with a pressure differential between outside and inside of from 100-10000Pa.
  • the result is a stack of three wafers as shown in Fig.29 that are bonded together with adhesive, and where the vias and interconnecting microchannels are filled with solder enabling electrical interconnection between the three wafers.
  • Using a solder reflow process with vacuum has the advantage that it is a simple process with low cost, and that it enables the vias and microchannels to be filled with solder with a smaller likelihood of the formation of voids than the prior art.
  • a single process is used to fill all the vias with solder rather than using a repeated solder reflow process that can cause reliability issues.
  • the lower part of the soldering chamber serves to keep the wafer stack out of contact with the molten solder other than at the openings through which the molten solder is drawn.
  • vertical vias and horizontal microchannels provides for maximum flexibility in the design of a wafer stack and in the provision of different arrangements of electrical interconnections between wafers depending on the requirements of any particular application.
  • Vertical vias and horizontal microchannels can be combined in any suitable way depending on the connection requirements and space limitations and considerations of any particular wafer stack.
  • Fig.30 shows a stack of three wafers in which the circuits formed on first and third wafers (ie the top and the bottom in the figure) are electrically connected to each other but the second is not.
  • a vertical TSV connects the first wafer to the middle second wafer
  • vertical TSVs connect the second wafer to the third wafer.
  • the TSVs of the second and third wafers are laterally is disposed relative to the TSV of the first wafer and the connection between the first wafer TSV and the second wafer TSV is made by a lateral microchannel at the junction or interface between the first and second wafers.
  • the TSV of the first wafer and the TSV of the third wafer connect to the circuits formed on those wafers by interconnections 30, but the TSV of the second wafer does not connect to the circuit formed on the second wafer which is therefore bypassed.
  • the example of Fig.31 is identical to Fig.30 except that the circuit on the second wafer is connected to the TSV of the second wafer.
  • Fig.32 there are shown three wafers connected by vertical TSVs alone with no lateral microchannels. In Fig.32 only the circuits formed in the first and third wafers connect to the circuits formed on those wafers by interconnections 30, while the circuit formed on the middle wafer does not and is therefore not connected to the first and third wafers. In contrast, in Fig.33 the same structure is shown except that in this case all three wafers include circuits that are connected to the TSVs and hence to each other.

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Abstract

L'invention porte sur une méthode de liaison de piles de tranches à base de vias traversants le silicium, selon laquelle les tranches présentent des vias traversants et des microcanaux qui sont remplis de soudure. Pour effectuer le remplissage, on place la pile de tranches dans une chambre de soudage où la soudure fondue est aspirée dans les vias et canaux par dépression. Les tranches sont maintenues ensemble par des couches d'adhésif pour constituer la pile. On utilise des moyens de réchauffe de la soudure après son refroidissement pour la ramollir et pouvoir l'éliminer de la chambre de soudage.
PCT/CN2008/071203 2008-06-05 2008-06-05 Méthode de liaison de piles de tranches en 3d à base de vias traversants le silicium WO2009146588A1 (fr)

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CN200880000042.8A CN101542702B (zh) 2008-06-05 2008-06-05 基于硅通孔的三维晶圆叠层的键合方法
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WO2014058601A1 (fr) * 2012-10-11 2014-04-17 International Business Machines Corporation Procédé avancé de décollage de tranche de support

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CN102363520B (zh) * 2011-11-04 2014-04-09 中国科学院半导体研究所 用于微机电系统器件的圆片级三维封装方法
TWI482240B (zh) * 2011-12-19 2015-04-21 Nat Univ Tsing Hua 半導體之貫孔內連接線的製造方法
CN102723287B (zh) * 2012-06-09 2013-10-09 江苏长电科技股份有限公司 双面三维线路芯片正装先封后蚀制造方法及其封装结构
CN104470262A (zh) * 2014-10-24 2015-03-25 成都博芯联科科技有限公司 一种基于焊锡熔接技术的三维电路层间连接方法
US9556015B1 (en) * 2015-10-28 2017-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Substrate structure, semiconductor structure and method for fabricating the same
TWI655694B (zh) * 2018-07-17 2019-04-01 奇景光電股份有限公司 封膠設備及封膠方法
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