200921815 九、發明説明： 【發明所屬之技術領域】 本發明係有關於半導體晶片之内部互連技術，特別 係有關於一種具有矽通孔（TSV)之半導體晶片裝置及其 製造方法。 【先前技術】 積體電路形成於一晶片之主動表面，而傳統晶片之 端子，例如銲墊，亦僅形成於主動表面。 杜日日片的高密 : 度電性互連技術中’希望晶片的主動表面與背面皆設有 端子，以供立體堆疊或/與高密度封裝。 衣 已知利用矽通 孔（Through Silicon Via，TSV)可作為晶片 ® 通路 徑，藉以達到晶片内部電性連接在不同表面之端子。然 而，目前的矽通孔形成技術包含了許多光罩製作、光微 影、濺鍍、電鍍等等積體電路相關製程以及後段組裝與 錫球陣列植球的製程，其製程相當複雜且影響製程的因 (素多而造成製程不穩定，相對的提高了晶片製作成本。 特別是將晶片的貫穿孔内填入導電材料，須先將晶片之 貫穿孔以半通孔（盲孔）型態沉積與電鍍，再進行晶圓研 磨等等’在實行上有相當的難度’會造成製造成本的大 中田牦加，且良率不穩定會有量產上的困難。一種習知的 矽通孔形成技術可見於本國專利公告第53 1 843號（即美 國專利申請公開第US 2003/0092256 A1)，其名稱為「製 造半導體元件之方法及其元件」。 如第1圖所示，習知半導體晶另裝置1〇〇主要包含 200921815 一晶片110、一重配置墊120、一保護層13〇以及在複數個 貫穿孔140内導電材肖16〇以及一絕緣層15〇。該晶片11〇 係具有一主動面m以及一相對之背面丨丨2。電性連接晶片 銲墊之重配置墊120與該保護層i3〇係形成於該晶片i 〇之 主動面111上。该些貫穿孔i 4〇係形成於該些重配置墊i 2〇 内，但僅有兀成在該導電材料160與晶背研磨之後方貫穿該 些重配置墊12〇並由該晶片110之該主動面lu連通至該背 面112。但在製造時，該些貫穿孔14〇並不直接貫穿該晶片 " U〇，而是半通孔以便於形成介電層113以及形成電鍍種子 層170。該介電層113係形成於該些貫穿孔14〇内，以供電 性隔離。該電鍍種子層170係位於該些貫穿孔14〇内並形成 於該絕緣層1 50，以電性連接對應之該些重配置墊12〇，並 可作為電鍍形成該導電材料16〇之種子層。為能提供貫穿晶 片之垂直電性導通路徑，形成該導電材料丨6〇以填入尚 未貫穿之該些貫穿孔140内。待該導電材料16〇形成之 後，研磨該晶片1 1 0之背面1 1 2，直到該導電材料i 6 0 外露’此時’該些貫穿孔140始成為貫穿型態。由於該導 電材料160之材質大部分採用電鍍銅（plated(：u)或摻雜多 b曰石夕（doped p〇lyCryStaiiine si)且製造上易有孔填不滿空 隙’故能承受應力的效果較差’並且須以往在晶片表面高精 密度之積體電路製程運用到貫穿晶 之孔電鍍/填塞，導致 製造成本較高。 此外’在晶背研磨之後需要再一次形成該絕緣層丨5〇於 該晶片110之已研磨背面丨丨2，方設置複數個外接墊i 8〇於 6 200921815 該晶片110之背面112在該些貫穿孔140 —端，並可覆上另 一保護層190於該晶片11 〇之背面11 2。由於該些重配置墊 120與該些外接墊丨8〇平貼於該晶片丨丨〇之上下表面’應另 設置銲球或凸塊（圖未繪出），以供接合至堆疊晶片或晶片載 體。因此’習知的貫穿孔140與包含介電層113與絕緣層150 之絕緣設計皆以多步驟分段形成，另須設置外接端子，導致 製程步驟過於複雜與冗長。 【發明内容】 本發明之主要目的係在於提供一種具有矽通孔（TSV) 之半導體晶片裝置及其製造方法，利用可撓性金屬線貫 穿曰曰曰片之貫穿孔並一體形成有雙面突出端子，具有良好 才几應力功效，以供上下層晶片堆疊或是設置於晶片載體 時完成高密度電性互連，不易有斷路問題。 本發明之次一目的係在於提供一種具有矽通孔（TSV) 之半導體晶片裝置及其製造方法，能提供晶片與晶片或 晶片載體之間良好之電性互連品質’並能簡化製程以縮 短製程時間並降低製造成本。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明’一種具有矽通孔（TSV)之半 導體晶片裝置主要包含一晶片、一重配置線路層、一保護 層、一貫穿孔、一絕緣層以及一可撓性金屬線。該晶片係具 有—主動面、一背面以及一形成於該主動面之銲墊。該重配 置線路層係形成於該主動面上並包含一連接至該銲墊之重 置塾。該保護層係形成於該晶片之該主動面，該保護層係 7 200921815 覆蓋該重配置線路層但顯露該重配置墊。該貫空π 牙孔係形成該 重配置墊内並貫穿該晶片由該主動面至該背面。 孩絕緣層係 形成於該貫穿孔内。該可撓性金屬線係具有—笛 第一端與一第 二端，其中該第一端係鍵合於該重配置墊，該宽_ ^ 乐一端係通過 該貫穿孔並突出於該晶片之該背面。本發明另搞+ 力褐不〜種製造 該半導體晶片裝置之方法。 在前述之半導體晶片裝置中’該絕緣層可争# 』旯形成於該 晶片之該背面。 f 在前述之半導體晶片裝置中，該第一端係可 J ^結球 端，其直徑係大於該貫穿孔之孔徑，以使該第—^ ^ 端突出 於該主動面。 在前述之半導體晶片裝置中，該第二端係可亦為結 球端。 在前述之半導體晶片裝置中，可另包含有 1〜外接 墊，其係對應於該貫穿孔並設於該晶片之該背面，4 α itE且 該第二端係突出地鍵合於該外接墊。 在前述之半導體晶片裝置中，其中該保護層係可具 有一對準該重配置墊之開孔，其孔徑大於該貫穿孔， 以供鍵合該可撓性金屬線之第一端。 在前述之半導體晶片裝置中，可另包含一孔金屬 層，係位於該貫穿孔内並形成於該絕緣層，以電性連接 該重配置墊。 在前述之半導體晶片裝置中，其中該可撓性金屬，線 與該孔金屬層可為零接合力。 8 200921815 ’該可撓性金屬線之第 在前述之半導體晶片裝置中 端係可沾附有銲料。 广前述之半導體晶片裝置中，該可撓性金屬線之第 一鈿係可相對於該重配置墊為可移動。 在前述之半導體晶片農置中，該晶片係可具有鄰近但 不顯露該貫穿孔之切割侧面。 【實施方式】 依據本發明之第一具體實施例，揭示一種具有矽通 孔（TSV)之半導體晶片裝置及其製造方法。 請參閱第2圖所示，一種具有矽通孔（TSV)之半導體 曰曰片裝S 200 i要包含一晶# 2 J〇、—重配置線路層 220、-第-保護| 23〇、複數個貫穿孔24Q、一絕緣層 250以及複數個可撓性金屬線26〇。該晶片2ι〇係具有 一主動面2U、一背面212以及複數個形成於該主動面 211之銲墊213。在第2圖中是以一個貫穿孔24〇、一 個可撓性金屬線2 6 0以及一個銲塾2 1 3繪示之。該主動 面211上形成有各式積體電路元件並電性連接至該些 銲墊2 1 3。該晶片2 1 0之材質係可為矽、砷化鎵或其它 半導體材質。 該重配置線路層2 2 0為導電材料，其係形成於該主 動面211上並包含複數個連接至該些銲墊213之重配置 墊221，以改變該晶片210之端子位置（由該些銲塾213 改變至該些重配置墊22 1)。在本實施例中，該些重配置 墊221係位於該晶片210之主動面211之周邊，且下方 200921815 内層無積體電路。該第一保護層2 3 0係為電絕緣材料’ 其係形成於該晶片2 1 0之該主動面2 11，該第一保護層 23 0係覆蓋該重配置線路層220。較佳地，該第一保護 層2 3 0係可具有複數個對準該些重配置塾2 2 1之開孔 23 1，其孔徑大於該貫穿孔240，使得該些重配置墊221 具有在該貫穿孔240外圍的顯露表面’可供鍵合该些可 撓性金屬線260之一端261。 該些貫穿孔2 4 0係形成於對應之該些重配置塾2 2 1 f 内，並貫穿該晶片210是由該主動面211至該背面212。 該絕緣層2 5 0係形成於該些貫穿孔2 4 0内’較佳地’該 絕緣層2 5 0可更形成於該晶片2 1 0之該背面2 1 2 ’以防 止該晶片2 1 0漏電流與短路。 每一可撓性金屬線260係具有一第一端261與一第 二端262，其中如第2圖所示，該些第一端261係鍵合 於該些重配置墊221’較佳型態中，是突出於該主動面 211。該些第二端262係通過該些貫穿孔240並突出於 V 該晶片2 1 0之該背面2 1 2。其中，該些可撓性金屬線2 6 〇 之第一端2 6 1係可為打線時燒結形成之結球端’電性連 接至該些重配置墊221，以使能突出於該主動面2丨1。 該半導體晶片裝置200中，可另包含有複數個外接 墊2 70，其係對應於該些貫穿孔240並設於該晶片2 1 〇 之該背面212。並可在該晶片210之該背面212覆蓋形 成一第二保護層2 8 0，以保護並固定該些外接墊2 7 0。 具體而言，該些可撓性金屬線260之第二端262亦可為 10 200921815 結球端’並且該些第二端2 6 2係突出地鍵合於該些外接 墊2 7 0。較佳地’再如第2圖所示，該晶片210係具有 鄰近但不顯露該貫穿孔2 4 0之切割側面2 1 4，以避免該 些可撓性金屬線260在第一端261與第二端262之間的 線段外露。 因此，本發明之半導體晶片裝置200係利用可撓性 金屬線260貫穿該晶片210之貫穿孔240並一體形成有 雙面突出端子（即第一端261與第二端2 62)，能低成本 製作矽通孔結構，並具備良好抗應力功效，以供上下層 晶片堆疊或是設置於晶片載體時完成高密度電性互 連’該晶片2 10之内部不易有斷路問題。此外，矽通孔 結構兩端各形成一突出端子，不需要另外設置凸塊或輝 球，使得該矽通孔結構深具成本降低與耐用度提高之優 點。 請參閱第3A至3L圖所示’本發明進一步說明該半 導體晶片裝置200之製造方法，以彰顯本發明具有降低 矽通孔製造成本的功效。 首先，如第3 A圖所示，提供至少一晶片21 〇，該。曰 片2 1 0係玎形成於一晶圓内，其係具有一主動面2 1 1、 一背面212以及複數個形成於該主動面211之銲墊213。 之後，如第3 B圖所示’可利用表面沉積與表面電錢技 術形成一重配置線路層22〇於该晶片210之主動面211上， 該重配置線路層220係包含複數個連接至該些銲塾213之重 配置墊221。之後，如第3C圖所示，以化學氣相沉積、 200921815 旋塗或印刷等技術可形成一第一保護層23〇於該晶片2i 〇 之該主動面2 11 ’該第一保護層230係覆蓋該重配置線路層 220，並以微影成像或電漿蝕刻等技術，該第一保護層23〇 係具有複數個對準該些重配置墊22 1之開孔23 1，其孔徑大 於該貫穿孔240預設孔徑’以供後續步驟中鍵合該些可撓性 金屬線260之第一端261 (如第2圖所示）。 然後，如第3 D圖所示’可利用雷射鑽孔或反應性離 子蚀刻技術形成複數個貫穿孔2 4 0 ’該些貫穿孔2 4 0係形成 Γ 於該些重配置墊221内並貫穿該晶片210由該主動面211至 3玄背面212。故以一次貫穿方式形成該些貫穿孔24〇0如 有需要’晶背研磨製程可預先在上述提供晶圓步驟中實施， 可不需要安插執行在該些貫穿孔240之形成過程中。 之後，如第3 E圖所示’可利用沉積或是矽氧化技術 形成一絕緣層250於該些貫穿孔240内。在本實施例中，該 絕緣層250可更形成於該晶片210之該背面212，以絕緣保 護該晶片2 1 0。 I _ 接著，如第3F圖所示，在一較佳型態但非必要的步 驟中，可在對應於該些貫穿孔240設置複數個外接塾27〇 於該晶片2 1 0之該背面2 1 2。另在一變化實施例中，可形成 一孔金屬層290於該絕緣層250(如第4圖所示），該孔金屬 層290係位於該些貫穿孔240内，以電性連接對應之該些重 配置墊221。其中該些可撓性金屬線26〇與該孔金屬層 290係可為零接合力，而不受該孔金屬層29〇之應力影 響。 12 200921815 之後，如第3G圖所示，形成一第二保護層28〇於該 晶片2 1 0之背面2 1 2，以保護該晶片2 j 〇。之後，利用 一銲針1 0提供一可撓性金屬線26〇於該晶片2丨〇之對應貫 穿孔240内。先拉出一預定長度，使該可撓性金屬線之 一端可通過對應之該些貫穿孔24〇並突出於該晶片21〇之該 背面212。如第3H圖所示，將該可撓性金屬線26〇之突出 端可利用燒結成球技術成為一結球端，其直徑係大於該 些貫穿孔240之孔徑’並在一壓合力與加熱溫度下，使 該結球端突出地鍵合於該些外接墊27〇，以形成為上述可撓 性金屬線260之第二端262。 之後，如第31圖所示，再利用燒結成球技術將該些 可撓性金屬線260之預定區段（在該主動面211上且鄰近: 對應重配置墊221)形成為一結球部。並可利用銲針ι〇擠壓 該結球部使其鍵合於該些重配置墊221，以形成上述可撓性 金屬線細之第一端261。接著，如第3K圖所示，切斷該 些可撓性金屬線260之結球部（即第—端261)上方之線端， 使其成為一完整之可挽性金屬線26〇。逐一重覆第3G圖至 第汉圖之動作’以使每一可撓性金屬線26〇係形成於對應 之該些貫穿孔240内。 最後，如第3L圖所示，另在設置該些可換性金屬線· 之後，可包含有一晶圓切割步驟’利用—切割工具2〇將晶 圓切割成複數個分離晶片21G，形成如第2圖所示之半導體 晶片裝置200 ’上述之切割側面214係形成於該晶圓切割步 13 200921815 請參考第5圖所示，本發明並可利用複數個半導體 晶片裝置200堆疊形成一立體之晶片堆疊構造，利用已製 得之半導體晶片裝置2 0 0，對準該些可撓性金屬線2 6 0 作堆疊，將上下半導體晶片裝置200電性導通，完成高密 度之多晶片堆疊。在多晶片堆疊過程，不需要進行晶片 内部電性互連，而易於堆疊。 在本發明之第二具體實施例，如第6圊所示，揭示 另一種具有矽通孔（TSV)之半導體晶片裝置。該半導體 晶片裝置300主要包含一晶片310、一重配置線路層 320、一保護層330、複數個貫穿孔340、一絕緣層350 以及複數個可撓性金屬線3 6 0。該晶片3 1 〇係具有一主 動面311、一背面312以及複數個形成於該主動面311 之銲墊3 1 3。該重配置線路層3 20係形成於該主動面3 1 1 上並包含複數個連接至該些銲墊313之重配置墊321。 該保護層3 3 0係形成於該晶片3 1 0之該主動面3 1 1並係 覆蓋該重配置線路層320。該保護層330係可具有複數 個對準該些重配置墊3 2 1之開孔3 3 1，其孔徑大於該貫 穿孔，使得該些重配置墊3 2 1具有在該貫穿孔3 4 0外圍 的顯露表面，以供該些可撓性金屬線360之鍵合。 該些貫穿孔340係形成於該些重配置墊321内並貫 穿該晶片3 1 0由該主動面3 11至該背面3 1 2。該絕緣層 3 5 〇係形成於該些貫穿孔3 4 0内，較佳地’該絕緣層3 5 0 可更形成於該晶片3 1 0之該背面3 1 2，以保護該晶片 3 1〇。每一可撓性金屬線36〇係具有一第一端361與一 14 200921815 第二端362’其中該些第一端361係鍵合於該些重配置 堅321，該些第二端362係通過該些貫穿孔34〇並突出 於5玄晶片3 1 0之該背面3 1 2。在本實施例中，該些第一 端3 6 1係可為結球端’該些第二端3 6 2係可為懸空線 知，並可省略該晶片310背面312之保護層，可節省製 ie成本與製程流程。此外，該些可挽性金屬線3 6 〇之第 二端3 62係可相對於該些重配置墊3 2丨為可移動。較佳 fBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal interconnect technology for a semiconductor wafer, and more particularly to a semiconductor wafer device having a via via (TSV) and a method of fabricating the same. [Prior Art] The integrated circuit is formed on the active surface of a wafer, and the terminals of the conventional wafer, such as pads, are formed only on the active surface. The high density of Du Ri Ri films: In the electrical interconnection technology, it is hoped that the active surface and the back surface of the wafer are provided with terminals for three-dimensional stacking or/and high-density packaging. It is known to use a Through Silicon Via (TSV) as a wafer ® via to achieve internal electrical connections to terminals on different surfaces. However, the current through-hole forming technology includes many processes related to photomask fabrication, photolithography, sputtering, electroplating, etc., as well as post-assembly and solder ball array ball-laying processes. The process is quite complicated and affects the process. The cause of the process is unstable, which increases the wafer fabrication cost. In particular, when filling the through hole of the wafer with a conductive material, the through hole of the wafer must first be deposited in a semi-via (blind hole) type. With electroplating, wafer polishing, etc., 'there is considerable difficulty in implementation', the manufacturing cost will increase, and the yield instability will be difficult in mass production. A conventional flaw through hole formation The technique can be found in the National Patent Publication No. 53 1 843 (i.e., U.S. Patent Application Publication No. US 2003/0092256 A1), which is entitled "Method of Manufacturing a Semiconductor Component and Its Components". As shown in Fig. 1, a conventional semiconductor crystal The device 1 〇〇 mainly comprises a 200921815 wafer 110, a relocation pad 120, a protective layer 13 〇, and a plurality of conductive holes 〇 16 〇 and an insulating layer 15 在 in the plurality of through holes 140. The wafer 11 〇 An active surface m and an opposite back surface 丨丨2. The reconfiguration pad 120 electrically connected to the wafer pad and the protective layer i3 are formed on the active surface 111 of the wafer i. The through holes i 4 The lanthanide is formed in the relocation pads i 2 , but only after the conductive material 160 and the back grinding are penetrated through the relocation pads 12 〇 and is connected to the active surface of the wafer 110 to The back surface 112. However, at the time of manufacture, the through holes 14 〇 do not directly penetrate the wafer " U 〇, but a half via hole to facilitate the formation of the dielectric layer 113 and the formation of the plating seed layer 170. The dielectric layer 113 The electroplating seed layer 170 is disposed in the through holes 14 并 and formed in the insulating layer 150 to electrically connect the corresponding reconfigurable pads. 12〇, and can be used as a seed layer for electroplating to form the conductive material. In order to provide a vertical electrical conduction path through the wafer, the conductive material 形成6〇 is formed to fill the through holes 140 that have not penetrated. After the conductive material 16 is formed, the wafer 1 10 is ground. The back surface 1 1 2 until the conductive material i 60 is exposed 'at this time', the through holes 140 begin to be through. Since the material of the conductive material 160 is mostly plated (:u) or doped b曰石夕 (doped p〇lyCryStaiiine si) and it is easy to fill holes in the manufacturing process, so it can withstand the effect of stress, and it must be applied to the through-hole plating process in the high-precision integrated circuit process on the wafer surface. /filling, resulting in higher manufacturing costs. In addition, after the crystal back grinding, it is necessary to form the insulating layer 〇5 on the polished back surface 该2 of the wafer 110, and a plurality of external pads are provided. The back surface 112 of the wafer 110 is at the end of the through holes 140 and may be covered with another protective layer 190 on the back surface 11 2 of the wafer 11 . Since the reconfigurable pads 120 and the external pads 8 are flat on the lower surface of the wafer cassette, solder balls or bumps (not shown) should be additionally provided for bonding to the stacked wafer or wafer. Carrier. Therefore, the conventional through hole 140 and the insulating design including the dielectric layer 113 and the insulating layer 150 are formed in a multi-step segmentation, and an external terminal is required, which makes the process step too complicated and lengthy. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor wafer device having a through-via via (TSV) and a method of fabricating the same, wherein a flexible metal wire is used to penetrate a through-hole of a cymbal sheet and integrally formed with a double-sided protrusion The terminal has a good stress effect for high-density electrical interconnection when the upper and lower wafers are stacked or disposed on the wafer carrier, and there is no problem of disconnection. A second object of the present invention is to provide a semiconductor wafer device having a through via (TSV) and a method of fabricating the same, which can provide good electrical interconnection quality between the wafer and the wafer or wafer carrier and simplify the process to shorten Process time and reduce manufacturing costs. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. A semiconductor wafer device having a through via (TSV) according to the present invention mainly comprises a wafer, a reconfigurable wiring layer, a protective layer, a uniform via, an insulating layer, and a flexible metal line. The wafer has an active surface, a back surface, and a solder pad formed on the active surface. The reconfigurable circuit layer is formed on the active surface and includes a reset raft connected to the pad. The protective layer is formed on the active surface of the wafer, and the protective layer 7 200921815 covers the reconfigured wiring layer but exposes the relocation pad. The through-space π-hole system is formed in the relocation pad and extends through the active surface to the back surface of the wafer. A child insulating layer is formed in the through hole. The flexible metal wire has a first end and a second end, wherein the first end is bonded to the reconfigurable pad, and the wide end passes through the through hole and protrudes from the chip. The back. The present invention further provides a method of manufacturing the semiconductor wafer device. In the foregoing semiconductor wafer device, the insulating layer is formed on the back surface of the wafer. f In the above semiconductor wafer device, the first end portion may be a ball end having a diameter larger than an aperture of the through hole such that the first end protrudes from the active surface. In the foregoing semiconductor wafer device, the second end portion may also be a ball end. In the above semiconductor wafer device, there may be further included an external pad corresponding to the through hole and disposed on the back surface of the wafer, 4α itE and the second end is protrudingly bonded to the external pad. . In the foregoing semiconductor wafer device, the protective layer may have an opening aligned with the re-arrangement pad, the aperture being larger than the through hole for bonding the first end of the flexible metal wire. In the foregoing semiconductor wafer device, a hole metal layer may be further disposed in the through hole and formed in the insulating layer to electrically connect the relocation pad. In the foregoing semiconductor wafer device, wherein the flexible metal, the wire and the hole metal layer can have zero bonding force. 8 200921815 The first of the flexible metal wires may be soldered to the ends of the semiconductor wafer device. In the above-described semiconductor wafer device, the first twist of the flexible metal wire is movable relative to the reset mat. In the aforementioned semiconductor wafer farm, the wafer system may have a cut side adjacent to but not revealing the through hole. [Embodiment] According to a first embodiment of the present invention, a semiconductor wafer device having a through via (TSV) and a method of fabricating the same are disclosed. Referring to FIG. 2, a semiconductor wafer device S 200 i having a through via (TSV) includes a crystal # 2 J〇, a reconfigurable circuit layer 220, a -protective | 23 〇, a plurality A through hole 24Q, an insulating layer 250, and a plurality of flexible metal wires 26A. The wafer 2 〇 has an active surface 2U, a back surface 212, and a plurality of pads 213 formed on the active surface 211. In Fig. 2, a through hole 24, a flexible metal wire 2 60 and a pad 2 1 3 are shown. The active surface 211 is formed with various integrated circuit components and electrically connected to the pads 2 1 3 . The material of the wafer 210 may be germanium, gallium arsenide or other semiconductor materials. The reconfigurable circuit layer 220 is a conductive material formed on the active surface 211 and includes a plurality of relocation pads 221 connected to the pads 213 to change the terminal positions of the wafers 210. The solder fillet 213 is changed to the reconfiguration pads 22 1). In this embodiment, the relocation pads 221 are located around the active surface 211 of the wafer 210, and the inner layer of the lower layer 200921815 has no integrated circuit. The first protective layer 230 is an electrically insulating material, which is formed on the active surface 211 of the wafer 210, and the first protective layer 230 covers the reconfigured wiring layer 220. Preferably, the first protection layer 203 has a plurality of openings 23 1 aligned with the reconfigurations 221, and the apertures thereof are larger than the through holes 240, so that the reconfiguration pads 221 have The exposed surface 'on the periphery of the through hole 240' is for bonding one end 261 of the flexible metal wires 260. The through holes 240 are formed in the corresponding reconfigurations 2 2 1 f, and the wafer 210 extends from the active surface 211 to the back surface 212. The insulating layer 250 is formed in the through holes 240. Preferably, the insulating layer 250 can be formed on the back surface 2 1 2 ' of the wafer 2 10 to prevent the wafer 2 1 . 0 leakage current and short circuit. Each of the flexible metal wires 260 has a first end 261 and a second end 262. The second end 261 is bonded to the reconfigurable pads 221' as shown in FIG. In the state, it is highlighted on the active surface 211. The second ends 262 pass through the through holes 240 and protrude from the back surface 21 of the wafer 210. The first end of the flexible metal wire 26 6 2 can be electrically connected to the ball-receiving end 221 of the sintered wire to be electrically connected to the re-arrangement pad 221 so as to protrude from the active surface 2丨1. The semiconductor wafer device 200 may further include a plurality of external pads 270 corresponding to the through holes 240 and disposed on the back surface 212 of the wafer 2 1 . A second protective layer 280 may be formed on the back surface 212 of the wafer 210 to protect and fix the external pads 270. Specifically, the second ends 262 of the flexible metal wires 260 may also be 10 200921815 ball ends ′ and the second ends 262 are protrudingly bonded to the outer pads 270 . Preferably, as shown in FIG. 2, the wafer 210 has a cut side 2 1 4 adjacent to but not revealing the through hole 240 to prevent the flexible metal wires 260 from being at the first end 261. The line segment between the second ends 262 is exposed. Therefore, the semiconductor wafer device 200 of the present invention penetrates the through hole 240 of the wafer 210 by the flexible metal wire 260 and integrally forms the double-sided protruding terminal (ie, the first end 261 and the second end 2 62), which can be low in cost. The through-hole structure is fabricated and has good stress-resistance effect for high-density electrical interconnection when the upper and lower wafers are stacked or disposed on the wafer carrier. The inside of the wafer 2 10 is not susceptible to open circuit problems. In addition, a protruding terminal is formed at each end of the through-hole structure, and no additional bumps or balls are required, so that the structure of the through-hole structure has the advantages of cost reduction and durability improvement. Referring to Figures 3A through 3L, the present invention further describes a method of fabricating the semiconductor wafer device 200 to demonstrate that the present invention has the effect of reducing the manufacturing cost of the via. First, as shown in Fig. 3A, at least one wafer 21 is provided. The 2 2 2 玎 is formed in a wafer having an active surface 21 1 , a back surface 212 , and a plurality of pads 213 formed on the active surface 211 . Thereafter, as shown in FIG. 3B, a reconfigurable wiring layer 22 may be formed on the active surface 211 of the wafer 210 by surface deposition and surface charge technology, and the reconfigured wiring layer 220 includes a plurality of connections to the The pad 221 is reconfigured with the pad 221. Thereafter, as shown in FIG. 3C, a first protective layer 23 can be formed by chemical vapor deposition, 200921815 spin coating or printing, etc., and the first protective layer 230 is formed on the active surface 2 11 ' of the wafer 2i 〇 Covering the reconfiguration circuit layer 220, and using a technique such as lithography or plasma etching, the first protection layer 23 has a plurality of openings 23 1 aligned with the reconfiguration pads 22 1 , and the aperture is larger than the The through hole 240 is preset to have a diameter 'for the first end 261 of the flexible metal wires 260 to be bonded in a subsequent step (as shown in FIG. 2). Then, as shown in FIG. 3D, a plurality of through holes 2400 may be formed by laser drilling or reactive ion etching techniques, and the through holes 240 are formed in the relocation pads 221 and Through the wafer 210, the active faces 211 to 3 are backed 212. Therefore, the through holes 24 〇 0 are formed in a single through manner. If necessary, the crystal back grinding process may be performed in the above-described step of providing wafers, and may not be performed in the formation process of the through holes 240. Thereafter, as shown in Fig. 3E, an insulating layer 250 may be formed in the through holes 240 by deposition or germanium oxidation. In this embodiment, the insulating layer 250 may be formed on the back surface 212 of the wafer 210 to insulate and protect the wafer 210. I _ Next, as shown in FIG. 3F, in a preferred but non-essential step, a plurality of external ridges 27 corresponding to the through holes 240 may be disposed on the back surface 2 of the wafer 2 1 0 1 2. In another variation, a hole metal layer 290 may be formed on the insulating layer 250 (as shown in FIG. 4). The hole metal layer 290 is located in the through holes 240 to electrically connect the corresponding holes. Reconfigure the pads 221. The flexible metal wires 26 and the hole metal layer 290 can be zero-bonding force without being affected by the stress of the hole metal layer 29. 12 200921815, as shown in FIG. 3G, a second protective layer 28 is formed on the back surface 2 1 2 of the wafer 210 to protect the wafer 2 j 〇. Thereafter, a solder pin 10 is used to provide a flexible metal line 26 within the corresponding through-hole 240 of the wafer 2. A predetermined length is first drawn so that one end of the flexible metal wire can pass through the corresponding through holes 24 and protrude from the back surface 212 of the wafer 21A. As shown in FIG. 3H, the protruding end of the flexible metal wire 26 can be formed into a ball end by using a sintered ball technique, and the diameter thereof is larger than the diameter of the through holes 240 and a pressing force and heating temperature. Next, the ball end is protrudedly bonded to the external pads 27A to form the second end 262 of the flexible metal wire 260. Thereafter, as shown in Fig. 31, predetermined portions of the flexible metal wires 260 (on the active surface 211 and adjacent to the corresponding relocation pad 221) are formed into a ball portion by a sintering ball technique. The ball portion may be pressed by a solder pin to bond the reposition pads 221 to form the first end 261 of the flexible metal wire. Next, as shown in Fig. 3K, the line ends above the ball portions (i.e., the first ends 261) of the flexible metal wires 260 are cut to form a complete leadable metal wire 26A. The operation of the 3Gth to the hanth diagrams is repeated one by one so that each of the flexible metal wires 26 is formed in the corresponding through holes 240. Finally, as shown in FIG. 3L, after the reconfigurable metal wires are disposed, a wafer cutting step may be included to cut the wafer into a plurality of separate wafers 21G by using the cutting tool 2, forming a The semiconductor wafer device 200 shown in FIG. 2 is formed on the wafer cutting step 13 200921815. Referring to FIG. 5, the present invention can be stacked to form a three-dimensional wafer by using a plurality of semiconductor wafer devices 200. The stacked structure is formed by stacking the flexible metal wires 206 by using the fabricated semiconductor wafer device 200, and electrically connecting the upper and lower semiconductor wafer devices 200 to complete high-density multi-wafer stacking. In the multi-wafer stacking process, it is not necessary to perform internal electrical interconnection of the wafer, and it is easy to stack. In a second embodiment of the present invention, as shown in Fig. 6, another semiconductor wafer device having a through via (TSV) is disclosed. The semiconductor wafer device 300 mainly includes a wafer 310, a re-distribution circuit layer 320, a protective layer 330, a plurality of through holes 340, an insulating layer 350, and a plurality of flexible metal lines 360. The wafer 3 1 has a main surface 311, a back surface 312, and a plurality of pads 3 1 3 formed on the active surface 311. The reconfiguration circuit layer 3 20 is formed on the active surface 31 1 and includes a plurality of reconfiguration pads 321 connected to the pads 313 . The protective layer 305 is formed on the active surface 31 of the wafer 310 and covers the rearrangement layer 320. The protective layer 330 can have a plurality of openings 33, 1 aligned with the reconfiguration pads 3 2 1 , and the apertures thereof are larger than the through holes, so that the reconfiguration pads 3 2 1 have the through holes 3 4 0 The exposed surface of the periphery is for bonding of the flexible metal wires 360. The through holes 340 are formed in the re-arrangement pads 321 and penetrate the wafers 310 from the active surface 3 11 to the back surface 3 1 2 . The insulating layer 35 is formed in the through holes 310, preferably, the insulating layer 350 can be formed on the back surface 31 of the wafer 310 to protect the wafer 3 1 Hey. Each of the flexible wires 36 has a first end 361 and a 14 200921815 second end 362 ′, wherein the first ends 361 are bonded to the reconfigurable 321 , and the second ends 362 are The back surface 33 is protruded through the through holes 34 and protrudes from the back surface 3 1 2 of the 5th wafer 300. In this embodiment, the first ends 361 can be ball ends. The second ends 362 can be suspended wires, and the protective layer on the back surface 312 of the wafer 310 can be omitted. Ie cost and process flow. In addition, the second ends 3 62 of the levable wires 36 can be movable relative to the reconfigurable pads 32 2 . Better f
地，該些可撓性金屬線36〇之第二端362係可沾附有銲 料3 7 0，以對外焊接。 總而言之，本發明以利用該些可撓性金屬線36〇貫 穿^些晶片3丨0之貫穿孔34〇，同時在該主動面3ιι與 该背面312各形成有一突出之第一# 361與第二端 362 ’作為外接端子。當複數個半導體晶片裝置300上 合時能完成晶片之間的高密度電性互連，能提供該 ::片310至晶片310與/或晶片載體之間良好之電性 :接品質’並能簡化製程以縮短製程時間及降低製作成 本發明作任何形式上的的較佳貫施例而已’並非對 所附申請專利範圍為準。 案軌圍备依 利用上述揭示的技術內可，，、、，。本專業的技術人員可 义揭不的技術内容作出些許更動 :化的等效實施例，但凡是未脫離本發C同 t，依據本發明的技術實質對以上實施例所二案的内 早修改、等同變化與修飾，均仍屬於本發明：的任何簡 筏術方案的 15 200921815 範圍内。 【圖式簡單說明】 第1圖：習知具有矽通孔（TSV)之半導體晶片裝置之局 部截面示意圖。 第2圖：依據本發明之第一具體實施例，一種具有矽通 孔（TSV)之半導體晶片裝置之局部截面示意 圖。 第3 A至3 L圖：依據本發明之第一具體實施例，繪示 f 該半導體晶片裝置於製造過程中之局部載面 示意圖。 第4圖：依據本發明之第一具體實施例之變化實施例， 繪示一孔金屬層形成於晶片之貫穿孔内之截 面示意圖。 第5圖：依據本發明之第一具體實施例，複數個半導體 晶片裝置立體堆疊之截面示意圖。 第6圖：依據本發明之第二具體實施例，另一種具有矽 I" 通孔（TSV)之半導體晶片裝置之局部截面示意 圖。 【主要元件符號說明】 10 銲針 20 刀具 30 電路板 100半導體晶片裝置 11 0晶片 111主動面 11 2背面 11 3介電層 120重配置墊 130保護層 140貫穿孔 16 200921815 150 絕 緣層 160 導 電 材料 170 孔 金屬 層 180 外接墊 190 保 護 層 200 半 導體 晶 片 裝 置 210 晶 片 211 主 動 面 212 背 面 213 銲 墊 214 切 割 側 面 220 重 配置 線路層 221 重 配 置 墊 230 第 一保 護 層 23 1 開 孔 240 貫 穿孔 250 絕 緣層 260 可 撓性 金 屬 線 261 第 一端 262 第 —— 端 270 外接墊 280 第 二 保 護層 290 孔 金屬 層 300 半 導體 晶 片 裝 置 310 晶 片 311 主 動 面 3 12 背 面 313 銲墊 320 重 配 置 線路層 321 重 配置 墊 330 保 護層 331 開 孔 340 貫 穿孔 350 絕 緣 層 360 可 撓性 金 屬 線 361 第 一端 362 第 _ — 端 370 銲料 17The second ends 362 of the flexible metal wires 36 are adhered with solder 370 for external soldering. In summary, the present invention utilizes the flexible metal wires 36 to penetrate through the through holes 34 of the wafers 3丨0, and at the same time, the active surfaces 3 ι and the back surface 312 are respectively formed with a protruding first #361 and second. Terminal 362' acts as an external terminal. When a plurality of semiconductor wafer devices 300 are assembled, high-density electrical interconnection between the wafers can be completed, which can provide: good electrical properties between the wafer 310 and the wafer 310 and/or the wafer carrier: Simplifying the process to shorten the process time and reduce the manufacturing cost. The invention is not limited to the scope of the appended claims. The track is prepared according to the techniques disclosed above, and can be used. Those skilled in the art can make some changes to the technical content of the invention, but the equivalent embodiment of the invention, but without departing from the present invention, the internal modification of the second embodiment of the above embodiment is based on the technical essence of the present invention. , equivalent changes and modifications, are still within the scope of the invention: 15 200921815 of any simplistic scheme. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional semiconductor wafer device having a through hole (TSV). Figure 2 is a partial cross-sectional view of a semiconductor wafer device having a through via (TSV) in accordance with a first embodiment of the present invention. 3A to 3L: According to a first embodiment of the present invention, a schematic view of a partial carrier of the semiconductor wafer device during the manufacturing process is shown. Fig. 4 is a cross-sectional view showing a hole metal layer formed in a through hole of a wafer in accordance with a modified embodiment of the first embodiment of the present invention. Figure 5 is a cross-sectional view showing a three-dimensional stack of a plurality of semiconductor wafer devices in accordance with a first embodiment of the present invention. Figure 6 is a partial cross-sectional schematic view of another semiconductor wafer device having a 矽 I" via (TSV) in accordance with a second embodiment of the present invention. [Main component symbol description] 10 soldering pin 20 tool 30 circuit board 100 semiconductor wafer device 11 0 wafer 111 active surface 11 2 back surface 11 3 dielectric layer 120 relocation pad 130 protective layer 140 through hole 16 200921815 150 insulating layer 160 conductive material 170 hole metal layer 180 external pad 190 protective layer 200 semiconductor wafer device 210 wafer 211 active surface 212 back surface 213 pad 214 cutting side 220 reconfiguration circuit layer 221 relocation pad 230 first protective layer 23 1 opening 240 through hole 250 insulation Layer 260 Flexible Metal Wire 261 First End 262 First End 270 External Pad 280 Second Protective Layer 290 Hole Metal Layer 300 Semiconductor Wafer Device 310 Wafer 311 Active Surface 3 12 Back Side 313 Pad 320 Reconfigured Circuit Layer 321 Heavy Configuration pad 330 protective layer 331 opening 340 through hole 350 insulating layer 360 flexible metal wire 361 first end 362 _ - end 370 solder 17