WO2009128301A1 - ダイヤモンド半導体装置及びその製造方法 - Google Patents
ダイヤモンド半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2009128301A1 WO2009128301A1 PCT/JP2009/054264 JP2009054264W WO2009128301A1 WO 2009128301 A1 WO2009128301 A1 WO 2009128301A1 JP 2009054264 W JP2009054264 W JP 2009054264W WO 2009128301 A1 WO2009128301 A1 WO 2009128301A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- diamond
- plane
- substrate
- phosphorus
- doped
- Prior art date
Links
- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 179
- 239000010432 diamond Substances 0.000 title claims abstract description 179
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 229910052698 phosphorus Inorganic materials 0.000 claims description 34
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 27
- 239000011574 phosphorus Substances 0.000 claims description 27
- 239000013078 crystal Substances 0.000 description 40
- 238000005530 etching Methods 0.000 description 23
- 239000010408 film Substances 0.000 description 20
- 125000004437 phosphorous atom Chemical group 0.000 description 13
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 13
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 12
- 239000010409 thin film Substances 0.000 description 12
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 8
- 239000002344 surface layer Substances 0.000 description 8
- 239000002253 acid Substances 0.000 description 6
- 238000005903 acid hydrolysis reaction Methods 0.000 description 6
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 6
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000010348 incorporation Methods 0.000 description 4
- 238000003786 synthesis reaction Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000005355 Hall effect Effects 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 238000005136 cathodoluminescence Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/04—Diamond
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/10—Heating of the reaction chamber or the substrate
- C30B25/105—Heating of the reaction chamber or the substrate by irradiation or electric discharge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02376—Carbon, e.g. diamond-like carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02527—Carbon, e.g. diamond-like carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
- H01L21/041—Making n- or p-doped regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
- H01L21/042—Changing their shape, e.g. forming recesses
Definitions
- the present invention relates to a diamond semiconductor device and a manufacturing method thereof.
- Diamond has a wide band gap, has the highest thermal conductivity among substances, and has high chemical stability, and is being applied to semiconductor devices.
- a semiconductor device using diamond operates stably in a high-temperature environment and a space environment, and can withstand a high-speed and high-power operation, so the necessity is high.
- a p-type diamond semiconductor In order to use diamond as a material for semiconductor devices, p-type or n-type electric conduction control is required.
- a p-type diamond semiconductor also exists in nature and is relatively easy to synthesize artificially.
- a p-type diamond semiconductor can be obtained by introducing a compound containing boron into the chamber as an impurity source during chemical vapor deposition (CVD) of diamond.
- n-type diamond semiconductors do not exist in nature, and until now it has been thought that artificial synthesis is impossible. In 1997, it was obtained by epitaxially growing diamond while doping phosphorus as an n-type impurity on a ⁇ 111 ⁇ plane diamond single crystal substrate (Patent Document 1). However, at that time, when diamond was epitaxially grown on a ⁇ 100 ⁇ plane diamond single crystal substrate under the synthesis conditions as in Patent Document 1 while doping n-type impurities, the doping efficiency was very low and almost no n-type impurities were taken in. There was a problem that conductivity could not be obtained.
- the ⁇ 111 ⁇ plane diamond single crystal substrate has a problem in that high-temperature and high-pressure methods and chemical vapor deposition methods cannot provide a large-area high-quality substrate, and cost reduction cannot be expected.
- the ⁇ 100 ⁇ plane diamond single crystal substrate is relatively easy to increase in area and has a high quality. For this reason, in the development of electronic devices, a technique for growing an n-type diamond semiconductor on the ⁇ 100 ⁇ plane has become essential.
- these methods enable growth of p-type and n-type diamond semiconductors without any restrictions on the plane orientation of the substrate.
- semiconductor devices such as a pn junction type and a pin junction type are progressing based on these technologies.
- the present invention has been made to solve the above problems, and an object of the present invention is to provide a diamond semiconductor device in which an impurity-doped diamond semiconductor is embedded in a selected region and a method for manufacturing the same.
- a diamond semiconductor device having an impurity-doped diamond region embedded in a recess selectively formed in a diamond substrate (2) The diamond semiconductor device according to (1), wherein the diamond substrate is an impurity-doped diamond substrate. (3) The diamond semiconductor device according to (1), wherein the diamond substrate is a diamond substrate having a diamond film formed on the substrate. (4) A main surface of the diamond substrate is a ⁇ 100 ⁇ plane, a side surface of the recess is a ⁇ 110 ⁇ plane, and a bottom surface is a ⁇ 100 ⁇ plane (1), ( The diamond semiconductor device according to 2) or (3).
- the buried semiconductor region forming technique and the selective growth technique are indispensable when manufacturing a semiconductor device, and the width of application of the semiconductor device varies greatly depending on the presence or absence thereof.
- an impurity-doped diamond semiconductor can be embedded in a selected region.
- the contact resistance when a metal and a semiconductor are bonded directly affects the performance of the device, so that a reduction in resistance is required.
- high concentration doping phosphorus concentration of 10 20 cm ⁇ 3 or more
- contact resistance cannot be reduced.
- the diamond semiconductor device and its manufacturing method make this possible.
- the present invention is a diamond semiconductor device having an impurity-doped diamond region (20) embedded in a recess selectively formed in a diamond substrate (10) and a method for manufacturing the same.
- a diamond ⁇ 100 ⁇ plane single crystal substrate (10) is processed, a diamond semiconductor is grown in the ⁇ 111> direction from the bottom angle of the processed recess, and impurity doping is performed simultaneously.
- a buried impurity-doped diamond region (20) is formed.
- the diamond substrate (10) is a non-doped, boron-doped, phosphorus-doped, nitrogen-doped, p-type, or n-type ⁇ 100 ⁇ plane substrate, or a ⁇ 100 ⁇ plane growth film.
- the buried impurity-doped diamond region (20) includes a group V element typified by phosphorus and other impurity elements capable of forming an n-type diamond semiconductor, or a group III element typified by boron, and other impurity elements capable of forming a p-type diamond semiconductor.
- the method for manufacturing a diamond semiconductor device of the present invention includes a step of forming a recess surrounded by a ⁇ 100 ⁇ plane and a side face by a ⁇ 110 ⁇ plane in a region where a buried region on a ⁇ 100 ⁇ plane diamond semiconductor is to be formed.
- the angle at which the ⁇ 100 ⁇ plane and the ⁇ 110 ⁇ plane intersect is the starting point of growth.
- phosphorus is taken as an example of the doping impurity, but this incorporation efficiency strongly depends on the plane orientation of the substrate.
- the phosphorus uptake efficiency is about 0.02%, whereas the ⁇ 100 ⁇ plane substrate is used.
- the phosphorus incorporation efficiency is less than 0.00001%.
- a ⁇ 100 ⁇ plane diamond single crystal substrate is processed to form a recess with ⁇ 110 ⁇ bottom surface and ⁇ 100 ⁇ bottom surface.
- the relationship between the depth D, the width W, and the length L of the recess is preferably 0.7 W ⁇ D ⁇ 1.4 W and W ⁇ L ⁇ (the size of the substrate) (see FIG. 2).
- the ⁇ 100 ⁇ plane on the bottom surface and the ⁇ 110 ⁇ plane on the side surface need only be shifted from the ideal plane by about 0 to 10 °, and there is no need to periodically make recesses.
- the recess by a periodic rectangular protruding structure may be sufficient.
- These recesses are preferably formed only in regions where a buried n-type diamond region is required. If it is not necessary to fill all the recesses, the above conditions may be excluded.
- the impurity-doped diamond semiconductor of the present invention is characterized in that it is selectively embedded only in a recess formed on a ⁇ 100 ⁇ plane diamond single crystal substrate.
- phosphorus doping since epitaxial growth is performed in the ⁇ 111> direction, phosphorus incorporation efficiency is relatively high, and the phosphorus concentration can be controlled in a wide range from 10 16 cm ⁇ 3 to 10 20 cm ⁇ 3 . Further, since it is a buried impurity-doped diamond semiconductor substrate with a ⁇ 100 ⁇ plane orientation substrate, which is essential in device development, it is highly practical.
- the ⁇ 100 ⁇ plane diamond single crystal substrate to be processed may be any of a ⁇ 100 ⁇ plane substrate formed by a high temperature and high pressure method, a substrate formed by a chemical vapor deposition (CVD) method, and a growth film, and doped with impurities. It may be a growth film on a conductive substrate.
- CVD chemical vapor deposition
- the identification of the buried impurity-doped diamond region can be easily confirmed by in-plane distribution measurement using a SIMS measurement or cathodoluminescence measurement by cleaving an appropriate region. Since the concave structure at the time of formation is a feature, the identification is easy.
- Embodiments 1 to 6 of the present invention will be described in detail with reference to FIGS. 3 to 28, the left figure is a plan view of the diamond semiconductor device, and the right figure is a sectional view thereof.
- Example 1 A diamond single crystal substrate (10) having a ⁇ 100 ⁇ surface as shown in FIG. 3 is prepared. As shown in FIG. 4, an Au / Ti thin film mask (Au300 nm / Au) having a line and space of 1 ⁇ m in line width and 1 ⁇ m in the ⁇ 110> direction is formed on a part of the surface of a ⁇ 100 ⁇ plane diamond single crystal substrate by photolithography. Ti 10 nm) (11) was formed.
- the ⁇ 100 ⁇ plane diamond single crystal substrate patterned on the Au / Ti thin film mask shown in FIG. 4 was etched by an inductively coupled plasma etching apparatus.
- the etching gas conditions are O 2 : 95 sccm, CF 4 : 2 sccm, RF power: 300 W, bias: 50 W, pressure: 2 Pa, and the etching depth is 1 ⁇ m.
- the etching selectivity between the ⁇ 100 ⁇ plane diamond single crystal substrate and Au is about 1: 8.
- the phosphorus concentration was examined using SIMS (Secondary Ion Mass Spectroscopy). As a result, phosphorus atoms were selectively incorporated only into the recessed region, and the phosphorus atom concentration was 1 ⁇ 10 20 cm ⁇ 3 .
- electrodes of Ti (30 nm) / Pt (30 nm) / (Au 100 nm) were deposited at an interval of 10 ⁇ m.
- a clear electrical conductivity was obtained from the current-voltage characteristics between the two electrodes, and the specific resistance value was about 2 ⁇ 10 3 ⁇ cm.
- Example 2 A diamond single crystal substrate (10) having a ⁇ 100 ⁇ surface as shown in FIG. 7 is prepared. As shown in FIG. 8, a line / space Au / Ti thin film mask (Au300 nm / Au) having a line width of 1 ⁇ m in the ⁇ 110> direction and an interval of 1 ⁇ m is formed on a part of the surface of a ⁇ 100 ⁇ plane diamond single crystal substrate by photolithography. Ti 10 nm) (11) was formed.
- the ⁇ 100 ⁇ plane diamond single crystal substrate patterned on the Au / Ti thin film mask shown in FIG. 8 was etched by an inductively coupled plasma etching apparatus.
- the etching gas conditions are O 2 : 95 sccm, CF 4 : 2 sccm, RF power: 300 W, bias: 50 W, pressure: 2 Pa, and the etching depth is 1 ⁇ m.
- the etching selectivity between the ⁇ 100 ⁇ plane diamond single crystal substrate and Au is about 1: 8.
- the phosphorus concentration was examined using SIMS (Secondary Ion Mass Spectroscopy). As a result, phosphorus atoms were selectively incorporated only into the recessed region, and the phosphorus atom concentration was 1 ⁇ 10 20 cm ⁇ 3 .
- electrodes of Ti (30 nm) / Pt (30 nm) / (Au 100 nm) were deposited at an interval of 10 ⁇ m.
- a clear electrical conductivity was obtained from the current-voltage characteristics between the two electrodes, and the specific resistance value was about 2 ⁇ 10 3 ⁇ cm.
- Example 3> A diamond single crystal substrate (10) having a ⁇ 100 ⁇ surface as shown in FIG. 11 is prepared. As shown in FIG. 12, a line / space Au / Ti thin film mask (Au300 nm / Au) having a line width of 1 ⁇ m in the ⁇ 100> direction and an interval of 1 ⁇ m is formed on a part of the surface of a ⁇ 100 ⁇ plane diamond single crystal substrate by photolithography. Ti 10 nm) (11) was formed.
- the ⁇ 100 ⁇ plane diamond single crystal substrate patterned on the Au / Ti thin film mask shown in FIG. 12 was etched by an inductively coupled plasma etching apparatus.
- the etching gas conditions are O 2 : 95 sccm, CF 4 : 2 sccm, RF power: 300 W, bias: 50 W, pressure: 2 Pa, and the etching depth is 1 ⁇ m.
- the etching selectivity between the ⁇ 100 ⁇ plane diamond single crystal substrate and Au is about 1: 8.
- the phosphorus concentration was examined using SIMS (Secondary Ion Mass Spectroscopy). As a result, phosphorus atoms were selectively taken into only the region of the recess (12), and the phosphorus atom concentration was about 5 ⁇ 10 17 cm ⁇ 3 .
- Example 4> A diamond single crystal substrate (10) having a ⁇ 100 ⁇ surface as shown in FIG. 15 is prepared. As shown in FIG. 16, a line / space Au / Ti thin film mask (Au300 nm / Au) having a line width of 1 ⁇ m in the ⁇ 100> direction and a space of 1 ⁇ m is formed on a part of the surface of a ⁇ 100 ⁇ plane diamond single crystal substrate by photolithography. Ti 10 nm) (11) was formed.
- the ⁇ 100 ⁇ plane diamond single crystal substrate patterned on the Au / Ti thin film mask shown in FIG. 16 was etched by an inductively coupled plasma etching apparatus.
- the etching gas conditions are O 2 : 95 sccm, CF 4 : 2 sccm, RF power: 300 W, bias: 50 W, pressure: 2 Pa, and the etching depth is 1 ⁇ m.
- the etching selectivity between the ⁇ 100 ⁇ plane diamond single crystal substrate and Au is about 1: 8.
- the phosphorus concentration was examined using SIMS (Secondary Ion Mass Spectroscopy). As a result, phosphorus atoms were selectively incorporated only into the recessed region, and the phosphorus atom concentration was about 5 ⁇ 10 17 cm ⁇ 3 .
- Example 5 A diamond single crystal substrate (10) having a ⁇ 100 ⁇ surface as shown in FIG. 19 is prepared. Using a microwave plasma CVD apparatus, H 2 : 397 sccm, CH 4 : 1.6 sccm, PH 3 : 0.16 sccm, pressure: 3.25 ⁇ 10 3 Pa, microwave power: 750 W, substrate heater temperature: 900 Phosphorous-doped diamond was synthesized under the conditions of °C and growth time of 6 hours. As shown in FIG. 20, a phosphorus-doped n-type diamond semiconductor (13) having a thickness of about 2 ⁇ m was formed.
- a line width of 1 ⁇ m in the ⁇ 100> direction and a spacing of 1 ⁇ m are formed on a part of the surface of a phosphorus-doped n-type diamond semiconductor film (13) formed into a ⁇ 100 ⁇ plane diamond single crystal substrate by photolithography.
- a line / space Au / Ti thin film mask (Au 300 nm / Ti 10 nm) (11) was formed.
- the phosphorus-doped n-type diamond semiconductor film obtained by patterning the Au / Ti thin film mask shown in FIG. 21 was etched by an inductively coupled plasma etching apparatus.
- the etching gas conditions are O 2 : 95 sccm, CF 4 : 2 sccm, RF power: 300 W, bias: 50 W, pressure: 2 Pa, and the etching depth is 1 ⁇ m.
- the etching selectivity between the ⁇ 100 ⁇ plane phosphorus-doped n-type diamond semiconductor film and Au is about 1: 8.
- the phosphorus concentration was examined using SIMS (Secondary Ion Mass Spectroscopy). As a result, phosphorus atoms were selectively incorporated only into the rectangular groove region, and the phosphorus atom concentration was 7 ⁇ 10 19 cm ⁇ 3 . The phosphorus concentration in the region deeper than the recess was 2 ⁇ 10 18 cm ⁇ 3 .
- Electrodes of Ti (30 nm) / Pt (30 nm) / (Au 100 nm) were deposited at an interval of 10 ⁇ m.
- a clear electrical conductivity was obtained from the current-voltage characteristics between the two electrodes, and the specific resistance value was about 2 ⁇ 10 3 ⁇ cm.
- the specific resistance value was about ⁇ 10 6 ⁇ cm.
- a buried high-concentration phosphorus-doped diamond region (20) having a low resistance was obtained in the surface layer of the ⁇ 100 ⁇ plane phosphorus-doped n-type diamond semiconductor film.
- the contact resistance of the n-type diamond region (20) embedded in the rectangular groove was evaluated using a linear TLM (Transfer Length Method) method, the contact resistance when Ti was deposited was 1 ⁇ 10 ⁇ 2 ⁇ cm. 2 was obtained.
- the contact resistance is 10 5 ⁇ cm 2 or more, and the ⁇ 100 ⁇ plane phosphorus-doped n-type diamond semiconductor It was confirmed that it was extremely effective in reducing the contact resistance of the film.
- a diamond single crystal substrate (10) having a ⁇ 100 ⁇ surface as shown in FIG. 24 is prepared.
- H 2 397 sccm, CH 4 : 1.2 sccm
- B 2 H 6 / H 2 gas 100 ppm: 0.6 sccm
- pressure 3.25 ⁇ 10 3 Pa
- microwave power Boron-doped diamond was synthesized under the conditions of 750 W, substrate heater temperature: 800 ° C., and growth time of 6 hours.
- a boron-doped p-type diamond semiconductor (14) having a thickness of about 2 ⁇ m was formed.
- a line width of 1 ⁇ m in the ⁇ 100> direction and a spacing of 1 ⁇ m are formed on a part of the surface of a boron-doped p-type diamond semiconductor film (14) formed into a ⁇ 100 ⁇ plane diamond single crystal substrate by photolithography.
- a line / space Au / Ti thin film mask (Au 300 nm / Ti 10 nm) (11) was formed.
- the boron-doped p-type diamond semiconductor film patterned on the Au / Ti thin film mask was etched by an inductively coupled plasma etching apparatus.
- the etching gas conditions are O 2 : 95 sccm, CF 4 : 2 sccm, RF power: 300 W, bias: 50 W, pressure: 2 Pa, and the etching depth is 1 ⁇ m.
- the selection ratio between the ⁇ 100 ⁇ plane boron-doped p-type diamond semiconductor film and Au is about 1: 8.
- the diamond semiconductor substrate according to the present invention includes a substrate made of ceramic or the like, or a substrate in which a diamond film is formed on the diamond substrate.
- a plane orientation such as ⁇ 100 ⁇ plane includes a nearby off-plane.
- the diamond semiconductor device of the present invention is used not only in semiconductor devices such as power semiconductor elements and high-frequency semiconductor elements, but also in various electronic devices such as ultraviolet light emitting devices, electron emission sources, X-ray / particle beam sensors, and X-ray / particle position sensors. Can be applied.
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Chemical Vapour Deposition (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
(1){100}面を加工し、ダイヤモンド成長時のαパラメータ制御により{111}面を成長させ、{100}面上に形成した{111}面へn型ダイヤモンド半導体を成長させる手法(特許文献2)。
(2) 特許文献1とは異なる合成条件で{100}面ダイヤモンド単結晶基板上へ直接n型不純物をドープしながらダイヤモンドをエピタキシャル成長させる手法(特許文献3)。
(1)ダイヤモンド基板に選択的に形成した凹所内に埋設された不純物ドープダイヤモンド領域を有するダイヤモンド半導体装置。
(2)前記ダイヤモンド基板は、不純物ドープダイヤモンド基板であることを特徴とする(1)に記載のダイヤモンド半導体装置。
(3)前記ダイヤモンド基板は、基板上にダイヤモンド膜が形成されたダイヤモンド基板であることを特徴とする(1)に記載のダイヤモンド半導体装置。
(4)前記ダイヤモンド基板の主表面は、{100}面であり、前記凹所の側面は、{110}面であり、底面は{100}面であることを特徴とする(1)、(2)又は(3)に記載のダイヤモンド半導体装置。
(5){100}面ダイヤモンド半導体基板に、底面が{100}面、側面が{110}面で囲まれた凹所を選択的に形成する工程と、不純物をドープしながらダイヤモンドを<111>方向へエピタキシャル成長させ該凹所を埋めることにより不純物ドープダイヤモンド領域を形成する工程とを含むダイヤモンド半導体装置の製造方法。
(6)前記不純物は、リンであることを特徴とする(5)に記載のダイヤモンド半導体装置の製造方法。
本発明のダイヤモンド半導体装置及びその製造方法によれば、選択された領域に不純物ドープダイヤモンド半導体を埋め込むことができる。
特に、{100}面でのn型ダイヤモンド半導体において、従来技術では高濃度ドーピング(リン濃度1020cm-3以上)が行えないため、接触抵抗の低減が不可能であったが、本発明のダイヤモンド半導体装置及びその製造方法はこれを可能にする。
本発明は、ダイヤモンド基板(10)に選択的に形成した凹所内に埋設された不純物ドープダイヤモンド領域(20)を有するダイヤモンド半導体装置及びその製造方法である。
本発明の好ましい実施例では、ダイヤモンド{100}面単結晶基板(10)を加工し、加工した凹所の底角からダイヤモンド半導体を<111>方向へ成長させ、かつ不純物ドーピングを同時に行うことで、埋め込み不純物ドープダイヤモンド領域(20)を形成する。
ダイヤモンド基板(10)は、ノンドープ、ボロンドープ、リンドープ、窒素ドープ、p型、n型のいずれかの{100}面基板、又は{100}面成長膜である。埋め込み不純物ドープダイヤモンド領域(20)は、リンを代表とするV族元素、及びその他n型ダイヤモンド半導体ができる不純物元素、又はボロンを代表とするIII属元素、及びその他p型ダイヤモンド半導体ができる不純物元素を有する。
なおリンの取り込み効率は、次の数式により算出される。
リンの取り込み効率=ダイヤモンド中の炭素原子に対するリン原子濃度([P]/[C])/気相中のメタンに対するホスフィン濃度([PH3]/[CH4])
なお、凹所を全て埋める必要がなければ、上記の条件から外れてもよい。
加工する{100}面ダイヤモンド単結晶基板は、高温高圧法により形成された{100}面基板、化学気相成長(CVD)法で形成された基板及び成長膜のいずれでもよく、また不純物がドープされた導電性基板上の成長膜でもよい。
図3乃至図28において、それぞれ左図はダイヤモンド半導体装置の平面図、右図はその断面図である。
図3に示すような表面が{100}面を有するダイヤモンド単結晶基板(10)を用意する。図4に示すように、フォトリソグラフィ法によって、{100}面ダイヤモンド単結晶基板の表面の一部に<110>方向に線幅1μm、間隔1μmのライン&スペースのAu/Ti薄膜マスク(Au300nm/Ti10nm)(11)を形成した。
図7に示すような表面が{100}面を有するダイヤモンド単結晶基板(10)を用意する。図8に示すように、フォトリソグラフィ法によって、{100}面ダイヤモンド単結晶基板の表面の一部に<110>方向に線幅1μm、間隔1μmのライン&スペースのAu/Ti薄膜マスク(Au300nm/Ti10nm)(11)を形成した。
図11に示すような表面が{100}面を有するダイヤモンド単結晶基板(10)を用意する。図12に示すように、フォトリソグラフィ法によって、{100}面ダイヤモンド単結晶基板の表面の一部に<100>方向に線幅1μm、間隔1μmのライン&スペースのAu/Ti薄膜マスク(Au300nm/Ti10nm)(11)を形成した。
図15に示すような表面が{100}面を有するダイヤモンド単結晶基板(10)を用意する。図16に示すように、フォトリソグラフィ法によって、{100}面ダイヤモンド単結晶基板の表面の一部に<100>方向に線幅1μm、間隔1μmのライン&スペースのAu/Ti薄膜マスク(Au300nm/Ti10nm)(11)を形成した。
図19に示すような表面が{100}面を有するダイヤモンド単結晶基板(10)を用意する。マイクロ波プラズマCVD装置を使用して、H2:397sccm、CH4:1.6sccm、PH3:0.16sccm、圧力:3.25×103Pa、マイクロ波パワー:750W、基板ヒータ温度:900℃、成長時間6時間の条件で、リンドープダイヤモンドの合成を行った。
図20のように、約2μm程度の膜厚のリンドープn型ダイヤモンド半導体(13)を形成した。ホール効果測定から、室温から700℃付近まで安定してn型判定が得られ、温度依存性の傾きからリンドナーの570meVの活性化エネルギーが見積もられ、{100}面ダイヤモンド単結晶基板上にリンドープn型ダイヤモンド半導体が形成されたことを確認した。
図24に示すような表面が{100}面を有するダイヤモンド単結晶基板(10)を用意する。マイクロ波プラズマCVD装置を使用して、H2:397sccm、CH4:1.2sccm、B2H6/H2ガス=100ppm:0.6sccm、圧力:3.25×103Pa、マイクロ波パワー:750W、基板ヒータ温度:800℃、成長時間6時間の条件で、ボロンドープダイヤモンドの合成を行った。図25のように、約2μm程度の膜厚のボロンドープp型ダイヤモンド半導体(14)を形成した。ホール効果測定から、室温から700℃付近まで安定してp型判定が得られ、温度依存性の傾きからボロンアクセプターの370meVの活性化エネルギーが見積もられ、{100}面ダイヤモンド単結晶基板上にボロンドープp型ダイヤモンド半導体が形成されたことを確認した。
例えば本発明に係るダイヤモンド半導体基板には、セラミック等の基板上、あるいはダイヤモンド基板上にダイヤモンド膜が形成された基板も含まれる。
また例えば{100}面等の面方位には、近傍のオフ面もこれに含まれる。
Claims (6)
- ダイヤモンド基板に選択的に形成した凹所内に埋設された不純物ドープダイヤモンド領域を有するダイヤモンド半導体装置。
- 前記ダイヤモンド基板は、不純物ドープダイヤモンド基板であることを特徴とする請求項1に記載のダイヤモンド半導体装置。
- 前記ダイヤモンド基板は、基板上にダイヤモンド膜が形成されたダイヤモンド基板であることを特徴とする請求項1に記載のダイヤモンド半導体装置。
- 前記ダイヤモンド基板の主表面は、{100}面であり、前記凹所の側面は、{110}面であり、底面は{100}面であることを特徴とする請求項1、2又は3に記載のダイヤモンド半導体装置。
- {100}面ダイヤモンド半導体基板に、底面が{100}面、側面が{110}面で囲まれた凹所を選択的に形成する工程と、不純物をドープしながらダイヤモンドを<111>方向へエピタキシャル成長させ該凹所を埋めることにより不純物ドープダイヤモンド領域を形成する工程とを含むダイヤモンド半導体装置の製造方法。
- 前記不純物は、リンであることを特徴とする請求項5に記載のダイヤモンド半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/988,089 US8624263B2 (en) | 2008-04-17 | 2009-03-06 | Diamond semiconductor device and method of manufacturing the same |
JP2010508147A JP5299921B2 (ja) | 2008-04-17 | 2009-03-06 | ダイヤモンド半導体装置及びその製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-108365 | 2008-04-17 | ||
JP2008108365 | 2008-04-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009128301A1 true WO2009128301A1 (ja) | 2009-10-22 |
Family
ID=41199001
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/054264 WO2009128301A1 (ja) | 2008-04-17 | 2009-03-06 | ダイヤモンド半導体装置及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8624263B2 (ja) |
JP (1) | JP5299921B2 (ja) |
WO (1) | WO2009128301A1 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014027600A1 (ja) * | 2012-08-17 | 2014-02-20 | 独立行政法人産業技術総合研究所 | ダイヤモンド半導体装置及びその製造方法 |
JP2016103651A (ja) * | 2015-12-25 | 2016-06-02 | 国立研究開発法人産業技術総合研究所 | ダイヤモンド半導体装置及びその製造方法 |
JP2017154908A (ja) * | 2016-02-29 | 2017-09-07 | 信越化学工業株式会社 | ダイヤモンド基板の製造方法、ダイヤモンド基板及びダイヤモンド自立基板 |
JP2017154909A (ja) * | 2016-02-29 | 2017-09-07 | 信越化学工業株式会社 | ダイヤモンド基板の製造方法 |
US10170561B1 (en) | 2017-09-07 | 2019-01-01 | Kabushiki Kaisha Toshiba | Diamond semiconductor device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201342423A (zh) * | 2012-04-13 | 2013-10-16 | Nation Chiao Tung University | 散熱基板與其製作方法 |
CN105047537A (zh) * | 2015-07-22 | 2015-11-11 | 芜湖德豪润达光电科技有限公司 | 一种不连续外延层的制备方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003106743A1 (ja) * | 2002-06-01 | 2003-12-24 | 住友電気工業株式会社 | n型半導体ダイヤモンド製造方法及び半導体ダイヤモンド |
JP2005335988A (ja) * | 2004-05-25 | 2005-12-08 | Tama Tlo Kk | ダイヤモンド膜付き基板とダイヤモンド膜およびそれらの形成方法、半導体装置、光デバイス、マイクロフィルタ、マイクロマシン用部品、装飾表示基板並びに砥粒 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08180067A (ja) * | 1994-12-26 | 1996-07-12 | Nec Corp | データベースレコード圧縮システム |
JP3051912B2 (ja) | 1996-09-03 | 2000-06-12 | 科学技術庁無機材質研究所長 | リンドープダイヤモンドの合成法 |
US20080193366A1 (en) * | 2005-02-03 | 2008-08-14 | National Institue Of Advanced Industrial Science And Technology | Film of N Type (100) Oriented Single Crystal Diamond Semiconductor Doped with Phosphorous Atoms, and a Method of Producing the Same |
-
2009
- 2009-03-06 US US12/988,089 patent/US8624263B2/en not_active Expired - Fee Related
- 2009-03-06 JP JP2010508147A patent/JP5299921B2/ja not_active Expired - Fee Related
- 2009-03-06 WO PCT/JP2009/054264 patent/WO2009128301A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003106743A1 (ja) * | 2002-06-01 | 2003-12-24 | 住友電気工業株式会社 | n型半導体ダイヤモンド製造方法及び半導体ダイヤモンド |
JP2005335988A (ja) * | 2004-05-25 | 2005-12-08 | Tama Tlo Kk | ダイヤモンド膜付き基板とダイヤモンド膜およびそれらの形成方法、半導体装置、光デバイス、マイクロフィルタ、マイクロマシン用部品、装飾表示基板並びに砥粒 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014027600A1 (ja) * | 2012-08-17 | 2014-02-20 | 独立行政法人産業技術総合研究所 | ダイヤモンド半導体装置及びその製造方法 |
US9478619B2 (en) | 2012-08-17 | 2016-10-25 | National Institute Of Advanced Industrial Science And Technology | Diamond semiconductor device and method for manufacturing same |
JP2016103651A (ja) * | 2015-12-25 | 2016-06-02 | 国立研究開発法人産業技術総合研究所 | ダイヤモンド半導体装置及びその製造方法 |
JP2017154908A (ja) * | 2016-02-29 | 2017-09-07 | 信越化学工業株式会社 | ダイヤモンド基板の製造方法、ダイヤモンド基板及びダイヤモンド自立基板 |
JP2017154909A (ja) * | 2016-02-29 | 2017-09-07 | 信越化学工業株式会社 | ダイヤモンド基板の製造方法 |
US10170561B1 (en) | 2017-09-07 | 2019-01-01 | Kabushiki Kaisha Toshiba | Diamond semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US8624263B2 (en) | 2014-01-07 |
JPWO2009128301A1 (ja) | 2011-08-04 |
US20110037076A1 (en) | 2011-02-17 |
JP5299921B2 (ja) | 2013-09-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5299921B2 (ja) | ダイヤモンド半導体装置及びその製造方法 | |
JP4218639B2 (ja) | n型半導体ダイヤモンド製造方法及び半導体ダイヤモンド | |
JP5967572B2 (ja) | ダイヤモンド半導体装置及びその製造方法 | |
JP3650727B2 (ja) | 炭化珪素製造方法 | |
KR101643758B1 (ko) | 분자빔 에피탁시 방법을 이용한 카본 절연층 제조방법 및 이를 이용한 전계효과 트랜지스터 제조방법 | |
CN109727846B (zh) | 大面积制备金属相与半导体相接触的二维碲化钼面内异质结的方法及应用 | |
EP2413348B1 (en) | Semiconductor substrate, semiconductor device, and method of producing semiconductor substrate | |
JP5846458B2 (ja) | ダイヤモンド半導体装置及びその製造方法 | |
JP2006273592A (ja) | ダイヤモンド基板及びその製造方法 | |
EP2226413B1 (en) | Method for manufacturing diamond monocrystal having a thin film, and diamond monocrystal having a thin film. | |
CN117512559A (zh) | 一种原位c掺杂的p型六方氮化硼薄膜及其制备方法 | |
JP5742712B2 (ja) | 炭化珪素半導体装置の製造方法 | |
JP2008004726A (ja) | 半導体素子およびその製造方法 | |
WO2004061167A1 (ja) | 低抵抗n型半導体ダイヤモンドおよびその製造方法 | |
US20140308782A1 (en) | Self-limiting selective epitaxy process for preventing merger of semiconductor fins | |
JP2004343133A (ja) | 炭化珪素製造方法、炭化珪素及び半導体装置 | |
CN117558762B (zh) | 一种沟槽型mosfet及制备方法 | |
JP6124373B2 (ja) | ダイヤモンド半導体装置及びその製造方法 | |
JP5028879B2 (ja) | 薄膜付きダイヤモンド単結晶の製造方法、及び薄膜付きダイヤモンド単結晶 | |
JP4241174B2 (ja) | 低抵抗n型半導体ダイヤモンド | |
JP5194437B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2009081155A (ja) | 炭化珪素半導体素子の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09731901 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12988089 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2010508147 Country of ref document: JP |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09731901 Country of ref document: EP Kind code of ref document: A1 |