WO2009119600A1 - Procédé permettant de fabriquer une carte de circuit imprimé, et carte de circuit imprimé - Google Patents

Procédé permettant de fabriquer une carte de circuit imprimé, et carte de circuit imprimé Download PDF

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Publication number
WO2009119600A1
WO2009119600A1 PCT/JP2009/055846 JP2009055846W WO2009119600A1 WO 2009119600 A1 WO2009119600 A1 WO 2009119600A1 JP 2009055846 W JP2009055846 W JP 2009055846W WO 2009119600 A1 WO2009119600 A1 WO 2009119600A1
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WO
WIPO (PCT)
Prior art keywords
via hole
resin layer
conductive paste
wiring board
cured
Prior art date
Application number
PCT/JP2009/055846
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English (en)
Japanese (ja)
Inventor
裕之 関本
Original Assignee
株式会社村田製作所
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Priority to JP2010505686A priority Critical patent/JP4748281B2/ja
Publication of WO2009119600A1 publication Critical patent/WO2009119600A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a wiring board having vias and the wiring board.
  • Patent Document 1 discloses that a wiring pattern is formed on one surface of a hard substrate, an adhesive layer is formed on the other surface, and the hard substrate and the adhesive layer are penetrated. A method of forming a hole in contact with the wiring pattern and filling the hole with a conductive paste is disclosed.
  • FIG. 9 shows an example of the manufacturing method disclosed in Patent Document 1.
  • a hard resin substrate 50 having a metal foil 51 attached to the upper surface is prepared, and the metal foil 51 is etched to form a wiring pattern 51a as shown in (b).
  • an adhesive layer 52 is laminated on one surface of the resin substrate 50 as shown in (c), and then laser is irradiated from the adhesive layer side as shown in (d), thereby the adhesive layer 52 and the resin substrate. 50 via holes 53 are formed.
  • a single-sided wiring board can be obtained by filling the via hole 53 with the conductive paste 54 as shown in FIG. At this time, the adhesive layer 52 and the conductive paste 54 are uncured.
  • the adhesive layer 52 and the conductive paste 54 are thermally cured at the same time, as shown in FIG. A multilayer wiring board can be obtained.
  • the laser beam is reflected by the wiring pattern 51 a and cuts the inner wall of the via hole 53.
  • the shape is tapered. In the case of the tapered via hole 53, the diameter of the bottom surface of the via hole is reduced. Therefore, in order to secure the connection area between the conductive paste 54 and the wiring pattern 51a on the bottom surface of the via hole, it is necessary to increase the diameter of the opening of the via hole 53. is there.
  • the thickness of the substrate 50 is increased by the amount of the adhesive layer 52, and when the laser is irradiated from above, the diameter of the opening of the via hole 53 is It gets bigger. As a result, there is a drawback that the pitch between vias cannot be narrowed and hinders fine wiring.
  • the unhardened adhesive bond layer 52 is irradiated with a laser beam.
  • the diameter of the via hole 53 of the adhesive layer 52 becomes larger than necessary.
  • the conductive paste 54 filled in the via hole of the resin substrate 50 and the via hole of the adhesive layer 52 is cured after being multilayered as shown in FIG.
  • the solvent contained in the conductive paste 54 is sufficient. There is a possibility of remaining without being emitted. In the subsequent process, when the entire substrate is heated, the remaining solvent expands, which may reduce the connection reliability between the via and the wiring.
  • An object of a preferred embodiment of the present invention is to provide a method of manufacturing a wiring board that can process a via hole without enlarging the diameter more than necessary, can be easily miniaturized, and can improve the connection reliability between the via and the wiring. It is to provide a wiring board.
  • the method for manufacturing a wiring board according to the present invention includes a first step of preparing a cured first resin layer having a conductor pattern and having a bottomed first via hole having the conductor pattern as a bottom surface. A second step of filling the first via hole with a conductive paste and curing the conductive paste; a third step of polishing the surface of the conductive paste filled in the first via hole; A fourth step of preparing an uncured second resin layer in which a second via hole penetrating at a position corresponding to one via hole is formed, and the first via hole and the second via hole are continuously provided Thus, a fifth step of laminating the first resin layer and the second resin layer and a sixth step of filling the second via hole with a conductive paste are provided.
  • the wiring board according to the present invention has a conductor pattern, a first resin layer having a bottomed first via hole with the conductor pattern as a bottom surface, and embedded in the first resin layer, And a circuit component mounted on the conductor pattern, a first conductive paste that is filled and cured in the first via hole, and the surface exposed on the upper surface of the first resin layer is polished, and a first conductive paste that penetrates vertically. 2 via holes are formed, the upper end opening of the second via hole is formed with a smaller diameter than the upper end opening of the first via hole, and the lower end opening of the second via hole is the upper end of the first via hole.
  • a method for manufacturing a wiring board according to the present invention will be described.
  • a cured first resin layer having a conductor pattern and having a bottomed first via hole having the conductor pattern as a bottom surface is prepared.
  • the first resin layer is formed by curing the resin layer. May be.
  • a first via hole having a conductor pattern as a bottom surface is formed in the first resin layer, and laser processing can be used at that time.
  • the via hole When the first via hole having the conductor pattern as the bottom surface is formed by laser processing, the via hole inevitably becomes a taper shape, but the first resin layer before the second resin layer is laminated is formed. Since laser processing is sufficient, the depth of the first via hole can be made relatively shallow, and an increase in the diameter of the opening can be suppressed.
  • the resin removed by laser irradiation may adhere to the periphery of the via hole or the surface of the wiring pattern, but the first resin layer is a cured resin plate, so that it is well known such as wet desmear treatment or dry plasma treatment The smear can be easily removed by this method.
  • the first via hole is filled with a conductive paste, and the conductive paste is cured.
  • the conductive paste is cured in a state of being exposed to the outside, the solvent contained in the conductive paste easily diverges, and a decrease in reliability due to the residual solvent can be prevented.
  • an uncured second resin layer having a second via hole is laminated on the cured first resin layer, and the second via hole is filled with the conductive paste to form the first paste. Conduction with the hardened conductive paste filled in the via hole.
  • the surface of the cured conductive paste is likely to be resin-rich, and when an uncured conductive paste is brought into contact with this conductive paste, the conduction resistance may increase at the interface between both conductive pastes.
  • the resin-rich surface layer is removed to expose the conductive portion on the surface. And the conduction resistance at the interface of the conductive paste can be lowered.
  • the second via hole of the second resin layer is formed separately from the first via hole of the first resin layer, the second via hole is not affected by the enlargement of the diameter as in the case of forming both via holes simultaneously. In other words, even if the opening diameter of the first via hole is increased by laser processing, the diameter of the second via hole can be made smaller than the opening diameter of the first via hole, and fine wiring can be realized.
  • the second via hole is a through hole, the second via hole is not limited to laser processing, and can be formed by other methods such as drilling or punching. Since the uncured second resin layer is laminated on the first resin layer and the second via hole is filled with the conductive paste in a state where they are in close contact with each other, the conductive paste becomes the first resin layer and the second resin layer. Therefore, a highly reliable wiring board can be obtained.
  • the polishing operation is simplified.
  • a film having a through hole is laminated on the first resin layer, and the first via hole and the film of the first resin layer are laminated.
  • the conductive paste may be filled with the conductive paste at the same time, and then the film may be peeled off so that the conductive paste partially protrudes from the surface of the first resin layer.
  • the resin-rich layer can be entirely accommodated in the protrusion, and the conductive material can be easily exposed by a subsequent polishing process. become.
  • the diameter of the through hole of the film is larger than the opening diameter of the first via hole.
  • buffing can be used as a method for polishing the surface of the conductive paste. Buffing is suitable when there are steps on the polished surface.
  • the bottom diameter of the second via hole is preferably made smaller than the opening diameter of the first via hole.
  • the wiring pattern formed on the second resin layer can be formed more finely.
  • the pitch of the first via hole and the pitch of the second via hole need to correspond accurately, but when the diameter of the second via hole is made smaller than the opening diameter of the first via hole, Can be absorbed.
  • a metal foil is pressure-bonded to the uncured second resin layer, and the metal foil is applied to an uncured conductive paste filled in the second via hole.
  • the metal foil is fixed to the second resin layer, and the metal foil and the conductive paste are electrically connected. Thereafter, a metal foil may be patterned.
  • the wiring formed on the second resin layer can be sequentially multilayered by appropriately mounting circuit components and forming a resin layer thereon.
  • a multilayer substrate may be formed by pressure bonding a substrate having a wiring pattern formed on the lower surface.
  • the first resin layer and the second resin layer in the present invention may be composed of various resin materials such as epoxy-based, polyimide-based, acrylate-based, phenol-based, etc., thermosetting resin and inorganic filler, Or a composite of carbon fiber or glass fiber impregnated with resin.
  • a conductor pattern is formed on a core substrate, a circuit component is mounted on the conductor pattern, and an uncured first resin layer is pressure-bonded and cured from the first circuit layer.
  • the resin layer and the core substrate may be integrated, and the circuit component may be embedded in the first resin layer.
  • a conductor pattern is formed on the carrier, circuit components are mounted on the conductor pattern, and an uncured first resin layer is pressure-bonded and cured from above to form a first resin layer. After the circuit component is embedded in the carrier, the carrier may be peeled off from the first resin layer. In this case, the conductor pattern is exposed on the bottom surface of the first resin layer.
  • the conductive paste is cured while being exposed to the outside. It is easy to remove the solvent contained in the solvent, and it is possible to prevent a decrease in reliability due to residual solvent. Further, in the present invention, since the surface of the cured conductive paste filled in the first via hole is polished to remove the resin-rich surface layer, the uncured second layer is removed from the first resin layer. When the resin layer is laminated and the second via hole is filled with the conductive paste, the conduction resistance at the interface of the conductive paste of both via holes can be lowered.
  • the second via hole of the second resin layer is formed separately from the first via hole of the first resin layer, even if the opening diameter of the first via hole is increased, the second via hole is formed. In addition to the opening diameter of the first via hole, the diameter can be made smaller, and fine wiring can be realized. Since the smear generated during the processing of the first via hole can be removed before the second resin layer is laminated, the smear can be easily removed by a known method, and a wiring board having high electrical reliability can be obtained. .
  • the surface of the first conductive paste filled in the first via hole of the first resin layer is polished to remove the resin-rich surface layer.
  • the conduction resistance at the interface between the conductive paste and the second conductive paste can be reduced, and a wiring board with high electrical reliability can be obtained.
  • the upper end opening diameter of the second via hole formed in the second resin layer is smaller than the upper end opening diameter of the first via hole formed in the first resin layer, the opening of the first via hole is not performed. Even if the aperture is increased, the wiring pattern formed on the upper surface of the second resin layer can be miniaturized.
  • FIG. 1 is a sectional view of a first embodiment of a wiring board according to the present invention.
  • the wiring board A of the present embodiment is configured as a component built-in board having circuit components built therein.
  • the wiring board A is a laminate of three resin layers.
  • the lowermost resin layer is a wired core substrate 1 (for example, a printed wiring board), and a conductive pattern 2 having mounting lands 2a and via lands 2b for mounting circuit components is formed on the surface thereof. ing.
  • wiring may be provided as appropriate on the back surface or inside of the core substrate 1 so as to be electrically connected via the land and via on the surface.
  • a circuit component 3 is mounted on the mounting land 2a by soldering or the like.
  • FIG. 1 shows an example in which the circuit component 3 is a two-terminal chip component, it may be a multi-terminal electronic component (for example, an integrated circuit).
  • the core substrate 1 is not limited to a resin substrate, and may be a ceramic substrate such as LTCC.
  • the first resin layer 4 is formed on the core substrate 1, and the circuit component 3 is embedded in the first resin layer 4.
  • the resin layer 4 is composed of a thermosetting resin such as an epoxy resin or a phenol resin, a mixture in which an inorganic filler is mixed with a thermosetting resin, or a composite material in which a glass fiber or carbon fiber is impregnated with a thermosetting resin.
  • a via hole 4a penetrating in the thickness direction is formed at a position of the resin layer 4 corresponding to the via land 2b of the core substrate 1, and the conductive paste 5 is filled and cured in the via hole 4a.
  • the via hole 4a is a tapered hole that is formed by laser processing and expands in diameter upward.
  • a second resin layer 6 thinner than the resin layer 4 is laminated and fixed on the first resin layer 4.
  • the second resin layer 6 is preferably made of the same thermosetting resin as the first resin layer 4.
  • a via hole 6a penetrating vertically is formed at a position of the second resin layer 6 corresponding to the via hole 4a of the first resin layer 4, and the conductive paste 7 is filled and cured in the via hole 6a, so that the inside of the via hole 4a Is electrically connected to the conductive paste 5 filled therein.
  • a wiring pattern 8 is formed on the upper surface of the second resin layer 6.
  • the wiring pattern 8 is composed of two via lands 8a formed at positions corresponding to the via holes 6a and one electrode 8b, but the wiring pattern shape is arbitrary.
  • Via land 8 a on the upper surface of second resin layer 6 and via land 2 b of core substrate 1 are electrically connected to each other via conductive pastes 7 and 5.
  • the second via hole 6a is a tapered hole whose diameter increases upward, but the second via hole 6a may be a straight hole having the same upper end opening diameter and lower end opening diameter.
  • the upper end opening diameter D2 of the second via hole 6a is smaller than the upper end opening diameter D1 of the first via hole 4a.
  • FIGS. 2 shows the first stage of the manufacturing process
  • FIG. 3 shows the second stage of the manufacturing process
  • FIG. 4 shows the final stage of the manufacturing process.
  • the manufacturing method of the wiring board A in the sub-board state will be described, but in actuality, it is manufactured in the collective board state and then divided into the sub-boards.
  • a core substrate 1 having a conductor pattern 2 formed on the upper surface is prepared, and a circuit component 3 is mounted on a mounting land 2a.
  • the core substrate 1 is created by a known printed wiring technique.
  • an uncured first resin layer 4 thicker than the component height is stacked and pressure-bonded on the core substrate 1.
  • the thickness of the first resin layer 4 is, for example, 400 to 500 ⁇ m.
  • Uncured means a semi-cured (for example, B stage) state or a softer state.
  • the softened resin enters the gap between the circuit component 3 and the core substrate 1, and the circuit component 3 is embedded in the resin layer 4.
  • the embedding condition is, for example, a temperature of 80 to 140 ° C.
  • the first resin layer 4 having the mounting land 2a and the via land 2b on the bottom surface is formed.
  • laser light is irradiated from above the cured resin layer 4 to process the bottomed via hole 4a with the via land 2b as the bottom surface.
  • the shape of the via hole 4a becomes a tapered shape whose diameter increases upward.
  • a desmear process is performed for cleaning the surface of the land 2b which is the bottom surface of the bottomed via hole 4a.
  • the desmear treatment may be either dry or wet.
  • a film 10 with an adhesive having a through hole 10a at the same position as the via hole 4a is prepared and affixed on the resin layer 4 with a laminator or a hand.
  • a PET film can be used as the film 10.
  • the thickness of the film 10 is desirably about 25 to 100 ⁇ m, and the through hole 10a formed in the film 10 is desirably equal to or larger than the opening diameter of the via hole 4a.
  • the film 10 is attached on the cured resin layer 4, and the via hole 4 a and the through hole 10 a are simultaneously formed by irradiating the laser beam. You may perform a desmear process.
  • the conductive paste 5 is filled in the via holes 4a and the through holes 10a by the printer 11 and cured.
  • the conductive paste 5 is cured by heating at about 160 to 200 ° C. Since the hardening of the conductive paste 5 can be performed in a state exposed to the outside, the solvent component contained in the conductive paste 5 can be surely volatilized.
  • the conductive paste 5 contains a conductive filler in a resin, and when cured, the surface tends to be resin-rich.
  • the projecting portion 5a is made by sticking the film 10 in this manner in order to prevent the resin layer 4 from being polished in the subsequent polishing step by projecting a resin-rich portion having a small conductive component. is there.
  • the upper 10 to 30 ⁇ m is considered to be a resin-rich layer. Therefore, if the protruding portion 5a is formed using the film 10 thicker than the resin-rich layer, the resin-rich layer can be entirely accommodated in the protruding portion 5a, and the conductive material can be easily exposed by a subsequent polishing process. Become.
  • the protruding portion 5a of the conductive paste 5 protruding in a protruding shape on the upper surface of the resin layer 4 is removed by physical polishing, and the resin layer 4 and the top surface of the conductive paste 5 are separated. Make it coplanar. Polishing can be performed, for example, with a buff 12 of about # 200 to # 600. By polishing the protruding portion 5 a of the resin rich surface layer, the conductive portion is exposed on the surface of the conductive paste 5.
  • an uncured resin layer 6 with a protective film 13 having a via hole 6a and a through hole 13a at the same position as the via hole 4a on the upper surface of the resin layer 4 is prepared, and pin lamination is performed.
  • the resin layer 6 is pressure-bonded onto the resin layer 4 with a press machine in a state where the positions are aligned.
  • the pressing conditions are performed by applying a temperature of about 50 to 120 ° C. and a pressure of about 0.1 to 5.0 MPa.
  • the thickness of the protective film 13 is desirably about 12.5 to 50 ⁇ m.
  • the via hole 6a and the through hole 13a are not limited to laser processing, and can be processed by a known method such as punching or drilling.
  • the via hole 6a can be a hole having a smaller diameter than the diameter of the opening of the via hole 4a. Therefore, the via holes 6a can be formed with a narrow pitch corresponding to the via lands 8a formed thereon.
  • the shape of the via hole 6a is also drawn as a taper shape, but it goes without saying that it may be a straight shape.
  • the conductive paste 7 is filled in the via holes 6a and the through holes 13a by a printing machine (not shown), and then the protective film 13 is peeled off. As a result, the conductive paste 7 is formed on the surface of the resin layer 6 so as to protrude by the thickness of the protective film 13. At this time, both the resin layer 6 and the conductive paste 7 are in an uncured state.
  • the copper foil 8 is pressure-bonded to the release surface of the resin layer 6 by a press machine.
  • the pressing conditions are performed by applying a temperature of about 50 to 120 ° C. and a pressure of about 0.1 to 5.0 MPa.
  • the resin layer 6 and the conductive paste 7 are collectively cured by heating at 160 to 200 ° C.
  • the conductive paste 7 protrudes from the surface of the resin layer 6, the density of the conductive paste 7 in the via hole 6 a is increased by crimping the copper foil 8, the conductivity of the conductive paste 7 itself is improved, and the conductive paste 5 Connection reliability is improved.
  • the wiring board A is completed by patterning (8a, 8b) the copper foil 8 by, for example, a subtractive method that is a photolithographic technique.
  • the process can be simplified, for example, the number of steps can be reduced. Since the via diameter can be individually set by using the cured resin layer 4 and the uncured resin layer 6 and creating the via holes 4a and 6a individually, the via diameter of the uncured resin layer 6 corresponding to the surface side is reduced. By doing so, the surface wiring pattern 8 can be miniaturized.
  • the surface of the cured conductive paste 5 tends to be resin-rich, and when the uncured conductive paste 7 is brought into contact with the conductive paste 5, there is a possibility that the conduction resistance becomes high at the interface between both conductive pastes.
  • the resin-rich surface layer can be removed to expose the conductive portion on the surface. The conduction resistance at the interface between the conductive pastes 5 and 7 can be lowered. Therefore, the conduction reliability in the via can be improved.
  • FIG. 5 shows a second embodiment of the method of manufacturing the wiring board A. Portions corresponding to those of the first embodiment are denoted by the same reference numerals, and redundant description is omitted.
  • the copper foil 8 is patterned after being attached to the second resin layer 6.
  • the method uses a copper foil with a carrier in which a wiring pattern is formed in advance. The pin lamination method is used for the alignment of the wiring.
  • FIG. 5 shows the state which stuck the carrier 20 to the back surface of the copper foil 8.
  • FIG. 5B The copper foil 8 is patterned as shown in FIG. 5B, and the copper foil 8 patterned as shown in FIG. 5C is pressed onto the uncured second resin layer 6 and cured.
  • the uncured second resin layer 6 is, for example, the resin layer 6 at the stage of (d) in FIG. In this case, since it is not necessary to carry out the pattern formation process of the copper foil 8 on the resin layers 4 and 6, it is not necessary to perform the wet treatment on the resin layers 4 and 6; The influence of moisture absorption etc. can be suppressed.
  • FIG. 6 shows a third embodiment of the method of manufacturing the wiring board A. Portions corresponding to those of the first embodiment are denoted by the same reference numerals, and redundant description is omitted.
  • the process up to the formation of the cured resin layer 4 (FIG. 3B) is the same as in the first embodiment, but the uncured resin layer 6 is not pressure-bonded to the resin layer 4, but is not applied to the copper foil 8. In this method, the cured resin layer 6 is pressure-bonded and the conductive paste 7 is filled, and then the resin layer 4 is pressure-bonded.
  • the copper foil 8 is pressure-bonded to the uncured resin layer 6 with the protective film 13 having the via hole 6a and the through hole 13a.
  • the conductive paste 7 is filled into the via holes 6 a and the through holes 13 a from the protective film 13 by the printing machine 21.
  • the protective film 13 is peeled off, and the conductive paste 7 partially protrudes from the surface of the second resin layer 6.
  • both the resin layer 6 and the conductive paste 7 are in an uncured state.
  • the surface from which the conductive paste 7 protrudes is pressure-bonded to the cured first resin layer 4.
  • the first resin layer 4 is obtained by physically polishing the surface of the conductive paste 5 as shown in FIG.
  • a pin lamination method is used for alignment of the vias at the time of crimping.
  • the copper foil 8 may be patterned.
  • FIG. 7 shows an example in which a multilayer wiring board is configured using the wiring board A manufactured as described above.
  • the circuit component 15 is mounted between one land 8a and the electrode 8b, the third resin layer 16 is formed thereon, and the circuit component 15 is embedded in the resin layer 16.
  • a fourth resin layer 17 is formed thereon, and a wiring 18 is formed thereon.
  • the wiring board A of the first embodiment corresponds to the core substrate
  • the third resin layer 16 corresponds to the first resin layer
  • the fourth resin layer 17 corresponds to the second resin layer.
  • the via hole 16a of the resin layer 16 corresponds, and the conductive paste 19 filled in the via hole 16a and the via land 8a are electrically connected.
  • a via hole 17a of the resin layer 17 corresponds to the conductive paste 19, and the conductive paste 20 filled in the via hole 17a is connected to the via land 18a thereon. In this way, multiple layers can be sequentially formed.
  • FIG. 8 shows another example of the wiring board.
  • the core substrate 1 in the wiring board A of FIG. 1 is omitted, and the mounting land 2a and the via land 2b are directly formed on the lower surface of the first resin layer 4.
  • the mounting land 2a and the via land 2b are formed by, for example, forming the mounting land 2a and the via land 2b on the carrier and forming the resin layer 4 on the mounting land 2a.
  • the carrier may be peeled off from the resin layer 4.
  • a multilayer wiring board can also be configured by stacking such a wiring board B on the uncured resin layer 6 instead of the copper foil in FIG.
  • the second via hole 6a is a tapered hole whose diameter increases upward, but may be a straight hole having the same diameter at the upper end and the same diameter at the lower end. Since the upper end opening diameter D2 of the second via hole 6a is smaller than the upper end opening diameter D1 of the first via hole 4a, the via land 8a formed on the upper surface of the conductive paste 7 can be miniaturized and the conductor pattern 8 can be miniaturized.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

La présente invention concerne un procédé permettant de fabriquer une carte de circuit imprimé. Dans le procédé, un trou d’interconnexion peut être percé sans agrandir le diamètre plus que nécessaire, un câblage de précision est réalisé, et la fiabilité de connexion du câblage et des trous d’interconnexion peut être améliorée. Une première couche de résine (4) dans un état durci est préparée ; elle comprend un premier trou d’interconnexion inférieur (4a) qui comporte un tracé conducteur (2a) en son fond ; le premier trou d’interconnexion est rempli d'une pâte conductrice (5) qui est ensuite amenée à durcir ; à la suite de cela, la surface de la pâte conductrice (5) est polie. Une seconde couche de résine (6) dans un état non durci, qui comprend un second trou d’interconnexion (6a) formé à une position qui correspond au premier trou d’interconnexion, est laminée sur la première couche de résine (4), de telle sorte que les premier et second trous d’interconnexion se continuent. Le second trou (6a) d’interconnexion est rempli d'une pâte conductrice (7) ; ensuite, une feuille de métal (8) est appliquée par pression par-dessus ; et la pâte conductrice (7) et la seconde couche de résine (6) sont amenées à durcir simultanément.
PCT/JP2009/055846 2008-03-26 2009-03-24 Procédé permettant de fabriquer une carte de circuit imprimé, et carte de circuit imprimé WO2009119600A1 (fr)

Priority Applications (1)

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JP2010505686A JP4748281B2 (ja) 2008-03-26 2009-03-24 配線基板の製造方法及び配線基板

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JP2008080227 2008-03-26
JP2008-080227 2008-03-26

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Cited By (3)

* Cited by examiner, † Cited by third party
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JP2012129363A (ja) * 2010-12-15 2012-07-05 Fujitsu Ltd 電子部品内蔵基板及びその製造方法
EP2592915B1 (fr) * 2010-07-06 2022-01-26 Fujikura, Ltd. Procédé de fabrication pour carte de câblage laminée
EP4311382A4 (fr) * 2022-06-08 2024-10-02 Enovate3D Hangzhou Tech Development Co Ltd Carte de circuit imprimé multicouche de haute précision et son procédé de préparation d'impression 3d

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JPH0722100A (ja) * 1993-04-29 1995-01-24 Fujitsu Ltd スルーホールを有する相互接続体とその製造方法
JP2000124581A (ja) * 1998-10-20 2000-04-28 Yotaro Hatamura 配線パターン形成方法及び積層配線基板の製造方法
JP2003124380A (ja) * 2001-10-15 2003-04-25 Matsushita Electric Ind Co Ltd 電子部品内蔵モジュールおよびその製造方法
JP2005064446A (ja) * 2003-07-25 2005-03-10 Dainippon Printing Co Ltd 積層用モジュールの製造方法
JP2006339365A (ja) * 2005-06-01 2006-12-14 Mitsui Mining & Smelting Co Ltd 配線基板およびその製造方法、多層積層配線基板の製造方法並びにビアホールの形成方法

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JP2002111201A (ja) * 2000-10-03 2002-04-12 Ibiden Co Ltd プリント基板の製造方法
JP3807312B2 (ja) * 2002-01-18 2006-08-09 富士通株式会社 プリント基板とその製造方法
KR100704915B1 (ko) * 2005-09-15 2007-04-09 삼성전기주식회사 미세 패턴을 가지는 인쇄회로기판 및 그 제조방법
JP2007281336A (ja) * 2006-04-11 2007-10-25 Fujikura Ltd 両面プリント配線板の製造方法および多層プリント配線板

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Publication number Priority date Publication date Assignee Title
JPH0722100A (ja) * 1993-04-29 1995-01-24 Fujitsu Ltd スルーホールを有する相互接続体とその製造方法
JP2000124581A (ja) * 1998-10-20 2000-04-28 Yotaro Hatamura 配線パターン形成方法及び積層配線基板の製造方法
JP2003124380A (ja) * 2001-10-15 2003-04-25 Matsushita Electric Ind Co Ltd 電子部品内蔵モジュールおよびその製造方法
JP2005064446A (ja) * 2003-07-25 2005-03-10 Dainippon Printing Co Ltd 積層用モジュールの製造方法
JP2006339365A (ja) * 2005-06-01 2006-12-14 Mitsui Mining & Smelting Co Ltd 配線基板およびその製造方法、多層積層配線基板の製造方法並びにビアホールの形成方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2592915B1 (fr) * 2010-07-06 2022-01-26 Fujikura, Ltd. Procédé de fabrication pour carte de câblage laminée
JP2012129363A (ja) * 2010-12-15 2012-07-05 Fujitsu Ltd 電子部品内蔵基板及びその製造方法
EP4311382A4 (fr) * 2022-06-08 2024-10-02 Enovate3D Hangzhou Tech Development Co Ltd Carte de circuit imprimé multicouche de haute précision et son procédé de préparation d'impression 3d

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