WO2009098989A1 - 位相同期装置および位相同期方法 - Google Patents
位相同期装置および位相同期方法 Download PDFInfo
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- WO2009098989A1 WO2009098989A1 PCT/JP2009/051406 JP2009051406W WO2009098989A1 WO 2009098989 A1 WO2009098989 A1 WO 2009098989A1 JP 2009051406 W JP2009051406 W JP 2009051406W WO 2009098989 A1 WO2009098989 A1 WO 2009098989A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0053—Closed loops
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0063—Elements of loops
- H04L2027/0067—Phase error detectors
Definitions
- the present invention relates to a technique for demodulating a phase-modulated received signal.
- Digital modulation includes ASK (Amplitude Shift Keying: amplitude modulation) that controls the amplitude of the carrier, FSK (Frequency Shift Keying: frequency modulation) that controls the frequency of the carrier, PSK (Phase Shift Keying: phase modulation) that controls the phase is roughly divided into three types.
- ASK Amplitude Shift Keying: amplitude modulation
- FSK Frequency Shift Keying: frequency modulation
- PSK Phase Shift Keying: phase modulation
- BPSK Binary Phase Shift Keying
- “1” data is made to correspond to the carrier wave
- “0” data is made to correspond to the waveform obtained by inverting the carrier wave by 180 degrees
- data switching is performed. It is assumed that the phase is switched instantaneously so that no phase stop point is generated. In this case, there is no overlap between “1” and “0” in the analysis. That is, in the above assumption, the probability of erroneously reading a “0” received signal as “1” data is zero in the analysis, except for the influence of noise mixed in the circuit or transmission line. Therefore, a good bit error rate can be realized.
- BPSK Binary Phase Shift Keying
- FIG. 12 is a graph showing the relationship between the value obtained by dividing the allocated energy per bit of the received signal by the noise power and the bit error rate for each digital modulation method. This is shown in Non-Patent Document 1 described later. From the graph shown in the figure, when the SNR (Signal-to-Noise Ratio) of the received signal, that is, the value proportional to the horizontal axis of the figure is the same in each modulation method, the bit error with the best PSK is obtained. It can be seen that the rate is achieved.
- SNR Signal-to-Noise Ratio
- the required SNR can be minimized by selecting PSK as the modulation method.
- PSK the modulation method.
- the allowable amount of noise mixed from the input to the demodulation of the receiving circuit can be greatly estimated. This makes it possible to set a large thermal noise allowed by the low noise amplifier of the radio reception circuit, and as a result, it is possible to reduce the power of the reception circuit.
- PSK requires a reference phase for demodulation. The reason will be explained.
- a signal whose phase advances from 0 degrees to 90 degrees and a signal whose phase advances from 90 degrees to 180 degrees have the same digital data.
- the receiving side acquires digital data by determining whether the modulation on the carrier wave is in the direction in which the phase advances or in the direction in which the phase is delayed. Further, when demodulating data on the receiving side, it is not necessary to match the phase of the carrier with that on the transmitting side.
- a clock required for data reading can be sent through a communication line separate from the data. Therefore, in the case of wired communication, it is relatively easy to grasp the reference phase on the receiving side.
- wired communication since there is only one physical transmission path, it is difficult to simultaneously send a clock and data required for demodulation.
- the UHF band is still mainly ASK and FSK, while the 2.4 GHz ISM band (Industry Science Medical band) is Bluetooth (registered trademark) EDR and ZigBee (registered trademark). ) Etc. adopt PSK. For this reason, it is required to develop a carrier wave recovery technique even in a weak power band such as the ISM band.
- a feedback loop called a Costas loop is used for carrier wave reproduction.
- This feedback loop is performed, for example, in an analog signal region after frequency conversion by a mixer.
- phase synchronization can be realized with high accuracy in the analog signal region, there is a problem that it is difficult to reduce the cost by reducing the circuit area.
- an analog circuit such as an analog mixer for multiplying the reception signal and the demodulation clock and an analog low-pass filter for smoothing by removing high-frequency noise from the signal representing the phase difference is necessary. .
- the above-described technology using the Costas loop has a problem that it is difficult to control characteristics such as a time constant required for synchronization from the outside when performing phase synchronization in the analog signal region. This is because the feedback loop is an analog signal, and the filter is also an analog circuit, so that it is difficult to change the loop transfer function with an external digital control signal.
- an object of the present invention is to provide a technique for saving power and reducing costs when detecting a reference phase used for demodulation of a phase-modulated signal.
- a phase synchronization apparatus includes a sampling unit that samples a phase-modulated continuous-time signal to generate a quantized signal, and a synchronization unit that detects a reference phase synchronized with the phase of the quantized signal in a digital signal domain
- a sampling filter that converts the continuous-time signal into a discrete-time signal and filters the discrete-time signal with a low-pass characteristic; and a high-frequency band for the discrete-time signal that has passed through the sampling filter.
- a 1-bit quantizer that outputs a signal representing a time-dependent change of the discrete-time signal as the quantized signal by filtering of the pass characteristics, and the synchronization unit calculates a phase difference between the inspection signal and the quantized signal.
- the phase difference detector to be obtained and the phase difference detection at a timing that allows for a delay amount corresponding to the phase difference obtained by the phase difference detector. And a delay control circuit for feeding back the test signal to.
- a phase synchronization method includes a sampling step of sampling a phase-modulated continuous-time signal to generate a quantized signal, and a synchronizing step of detecting a reference phase synchronized with the phase of the quantized signal in a digital signal domain
- the sampling step the phase-modulated continuous-time signal is converted into a discrete-time signal, the discrete-time signal is subjected to low-pass filtering, and the filtered high-pass signal is applied to the discrete-time signal.
- a new test signal is output at the timing, and the phase difference between the new test signal and the current quantized signal
- 1 is a block diagram of a phase synchronization apparatus according to a first embodiment of the present invention. It is a block diagram of the sampling part by 1st embodiment of this invention. It is a flowchart of the operation
- phase synchronizer by 2nd embodiment of this invention It is a block diagram of the phase synchronizer by 2nd embodiment of this invention. It is a block diagram relevant to the sampling filter by 2nd embodiment of this invention. It is explanatory drawing regarding the operation timing of the sampling filter by 2nd embodiment of this invention. It is explanatory drawing regarding the bit error rate according to digital modulation of a nonpatent literature 1.
- FIG. 1 is a block diagram showing a configuration of a phase synchronization apparatus 100 according to the first embodiment of the present invention.
- the phase synchronizer 100 is provided in a stage subsequent to the front end (not shown) of the communication receiver.
- the front-end unit receives the phase-modulated signal on the transmission side, the front-end unit performs amplification, frequency conversion, filter processing, and the like so as to make it suitable for demodulation, and inputs the received signal 101 to the phase synchronization apparatus 100 .
- the front-end unit includes an antenna, a low noise amplifier, a mixer, a communication band limiting filter, an interference wave removing filter, and the like for wireless communication.
- it is a reception input buffer designed in accordance with the transmission side output impedance and the transmission line characteristic impedance.
- the phase synchronization apparatus 100 includes a sampling unit 100A, a synchronization unit 100B, and a clock generator 104.
- the sampling unit 100A samples the received signal 101 that has passed through the front end unit, and generates a quantized signal 108.
- Synchronizer 100B detects a reference phase synchronized with the phase of quantized signal 108 in the digital signal domain.
- the clock generator 104 supplies a common clock signal to the sampling unit 100A and the synchronization unit 100B.
- the sampling unit 100A includes a sampling filter 102 that converts the received signal 101, which is a continuous time signal, into a discrete time signal, and a 1-bit quantizer 107 that generates a quantized signal 108 that represents a change over time of the discrete time signal.
- FIG. 2 shows the detailed configuration of the sampling unit 100A.
- the received signal 101 is input to the sampling filter 102, it is input to the two systems of sample and hold circuits 103a and 103b.
- the sample and hold circuits 103a and 103b have a filter characteristic defined by a sampling clock having a frequency fs supplied from the clock generator 104.
- the sampling switches 105a and 105b repeat the on / off operation according to the clock signals a and b supplied thereto.
- Sampling capacitors 106a and 106b store signals input when switches 105a and 105b are turned on.
- the switches 105c1 and 105c2 are output switches that operate based on the clock signal c.
- the signals accumulated in the sampling capacitors 106a and 106b are output to the 1-bit quantizer 107 when the switches 105c1 and 105c2 are turned on.
- the 1-bit quantizer 107 generates a quantized signal 108 representing a temporal change of the discrete time signal from the sampling filter 102 in accordance with the clock signal from the clock generator (104).
- the generated quantized signal 108 is output to the synchronization unit 100B.
- the synchronization unit 100B includes a phase difference detector 110, a low-pass filter 112, and a delay control circuit 114.
- the phase difference detector 110 outputs a phase difference signal 111 representing the phase difference between the quantized signal 108 from the 1-bit quantizer 107 and a reproduction demodulation clock 109 (to be described later) fed back from the delay control circuit 114.
- the low-pass filter 112 removes a high frequency component that becomes noise of the phase difference signal 111 and outputs it to the delay control circuit 114.
- the delay control circuit 114 generates a phase difference signal 111 from which noise has been removed, that is, a signal representing a temporal delay amount corresponding to the phase difference represented by the filter output signal 113. Then, the reproduction demodulation clock 109 is fed back to the delay control circuit 114 at the timing when the delay amount is expected. This reproduction demodulation clock 109 corresponds to the inspection signal according to the present invention.
- the operation of the phase synchronization apparatus 100 configured as described above will be described with reference to the flowchart shown in FIG.
- the received signal 101 having the frequency f1 input to the sampling filter 102 is sampled according to the clocks a and b having the frequency fs0 by the sample and hold circuits 103a and 103b, and the sample value is held. Thereby, the received signal 101 is converted from a continuous time signal to a discrete time signal (step S1).
- FIG. 4 shows an example of sampling by the sampling filter 102.
- the received signal 101 is converted into discrete signals A1 to A4 and A9 to A12 according to the clock a, and converted into discrete signals B5 to B8 and B13 to B16 according to the clock b.
- the values A1 to A4 are held as analog addition values of A1 + A2 + A3 + A4 in the sampling capacitor 106a, and the values of A9 to A12 are also held as addition values of A9 + A10 + A11 + A12.
- B5 to B8 and B13 to B16 are respectively held as added values by the sampling capacitor 106b.
- the sampling filter 102 calculates a moving average for four units of sampling points held in the sampling capacitors 106a and 106b. By this calculation process, a filter showing a low-pass characteristic is formed (FIG. 3: step S2).
- the transfer function of the formed filter is expressed by the following ⁇ Equation 1>, for example.
- the signal subjected to the low-pass filtering according to the above ⁇ Formula 1> is output to the 1-bit quantizer 107.
- the 1-bit quantizer 107 compares two average values from the sampling filter 102, that is, obtains a subtraction value of two sampling points. By this subtraction process, a filter showing high-pass characteristics is formed (step S3).
- the transfer function of this filter is expressed by the following ⁇ Expression 2>, for example.
- the filter formed by the sampling filter 102 and the 1-bit quantizer 107 is a moving average low-pass filter expressed by ⁇ Equation 1> and a subtraction high expressed by ⁇ Equation 2>.
- the bandpass characteristics as shown in FIG. 5 eliminate noise such as noises included as harmonics having frequencies of 2 ⁇ f1 and 3 ⁇ f1 and thermal noise added when passing through the front end of the previous stage. .
- the characteristics of the band-pass filter may be changed according to the degree of noise that can be mixed into the received signal (101).
- the filter characteristics shown in the above ⁇ Expression 1> and ⁇ Expression 2> are so-called finite impulse response filters that do not have a process of returning a part of the output to the input.
- this finite impulse response filter In order to obtain a steep cut-off characteristic by this finite impulse response filter, it is necessary to configure a relatively large number of operation stages. Therefore, when it is estimated that a large amount of noise is mixed, an infinite impulse response filter that returns a part of the output to the input may be used. Thereby, the number of calculation stages can be suppressed.
- the frequency f1 of the received signal (101) is arranged at the position indicated by the dotted arrow, which is the maximum gain point in the frequency characteristics of FIG. Therefore, it is desirable to set the filter characteristics.
- the quantized signal 108 output from the 1-bit quantizer 107 indicates a time change rate at an interval 1 / ((fs0) / 4) when the received signal 101 is regarded as a sine wave.
- the latter is larger than the former (FIG. 3: Step S4: Yes)
- the 1-bit quantizer 107 outputs a signal “1”. This signal indicates that the change in the time axis of the received signal has a positive slope (step S5).
- step S4 the 1-bit quantizer 107 outputs a signal “0” indicating that the change in the received signal on the time axis has a negative slope (step S4).
- step S6 the 1-bit quantizer 107 of the present embodiment simply expresses the temporal change of the waveform of the received signal with the binary values of “0” and “1”.
- the linear distortion of the received signal 101 is removed to some extent by the filter formed by the sampling unit 100A. Therefore, it is sufficient for the synchronization unit 100B in the subsequent stage to obtain binary level information as information representing the change over time of the received signal 101. Further, by using the 1-bit quantizer 107, the circuit configuration can be simplified, and as a result, the circuit scale can be reduced.
- the synchronization unit 100B moves to an operation of matching the phase of the quantized signal 108 with the phase of the inspection signal (reproduction demodulated clock 109) for phase synchronization.
- the phase difference detector 110 detects a temporal difference between the rising edge of the quantized signal 108 and the rising edge of the reproduction demodulation clock 109 as a check signal, and outputs it as a phase difference signal 111 (see FIG. 3: Step S7). Therefore, in the present embodiment, NOT gates 110a and 110c and a NAND gate 110b arranged as shown in FIG. 6 are used.
- the phase difference signal 111 originally indicates a time difference between the rising edge of the reproduction demodulation clock 109 and the quantized signal 108, but actually includes high frequency noise mixed up to the phase difference detector 110. Therefore, the low-pass filter 112 of the digital filter removes this high frequency noise (step S8). This makes it easier to extract time difference information from the phase difference signal 111.
- the low-pass filter 112 includes, for example, delay flip-flop circuits (DFF) 112a and 112b that operate based on the filter clock 104A from the clock generator 104, and an XOR gate 112c, as shown in FIG. be able to.
- DFF delay flip-flop circuits
- FIG. 7 shows waveforms of the phase difference signal 111 corresponding to the phase difference between the quantized signal 108 and the reproduction demodulation clock 109, and the filter output signal 113 based on the filter clock 104A.
- the low-pass filter 112 outputs a moving average of the phase difference signal 111 at three consecutive timings based on the filter clock 104A as the filter output signal 113.
- the characteristics of the low-pass filter 112 are appropriately set according to the noise that can be included in the phase difference signal 111. Since the low-pass filter 112 is a digital filter composed of only logic gates as described above (FIG. 6), the control of characteristics is relatively easy.
- the phase difference signal 111 is input to the delay control circuit 114 as a filter output signal 113 when high-frequency noise is removed by the low-pass filter 112.
- the delay control circuit 114 determines whether or not the input filter output signal 113 indicates the same phase of the quantized signal 108 and the reproduction demodulation clock 109. It should be noted that the filter output signal 113 does not show the same phase while the reproduction demodulation clock 109 is not yet synchronized with the quantized signal 108 as at the start of the synchronization process (FIG. 3: Step S9: No).
- the delay control circuit 114 generates a control code corresponding to the current phase difference in order to guide the filter output signal 113 to indicate the same phase (step S10), and at the delay timing based on the control code, The reproduction demodulation clock 109 is fed back to the phase difference detector 110 (step S11).
- the digital phase adjustment circuit 114c is a digital circuit that discretely controls the rising edge position of the reproduction demodulation clock 109. As shown in FIG. 8, the digital phase adjustment circuit 114c determines the delay amount ([Deg.]) To be added to the output timing of the reproduction demodulation clock 109 based on the control code 114b (binary number) from the decoder 114a. To figure out.
- the decoder 114a generates a control code 114b corresponding to the phase difference indicated by the filter output signal 113 from the low-pass filter 112.
- the pulse width of the filter output signal 113 corresponds to the time difference between the rising edge of the quantized signal 108 and the rising edge of the regenerative demodulation clock 109 as described above.
- the filter output signal 113 shows a certain phase difference until phase synchronization is established.
- the above-described operation of the delay control circuit 114 is an operation of feeding back the reproduction demodulation clock 109 to the phase difference detector 110 at a timing that allows for a delay amount corresponding to the current phase difference. By repeating this operation, the phase difference indicated by the filter output signal 113 is converged to zero.
- step S11 When the phase difference indicated by the filter output signal 113 converges to zero (step S11: Yes), the delay control circuit 114 recognizes that the phase synchronization between the reception signal 101 and the reproduction demodulation clock 109 is established (step S12). .
- the phase of the reproduction demodulation clock 109 at this time corresponds to the reference phase to be detected by the synchronization unit 100B. Thereafter, the received signal is demodulated by the 1-bit quantizer 107 using the detected reference phase, so that the data can be properly reproduced.
- phase of the carrier wave of the received signal generally fluctuates constantly due to the mixing of various noise components.
- a phase shift that fluctuates in a short period at a high frequency has a relatively short convergence time of the feedback loop.
- the convergence time tends to be prolonged.
- the phase shift that fluctuates in a long cycle causes deterioration of the bit error rate particularly in communication with a large amount of data. Therefore, it is desirable to determine the phase shift period and the loop convergence time in accordance with the amount of data handled by communication.
- an A / D converter having a high resolution and a high sampling rate that is required in the conventional technique for detecting the reference phase in the digital signal domain is unnecessary. Therefore, the circuit scale can be reduced and the power consumption can be reduced.
- filtering for noise removal is also performed in the sampling unit 100A in the previous stage that operates with a clock common to the synchronization unit 100B (see FIG. 5). That is, the quantized signal 108 input to the synchronization unit 100B has already been subjected to some noise removal by the preceding sampling unit 100A that operates with the same clock as the synchronization unit 100B. Therefore, it is possible to prevent the convergence time of subsequent loop processing in the synchronization unit 100B from being prolonged.
- sampling unit 100A can be used not only for the phase synchronization processing shown in the above embodiment but also for subsequent data demodulation processing. This contributes to downsizing of the entire receiving circuit.
- FIG. 9 shows the configuration of the second embodiment of the present invention.
- the same components as those in the first embodiment described above are denoted by the same reference numerals.
- the phase synchronization apparatus 200 of the present embodiment is provided with a multiphase generator 215 and a phase compensator 216 in addition to the sampling unit 200A, the synchronization unit 100B, and the clock generator 104.
- the multiphase generator 215 converts the clock signal supplied from the clock generator 104 toward the sampling switch of the sampling filter 202 into a multiphase clock signal.
- the phase compensator 216 compensates for the correlation skew of the multiphase clock signal input to the sampling filter 202, that is, compensates for phase variations between the multiphase clock signals.
- FIG. 10 partially shows the configuration of the sampling filter 202 of the present embodiment.
- the configuration shown is related to the clock a which is one of the clock signals output from the clock generator (104).
- the sampling filter 202 includes a sample and hold circuit 203a to which clocks a1 to a4 obtained by multi-phase clock a are supplied. Although omitted in FIG. 10, the other clock signals are similarly provided with sample and hold circuits corresponding to the number of multiphases of the clock.
- the basic configuration of the sample and hold circuit 203a conforms to the sample and hold circuit 103a (FIG. 2) in the above-described embodiment. That is, the sample and hold circuit 203a includes sampling switches 105a1 to 105a4 that are turned on and off by clocks a1 to a4, and accumulates the discrete time signal of the received signal 101 in each sampling capacitor when they are turned on.
- the multi-phase generator 215 converts the clock a input from the clock generator 104 into four phases to generate four clocks a1 to a4 and outputs them to the phase compensator 216.
- the phase compensator 216 adjusts the correlation skew of the clocks a1 to a4, and sequentially inputs them to the sample and hold circuit 203a.
- the clock a1 is input to the switch 105a1 of the sample-and-hold circuit 203a, the clock a2 to the switch 105a2, the clock a3 to the switch 105a3, and the clock a4 to the switch 105a4. , Respectively.
- FIG. 11 shows the timing relationship between the received signal 101 and the clocks a1 to a4 and the clock c.
- continuous sample values such as A1 to A4 are obtained from the single-phase clock a (FIG. 4).
- continuous sample values are acquired based on a plurality of clocks using multiphase clocks a1 to a4. For example, in the case of sample values A1 to A4, A1 is obtained from the clock a1, A2 is obtained from the clock a2, A3 is obtained from the clock a3, and A4 is obtained from the clock a4.
- the sampling filter 202 obtains an added value such as A1 + A2 + A3 + A4 at the timing of the clock c for the acquired sample value, and outputs the average value to the 1-bit quantizer 107.
- movement it is the same as that of the above-mentioned embodiment.
- the sampling frequency can be easily increased. This is useful, for example, in an environment where it is difficult to make the sampling frequency sufficiently high.
- the present invention is not limited to the above embodiments.
- the implementation of the present invention may be appropriately changed from the above embodiments within the scope of the claims.
- the low-pass filter 112 is disposed after the phase difference detector 110 in order to remove the high frequency noise of the phase difference signal 111.
- the noise is obtained by filtering by the sampling unit 100A (FIG. 5). Is sufficiently removed, the low-pass filter 112 may be omitted from the synchronization unit 100B. Since the filtering process is omitted, the processing time of the synchronization unit 100B can be shortened.
- a single clock generator (104) is used to supply a common clock signal to each circuit of the phase synchronization apparatus.
- a plurality of clock generators are used.
- the structure to be used may be used. In this case, the clock signals from the generators are used after being synchronized.
- phase synchronizer 101 Received signal 102 Sampling filter 103a, 103b Sample and hold circuit 104 clock generator 105a, 105b Sampling switch 105c1,105c2 Output switch 106a, 106b Sampling capacity 107 1-bit quantizer 108 Quantized signal 109 Reproduction demodulation clock 110 Phase detector 111 Phase difference signal 112 Low-pass filter 113 Filter output signal 114 Delay control circuit
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Abstract
Description
図1は、本発明の第1の実施形態による位相同期装置100の構成を示すブロック図である。位相同期装置100は、通信の受信装置のフロントエンド部(図示略)の後段に設けられる。フロントエンド部は、送信側で位相変調された信号を受信すると、それを復調に好適な状態にすべく、増幅、周波数変換およびフィルタ処理等を施し、受信信号101として位相同期装置100へ入力する。
図3に示すフローチャートに沿って、上記構成による位相同期装置100の動作について説明する。サンプリングフィルタ102に入力された周波数f1の受信信号101は、各サンプル・ホールド回路103a及び103bにより、周波数fs0のクロックa及びbに従ってサンプリングされ、そのサンプル値を保持される。これにより、受信信号101は、連続時間信号から離散時間信号へ変換される(ステップS1)。
ただし、z=exp(j×2π×fs0)
例えばA1+A2+A3+A4の平均値が出力され、サンプリング容量106bから例えばB5+B6+B7+B8の平均値が出力される。
ただし、z=exp[j×2π×(fs0/4)]
図9に、本発明の第二の実施形態の構成を示す。図示の構成において、前述の第一の実施形態の構成要素(図1)と同様なものには、同じ符号が付されている。
上記構成による位相同期装置200の動作について説明する。なお、本実施形態における同期部100Bの動作は、前述の第一の実施形態のものと同様であり、説明を省略する。以下では、サンプリング部200Aの動作に関し、主に、第一の実施形態におけるサンプリング部100Aのものと異なる点について説明する。
101 受信信号
102 サンプリングフィルタ
103a,103b サンプル・ホールド回路
104 クロック生成器
105a,105b サンプリング用スイッチ
105c1,105c2 出力用スイッチ
106a,106b サンプリング容量
107 1ビット量子化器
108 量子化信号
109 再生復調クロック
110 位相差検出器
111 位相差信号
112 低域通過フィルタ
113 フィルタ出力信号
114 遅延制御回路
Claims (10)
- 位相変調された連続時間信号をサンプリングして量子化信号を生成するサンプリング部と、前記量子化信号の位相に同期する基準位相をディジタル信号領域で検出する同期部とを備え、
前記サンプリング部は、前記連続時間信号を離散時間信号へ変換して該離散時間信号に対し低域通過特性のフィルタリングを施すサンプリングフィルタと、前記サンプリングフィルタを経た離散時間信号に対する高域通過特性のフィルタリングにより当該離散時間信号の経時変化を表す信号を前記量子化信号として出力する1ビット量子化器とを有し、
前記同期部は、検査信号と前記量子化信号との位相差を求める位相差検出器と、前記位相差検出器が求めた位相差に相当する遅延量を見込んだタイミングで前記位相差検出器に対し検査信号をフィードバックする遅延制御回路とを有することを特徴とする位相同期装置。 - さらに、前記サンプリング部および前記同期部に対し共通のクロック信号を供給するクロック生成器を備え、
前記サンプリング部および前記同期部は、前記クロック信号に基づき動作することを特徴とする請求項1記載の位相同期装置。 - 前記同期部は、前記位相差検出器が求めた位相差を表す信号から高周波ノイズを除去し且つ該高周波ノイズを除去した信号を前記遅延制御回路へ供給する低域通過フィルタを有することを特徴とする請求項2記載の位相同期装置。
- 前記1ビット量子化器は、前記経時変化が時間軸上の正の傾き又は負の傾きであることを表す2値信号を前記量子化信号として出力することを特徴とする請求項1乃至3のいずれか1項に記載の位相同期装置。
- さらに、前記クロック生成器から前記サンプリングフィルタに対するクロック信号を多相クロック信号に変換する多相生成器と、前記多相クロック信号における位相のばらつきを補償して該多相クロック信号を前記サンプリングフィルタへ出力する位相補償器とを備えることを特徴とする請求項2乃至4のいずれか1項に記載の位相同期装置。
- 位相変調された連続時間信号をサンプリングして量子化信号を生成するサンプリングステップと、前記量子化信号の位相に同期する基準位相をディジタル信号領域で検出する同期ステップとを含み、
前記サンプリングステップにおいて、位相変調された連続時間信号を離散時間信号へ変換して該離散時間信号に対し低域通過特性のフィルタリングを施し、前記フィルタリングを経た離散時間信号に対する高域通過特性のフィルタリングにより当該離散時間信号の経時変化を表す量子化信号を生成し、
前記同期ステップにおいて、検査信号と前記量子化信号との位相差を求め、前記位相差に相当する遅延量を見込んだタイミングで新たな検査信号を出力し、前記新たな検査信号と現時点の量子化信号との位相差が同位相を示すとき当該新たな検査信号の位相を基準位相として検出することを特徴とする位相同期方法。 - 前記各ステップを共通のクロック信号に基づき実行することを特徴とする請求項6記載の位相同期方法。
- 前記同期ステップにおいて、前記遅延量に用いる位相差を表す信号から高周波ノイズを除去することを特徴とする請求項7記載の位相同期方法。
- 前記サンプリングステップにおいて、前記経時変化が時間軸上の正の傾き又は負の傾きであることを表す2値信号を前記量子化信号として出力することを特徴とする請求項6乃至8のいずれか1項に記載の位相同期方法。
- さらに、前記サンプリングステップにおける離散時間信号への変換のためのクロック信号を多相クロック信号に変換し且つ該多相クロック信号における位相のばらつきを補償するステップを含むことを特徴とする請求項7乃至9のいずれか1項に記載の位相同期方法。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210126766A1 (en) * | 2018-07-10 | 2021-04-29 | Socionext Inc. | Phase synchronization circuit, transmission and reception circuit, and integrated circuit |
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Publication number | Priority date | Publication date | Assignee | Title |
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EP2299588B1 (en) * | 2009-09-11 | 2012-12-19 | Stichting IMEC Nederland | Receiver with improved flicker noise performance |
WO2016061781A1 (en) * | 2014-10-23 | 2016-04-28 | Lattice Semiconductor Corporation | Phase locked loop with sub-harmonic locking prevention functionality |
WO2019124721A1 (ko) * | 2017-12-18 | 2019-06-27 | 주식회사 포인투테크놀로지 | 위상 동기화 장치 |
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US10746814B2 (en) * | 2018-06-21 | 2020-08-18 | Allegro Microsystems, Llc | Diagnostic methods and apparatus for magnetic field sensors |
US11561257B2 (en) | 2020-12-22 | 2023-01-24 | Allegro Microsystems, Llc | Signal path monitor |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05110610A (ja) * | 1991-10-16 | 1993-04-30 | Nec Corp | ボータイミング抽出回路 |
JPH0630063A (ja) * | 1992-07-08 | 1994-02-04 | Sanyo Electric Co Ltd | デジタル復調器 |
JPH09130443A (ja) * | 1995-10-31 | 1997-05-16 | Toshiba Corp | ディジタル復調装置 |
JPH09224063A (ja) * | 1996-02-16 | 1997-08-26 | Nippon Telegr & Teleph Corp <Ntt> | クロック再生回路 |
JP2002094585A (ja) | 2000-09-12 | 2002-03-29 | Sony Corp | 受信装置、フィルタ回路制御装置およびそれらの方法 |
JP2002124999A (ja) | 2000-10-16 | 2002-04-26 | Ee O R:Kk | Psk同調確認方法及びpsk同調確認装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4233565A (en) * | 1979-06-29 | 1980-11-11 | Motorola, Inc. | Method and apparatus for a PSK signal detector |
JP2841935B2 (ja) | 1990-07-20 | 1998-12-24 | 日本電気株式会社 | 位相復調器 |
EP0467712B1 (en) * | 1990-07-20 | 1998-04-29 | Nec Corporation | Phase demodulator for psk-modulated signals |
JP2795585B2 (ja) | 1992-08-19 | 1998-09-10 | ユニデン株式会社 | 選択呼出し受信機のフィルタ回路 |
JP3628463B2 (ja) | 1996-12-26 | 2005-03-09 | 松下電器産業株式会社 | デルタシグマ型a/d変換器 |
JP2006041580A (ja) | 2004-07-22 | 2006-02-09 | Renesas Technology Corp | 通信用半導体集積回路 |
JP4716032B2 (ja) * | 2004-10-27 | 2011-07-06 | 日本電気株式会社 | ディジタル無線受信装置 |
JP2007174620A (ja) * | 2005-11-25 | 2007-07-05 | Seiko Epson Corp | Psk受信機、psk復調回路、通信装置、および、psk受信方法 |
JP5046622B2 (ja) | 2005-12-13 | 2012-10-10 | パナソニック株式会社 | サンプリングフィルタ装置 |
-
2009
- 2009-01-29 WO PCT/JP2009/051406 patent/WO2009098989A1/ja active Application Filing
- 2009-01-29 US US12/865,192 patent/US8125258B2/en active Active
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05110610A (ja) * | 1991-10-16 | 1993-04-30 | Nec Corp | ボータイミング抽出回路 |
JPH0630063A (ja) * | 1992-07-08 | 1994-02-04 | Sanyo Electric Co Ltd | デジタル復調器 |
JPH09130443A (ja) * | 1995-10-31 | 1997-05-16 | Toshiba Corp | ディジタル復調装置 |
JPH09224063A (ja) * | 1996-02-16 | 1997-08-26 | Nippon Telegr & Teleph Corp <Ntt> | クロック再生回路 |
JP2002094585A (ja) | 2000-09-12 | 2002-03-29 | Sony Corp | 受信装置、フィルタ回路制御装置およびそれらの方法 |
JP2002124999A (ja) | 2000-10-16 | 2002-04-26 | Ee O R:Kk | Psk同調確認方法及びpsk同調確認装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2249534A4 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210126766A1 (en) * | 2018-07-10 | 2021-04-29 | Socionext Inc. | Phase synchronization circuit, transmission and reception circuit, and integrated circuit |
US11777701B2 (en) * | 2018-07-10 | 2023-10-03 | Socionext Inc. | Phase synchronization circuit, transmission and reception circuit, and integrated circuit |
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