WO2009096203A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2009096203A1 WO2009096203A1 PCT/JP2009/050047 JP2009050047W WO2009096203A1 WO 2009096203 A1 WO2009096203 A1 WO 2009096203A1 JP 2009050047 W JP2009050047 W JP 2009050047W WO 2009096203 A1 WO2009096203 A1 WO 2009096203A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wiring
- impedance
- semiconductor device
- power supply
- conductive plate
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates to a technology that makes it possible to reduce noise current in a semiconductor device.
- a major cause of EMI generated by electronic devices and the like is a high-frequency current generated by a high-speed switching operation of an internal circuit such as an LSI.
- the high-frequency current generated inside the LSI propagates to the circuit board and causes radiation from the circuit board. In addition, it may propagate to wiring or other boards through a connector connected to the circuit board, and may cause radiation.
- a technique for preventing the propagation of high-frequency current from the LSI to the circuit board has been proposed.
- a circuit board on which an LSI is mounted includes a first capacitor that electrically connects a power supply terminal and a via hole, a first power supply wiring, a second power supply wiring, and a second capacitor.
- the characteristic impedance of the power supply wiring in the predetermined frequency range is set to be three times or more the impedance magnitude of the capacitor, and the length of the power supply wiring is 20 mm or more multiplied by the wavelength reduction rate of the circuit board, and
- the effect of the low-frequency pass filter is enhanced by a configuration in which the wavelength is reduced to a value equal to or less than a quarter wavelength of the upper limit frequency of the predetermined frequency.
- Patent Document 2 discloses a wiring board in which a predetermined wiring is disposed on a wiring board and an electromagnetic wave shielding film (metal foil) is disposed at a position close to the wiring, and an integrated circuit of a semiconductor chip.
- An insulating film is disposed on the formed surface, a lead is disposed on the electromagnetic wave shielding film via the insulating film, the lead and an external terminal of the semiconductor chip are electrically connected, and a sealing material
- the structure of a semiconductor device sealed with is described. With this configuration, it is possible to reduce wiring inductance and inductive crosstalk due to wiring or leads in the semiconductor package.
- Non-Patent Document 1 As a method for suppressing a high-frequency current (common mode current) flowing in the same phase through a power supply wiring / ground (GND) wiring that is a main factor of radiation, a parasitic due to a wiring pattern of a printed circuit board A method to properly balance inductance and capacitance is proposed. This outline is shown in FIG.
- FIG. 12 is a schematic diagram showing a state of common mode current generation in an electronic device.
- the electronic device includes a circuit board 201 on which the semiconductor device 10 is mounted, a power cable 202, a power supply 203, and a reference GND 101.
- the lower part of FIG. 12 is an equivalent circuit of this component circuit.
- the circuit board 201 is represented by an equivalent circuit 501
- the power cable 202 is represented by an equivalent circuit 502
- the power source 203 is represented by an equivalent circuit 503.
- the equivalent circuit 501 the equivalent circuit 510 of the semiconductor device 10 having the noise source 500, the parasitic wirings 531 and 532, and the parasitic inductance that the power supply wiring pattern 521 and the GND wiring pattern 522 of the circuit board 201 have with respect to the reference GND 101, respectively.
- the equivalent circuit 502 of the power supply cable 202 and the equivalent circuit 503 of the power supply 203 are similarly represented by the parasitic capacitance with respect to the reference GND 101, the parasitic inductance, and the parasitic capacitance between the power supply wiring / GND wiring.
- the equivalent circuit of this component circuit there are two noise current loops.
- the noise current leaked from the semiconductor device 10 passes through the parasitic capacitance 531 of the power supply wiring pattern 521 of the circuit board 201, and the power supply side noise current loop 402 that flows to the reference GND 101 and the parasitic capacitance 532 of the GND wiring pattern 522 of the circuit board 201.
- a GND-side noise current loop 403 that flows to the reference GND 101 is formed.
- a common mode current which is a high-frequency current flowing in the same phase in the power supply wiring / GND wiring, is generated by the difference between the two noise currents.
- the difference between the two noise currents is due to the difference in impedance between the two noise current loops.
- the parasitic capacitance of the noise current loop and the parasitic inductance of the board wiring pattern are controlled. It is important to match the impedances of both noise current loops. This is called impedance balancing. Conversely, a state where there is a difference in impedance is expressed as an impedance being unbalanced.
- the common mode current is suppressed by changing the wiring pattern of the circuit board and controlling the parasitic capacitance to balance the impedance.
- Patent Document 3 discloses that the ground layer is provided with a hollow portion so as to be positioned below the communication line wired on the printed wiring board, thereby making the proximity to the hollow portion.
- a technique has been proposed in which two magnetic fluxes flowing in opposite directions are generated by two loop currents flowing in the opposite direction, and the two magnetic fluxes cancel each other, thereby attenuating the level of the common mode current.
- JP 2001-119110 A Japanese Patent Laid-Open No. 11-220056 JP 2000-307205 A IEICE Transactions Vol.J89-C No.11 pp.854-865
- Patent Documents 1 and 2 propose a structure that prevents high-frequency current propagation from a semiconductor device to a circuit board.
- propagation of high-frequency current to two loops can be suppressed.
- the high-frequency current (common mode current) flowing in the same phase through the power supply wiring / ground (GND) wiring which is the main factor of radiation, cannot be effectively suppressed.
- Non-Patent Document 1 discloses a method of suppressing the common mode current by suppressing the impedance imbalance of the circuit board.
- balancing must be performed in the entire system including the semiconductor device and the circuit board. For this reason, it is necessary to adjust the impedance for each circuit board layout, which may be costly and time-consuming to design.
- the technique disclosed in Patent Document 3 suppresses a common mode current in a circuit board by the structure of the circuit board.
- an object of the present invention is to provide a semiconductor device capable of matching the impedance of the power supply wiring / GND wiring inside the semiconductor device, suppressing the common mode current, and reducing the noise current without depending on the mounting layout of the circuit board. To provide an apparatus.
- a semiconductor device includes a package substrate, a semiconductor chip mounted on the package substrate, a first wiring for supplying a first power supply potential to the semiconductor chip, and the semiconductor chip. And a second wiring for supplying a second power supply potential lower than the first power supply potential, and a third wiring different from the first power supply potential and the second power supply potential.
- the impedance imbalance of the semiconductor device is balanced only inside the semiconductor device, and the EMI of the semiconductor device is suppressed regardless of the wiring state of the external circuit board. Can do.
- 1 and 2 are diagrams illustrating a configuration example of the semiconductor device of the present embodiment.
- the power supply terminal of the semiconductor chip 12 is connected to the power supply wiring 15 formed in the wiring layer via the wire 13.
- the power supply wiring 15 is connected to the power supply layer 22 through the impedance adjustment element 31.
- the GND terminal of the semiconductor chip 12 is connected to the GND wiring 16 formed in the wiring layer via the wire 14.
- the GND wiring 16 is connected to the GND layer 23 through the impedance adjustment element 32.
- a dielectric 21 is filled between the layers of the package substrate.
- the conductive plate 11 is disposed in the lowermost layer of the semiconductor device 10.
- the conductive plate 11 has a potential different from that of the power supply wiring 15 / GND wiring 16 inside the semiconductor device 10 with respect to the reference GND 101, and generates a parasitic capacitance for the power supply wiring 15 / GND wiring 16.
- the conductive plate 11 was provided on the contact surface side of the semiconductor device 10 with the circuit board immediately below the power supply wiring 15 / GND wiring 16.
- the conductive plate 11 is arranged in this way, but the size of the conductive plate 11 may be arbitrary as long as parasitic capacitance is generated for the power supply wiring 15 / GND wiring 16.
- the conductive plate 11 is preferably provided on the contact surface side of the semiconductor device 10 with the circuit board. However, the conductive plate 11 may be arbitrarily positioned as long as it generates parasitic capacitance with respect to the power supply wiring 15 / GND wiring 16 inside the semiconductor device 10. May be arranged.
- FIG. 3 is a diagram showing an approximate equivalent circuit of the semiconductor device 10 of the present embodiment.
- the equivalent circuit includes a semiconductor device 10, a circuit board 61 on which the semiconductor device 10 is mounted, and a power cable 62.
- the semiconductor chip 12 shown in FIGS. 1 and 2 operates, a through current 100 flows in the semiconductor device 10.
- Parasitic inductances 43 and 44 are generated in the power supply wiring 15 and the GND wiring 16 inside the semiconductor device 10, respectively, and parasitic capacitances 41 and 42 are generated between the semiconductor device 10 and the conductive plate 11, respectively.
- the parasitic capacitance 45 is a parasitic capacitance between the power supply wiring 15 / GND wiring 16, and the parasitic capacitance 46 is a parasitic capacitance between the conductive plate 11 and the reference GND 101.
- a parasitic capacitance 45 exists between VG in FIG. 3, a bypass capacitor may be mounted between VG.
- the impedance between VG is set to a value sufficiently smaller than the wiring impedance of the impedance adjusting elements 31 and 32 and the parasitic inductances 43 and 44, and the same potential in terms of high frequency.
- FIG. 4 is a diagram showing an equivalent circuit obtained by further approximating the equivalent circuit shown in FIG.
- a connection point 102 is a point where the semiconductor device 10 and the circuit board 61 are connected, and further, a common mode impedance 52, a common mode current 53, and a common mode voltage 54 that are impedances of the circuit board 61 and the power cable 62. It is shown. A condition for suppressing the common mode current 53 in this circuit is derived.
- the impedances of the parasitic capacitances 41 and 42 between the power supply wiring 15 / GND wiring 16 and the conductive plate 11 in the circuit of FIG. 4 are Z Cv and Z Cg , respectively.
- combined impedances 47 and 48 which are impedance values obtained by combining the parasitic inductances 43 and 44 of the power supply wiring 15 / GND wiring 16 and the impedance adjustment elements 31 and 32, are defined as Z Lv and Z Lg .
- the common mode impedance 52 which is the impedance of the circuit board and the power cable is Z C
- the common mode voltage 54 is V C
- the voltage of the noise source 51 is V d .
- the common mode voltage 54 can be expressed by the following equation.
- the common mode current 53 is proportional to the common mode voltage 54. Therefore, the condition for suppressing the common mode current 53 is obtained as the following equation.
- the common mode current 53 can be suppressed by adjusting the impedance adjusting elements 31 and 32 so as to satisfy this condition.
- the generation state of the common mode current when the semiconductor device 10 having the configuration in which the conductive plate 11 is not mounted is mounted on the circuit board.
- the generation state of the common mode current when the semiconductor device 10 having the configuration in which the conductive plate 11 is mounted is mounted on a circuit board is shown.
- FIG. 13 is a diagram showing the configuration of a measurement system that measures the occurrence of common mode current.
- the measurement system includes a circuit board 201 on which the semiconductor device 10 is mounted, a power cable 202, a pseudo load circuit 204, and a power source 203.
- the power cable 202 has a length of 1500 mm from the circuit board 201 and is at a height of 50 mm from the reference GND 101.
- the circuit board 201 is also located at a height of 50 mm from the reference GND 101.
- the current probe 302 is fixed at a position 50 mm from the circuit board 201.
- the circuit board 201 was operated, and the common mode current 401 flowing through the power cable 202 was measured using the current probe 302 and the spectrum analyzer 301.
- Inductor elements are used for the impedance adjustment elements 31 and 32 on the upper part of the semiconductor device 10 in FIG. 1, the value of the impedance adjustment element 32 on the GND terminal side is fixed to 10 nH, and the value of the impedance adjustment element 31 on the power supply terminal side is 1 nH.
- the amount of change in the common mode current 401 when changing from 100 to 100 nH was measured.
- FIG. 5 is a diagram illustrating a generation state of the common mode current 401 when the semiconductor device 10 having no conductive plate 11 is mounted on the circuit board 201.
- FIG. 6 is a semiconductor having the conductive plate 11 mounted.
- FIG. 6 is a diagram illustrating a generation state of a common mode current 401 when the device 10 is mounted on a circuit board 201.
- the common mode current 401 can be suppressed by adjusting the impedance by the impedance adjusting elements 31 and 32.
- the parasitic capacitances 41 and 42 shown in FIG. 3 are not uniquely determined due to the influence of the wiring pattern of the circuit board 201 on which the semiconductor device 10 is mounted. Therefore, there is a balance point at which the common mode current 401 is minimized. Different for each frequency. For this reason, variations in the suppression effect of the common mode current 401 occur depending on the layout of the circuit board 201.
- the balance point is uniquely determined as shown in FIG. 6, and the common mode current 401 can be suppressed without being affected by the circuit board 201.
- the impedance is adjusted and balanced only inside the semiconductor device 10 using the impedance adjusting elements 31 and 32, thereby providing a semiconductor.
- the common mode current can be suppressed without being affected by the wiring pattern of the circuit board 201 on which the device 10 is mounted.
- FIG. 7 is a diagram illustrating a configuration example of the semiconductor device of this embodiment.
- the semiconductor device 10 of the present embodiment is an example where the power supply layer 22 and the GND layer 23 in the configuration of the semiconductor device 10 shown in FIG. 1 are not in the same plane but in different layers.
- the semiconductor device 10 can be handled in the same manner as the equivalent circuit shown in FIG. 3, and is the same as in the first embodiment.
- the common mode current can be suppressed by adjusting the impedance using the impedance adjusting elements 31 and 32.
- FIG. 8 is a diagram illustrating a configuration example of the semiconductor device of the present embodiment.
- the power supply terminal of the semiconductor chip 12 is connected to the power supply wiring 15 formed in the wiring layer via the wire 13.
- the power supply wiring 15 is connected to the power supply layer 22 and to the conductive plate 11 through the impedance adjustment element 33.
- the GND terminal of the semiconductor chip 12 is connected to the GND wiring 16 through the wire 14.
- the GND wiring 16 is connected to the GND layer 23 and is connected to the conductive plate 11 via the impedance adjustment element 34.
- a dielectric 21 is filled between the layers of the package substrate.
- the conductive plate 11 is disposed in the lowermost layer of the semiconductor device 10.
- the conductive plate 11 has a potential different from that of the power supply wiring 15 / GND wiring 16 inside the semiconductor device 10 with respect to the reference GND 101, and generates a parasitic capacitance for the power supply wiring 15 / GND wiring 16.
- the size of the conductive plate 11 may be arbitrary as long as it generates parasitic capacitance for the power supply wiring 15 / GND wiring 16.
- the conductive plate 11 is desirably provided on the contact surface side of the semiconductor device 10 with the circuit board. However, the conductive plate 11 is optional as long as it is a position where parasitic capacitance is generated with respect to the power supply wiring 15 / GND wiring 16 inside the semiconductor device 10. May be arranged.
- FIG. 9 is a diagram showing an equivalent circuit of the semiconductor device 10 of the present embodiment.
- An equivalent circuit of the power supply wiring 15 / GND wiring 16 of the semiconductor device 10 is represented by impedance adjusting elements 33 and 34 provided in the power supply wiring 15 / GND wiring 16, respectively, parasitic capacitance 41 generated in the power supply wiring 15 and the conductive plate 11, GND This is expressed using a parasitic capacitance 42 generated in the wiring 16 and the conductive plate 11, a parasitic inductance 43 of the power supply wiring 15, and a parasitic inductance 44 of the GND wiring 16.
- the generation of the common mode voltage 54 may be suppressed.
- the generation of the common mode voltage 54 can be suppressed if the bridge circuit composed of the noise source 51, the parasitic capacitors 41 and 42, the parasitic inductances 43 and 44, and the impedance adjusting elements 33 and 34 is balanced.
- the bridge circuit can be balanced by adjusting the impedance adjusting elements 33 and 34. .
- Z Cv and Z Cg are values obtained by combining the impedances of the parasitic capacitors 41 and 42 and the impedance adjusting elements 33 and 34 in the circuit of FIG. 9, and the impedances of the parasitic inductances 43 and 44 are Z Lv and Z Lg , respectively.
- the conditions for balancing the bridge circuit are the same as those in the first embodiment, where the parasitic capacitances 41 and 42 are C v and C g , respectively, and the impedance adjustment elements 33 and 34 are C v ′ and C v ′, respectively.
- C g ′ and the parasitic inductances 43 and 44 are L v and L g , respectively, the following equations are obtained.
- the common mode current 53 can be suppressed by adjusting the impedance adjusting elements 33 and 34 so as to satisfy this condition.
- the impedance adjusting elements 33 and 34 capacitive adjusting elements are used so that the power supply wiring 15 / GND wiring 16 and the conductive plate 11 are not short-circuited in a low frequency region.
- FIG. 10 is a diagram illustrating a configuration example of the semiconductor device of the present embodiment.
- the power supply terminal of the semiconductor chip 12 is connected to the power supply wiring 15 formed in the wiring layer via the wire 13.
- the power supply wiring 15 is connected to the power supply layer 22 through the impedance adjustment element 31 and is connected to the conductive plate 11 through the impedance adjustment element 33.
- the GND terminal of the semiconductor chip 12 is connected to the GND wiring 16 through the wire 14.
- the GND wiring 16 is connected to the GND layer 23 via the impedance adjustment element 32 and to the conductive plate 11 via the impedance adjustment element 34.
- a dielectric 21 is filled between the layers of the package substrate.
- the conductive plate 11 is disposed in the lowermost layer of the semiconductor device 10.
- the conductive plate 11 has a potential different from that of the power supply wiring 15 / GND wiring 16 inside the semiconductor device 10 with respect to the reference GND 101, and generates a parasitic capacitance for the power supply wiring 15 / GND wiring 16.
- the size of the conductive plate 11 may be arbitrary as long as it generates parasitic capacitance for the power supply wiring 15 / GND wiring 16.
- the conductive plate 11 is desirably provided on the contact surface side of the semiconductor device 10 with the circuit board. However, the conductive plate 11 is optional as long as it is a position where parasitic capacitance is generated with respect to the power supply wiring 15 / GND wiring 16 inside the semiconductor device 10. May be arranged.
- FIG. 11 is a diagram showing an equivalent circuit of the semiconductor device 10 of the present embodiment.
- An equivalent circuit of the power supply wiring 15 / GND wiring 16 of the semiconductor device 10 is connected to the impedance adjustment elements 31, 32 and impedance adjustment elements 33, 34, the power supply wiring 15 and the conductive plate 11 provided in the power supply wiring 15 / GND wiring 16, respectively. This is expressed by using the parasitic capacitance 41 generated, the parasitic capacitance 42 generated in the GND wiring 16 and the conductive plate 11, the parasitic inductance 43 of the power supply wiring 15, and the parasitic inductance 44 of the GND wiring 16.
- the generation of the common mode voltage 54 may be suppressed.
- the bridge circuit composed of the noise source 51, the parasitic capacitors 41 and 42, the parasitic inductances 43 and 44, and the impedance adjusting elements 31, 32, 33, and 34 is balanced, the common mode voltage 54 Generation can be suppressed.
- the bridge circuit is balanced by adjusting the impedance adjustment elements 31, 32, 33, and 34. can do.
- Z Cv and Z Cg are values obtained by combining the impedances of the parasitic capacitors 41 and 42 and the impedance adjustment elements 33 and 34 in the circuit of FIG. 11, and the parasitic inductances 43 and 44 and the impedance adjustment elements 31 and 32 are respectively set.
- the combined impedance values are Z Lv and Z Lg
- the conditions for balancing the bridge circuit are the same as in Equation 2 of the first embodiment, and the parasitic capacitances 41 and 42 are C v and C g , respectively.
- the adjustment elements 33 and 34 are C v ′ and C g ′, the parasitic inductances 43 and 44 are L v and L g , respectively, and the impedance adjustment elements 31 and 32 are L v ′ and L g ′, respectively, The formula is obtained.
- the common mode current 53 can be suppressed by adjusting the impedance adjusting elements 31, 32, 33, and 34 so as to satisfy this condition.
- the impedance adjusting elements 33 and 34 capacitive adjusting elements are used so that the power supply wiring 15 / GND wiring 16 and the conductive plate 11 are not short-circuited in a low frequency region.
- the impedance adjustment elements 31, 32, 33, and 34 are used only inside the semiconductor device 10. By adjusting and balancing the impedance, the common mode current can be suppressed and the noise current can be reduced without being affected by the wiring pattern of the circuit board 201 on which the semiconductor device 10 is mounted.
- FIG. 14 to 17 are diagrams showing examples of mounting the semiconductor device of the present embodiment.
- FIG. 14 is a diagram illustrating a mounting example of the semiconductor device 10
- FIGS. 15 to 17 are diagrams illustrating mounting examples of the first layer to the third layer of the semiconductor device 10, respectively.
- the power supply terminal of the semiconductor chip 12 is connected to the power supply wiring 25 formed in the first wiring layer via the wire 13.
- the power supply wiring 25 is connected to the second-layer power supply wiring 152 through the via 17. Further, it is connected to the power wiring 15 of the first layer through the via 20 and connected to the power wiring 151 through the impedance adjusting element 31. Further, it is connected to the power wiring 153 of the second layer through the via 201.
- the GND terminal of the semiconductor chip 12 is connected to the GND wiring 24 formed in the first wiring layer via the wire 14.
- the GND wiring 24 is connected to the second-layer GND wiring 162 through the via 19. Further, it is connected to the GND wiring 16 of the first layer through the via 18 and connected to the GND wiring 161 through the impedance adjustment element 32. Further, it is connected to the second-layer GND wiring 163 through the via 181.
- the third layer has a conductive plate 11 and is filled with a dielectric between the layers.
- the bypass capacitor 49 may be mounted between the power supply wiring and the GND wiring.
- FIG. 18 is a diagram illustrating a configuration example of the semiconductor device of the present embodiment.
- the semiconductor device 10 of the present embodiment is an example in which the conductive plate 11 is not disposed on the contact surface side with the circuit board but between the semiconductor chip 12, the power supply layer 22 and the GND layer 23.
- the equivalent circuit at this time is as shown in FIG. 19, and the power supply wiring 15 / GND wiring 16 on the package substrate has parasitic capacitances 411 and 421 with respect to the reference GND101.
- the dielectric 211 is inserted to partially change the dielectric constant in the package substrate, the dielectric constant of the dielectric 21 is changed, the distance between the package substrates is reduced, or the package
- the values of the parasitic capacitors 41 and 42 with respect to the parasitic capacitors 411 and 421 can be increased, and the influence of the parasitic capacitors 411 and 421 can be reduced. Accordingly, it is possible to handle the same equivalent circuit as in FIG. 4 as before.
- FIG. 20 is a diagram illustrating a configuration example of the semiconductor device of the present embodiment.
- the semiconductor device 10 according to the present embodiment is an example in the case where the impedance adjustment elements 31 and 32 are not provided.
- FIG. 21 is a diagram showing an equivalent circuit of the semiconductor device 10 of the present embodiment.
- An equivalent circuit of the power supply wiring 15 / GND wiring 16 of the semiconductor device 10 is represented by a parasitic capacitance 41 generated in the power supply wiring 15 and the conductive plate 11, a parasitic capacitance 42 generated in the GND wiring 16 and the conductive plate 11, and a parasitic inductance of the power supply wiring 15. 43, the parasitic inductance 44 of the GND wiring 16 is used.
- the parasitic capacitances 41 and 42 and the parasitic inductances 43 and 44 generated with respect to the conductive plate 11 and the power supply wiring 15 / GND wiring 16 on the package substrate should satisfy the number 2 shown in the first embodiment.
- the common mode current 53 can be reduced even when the impedance adjustment elements 31 and 32 are not provided.
- the generation of the common mode voltage 54 may be suppressed.
- the bridge circuit composed of the noise source 51, the parasitic capacitors 41 and 42, and the parasitic inductances 43 and 44 is balanced, the generation of the common mode voltage 54 can be suppressed.
- the noise source 51, the parasitic capacitances 41 and 42, and the parasitic inductances 43 and 44 are predetermined depending on the structure of the semiconductor device 10, the bridge circuit is designed to be balanced when the semiconductor device 10 is designed. I understand that
- the condition for the bridge circuit to be balanced is as follows. It becomes the same as the number 2 of. Accordingly, when the parasitic capacitances 41 and 42 are C v and C g respectively, and the parasitic inductances 43 and 44 are L v and L g respectively, the following equations are obtained.
- the common mode current 53 can be reduced by designing so as to satisfy Equation (6).
- FIG. 22 is a diagram illustrating a configuration example of the semiconductor device of this embodiment.
- the conductive plate 11 is disposed between the semiconductor chip 12 and the power supply layer 23.
- a capacitance is generated with respect to the reference GND 101 like the parasitic capacitances 411 and 421 shown in FIG.
- the dielectric 211 is inserted to partially change the dielectric constant in the package substrate, the dielectric constant of the dielectric 21 is changed, the distance between the package substrates is reduced, or the package
- the values of the parasitic capacitors 41 and 42 with respect to the parasitic capacitors 411 and 421 can be increased, and the influence of the parasitic capacitors 411 and 421 can be reduced. Accordingly, it is possible to handle the same equivalent circuit as in FIG. 11 as before.
- FIG. 23 is a diagram illustrating a configuration example of the semiconductor device of the present embodiment.
- the conductive plate 11 is disposed between the power supply layer 22 and the GND layer 23.
- a capacitance is generated with respect to the reference GND 101 like the parasitic capacitances 411 and 421 shown in FIG.
- the dielectric 211 is inserted to partially change the dielectric constant in the package substrate, the dielectric constant of the dielectric 21 is changed, the distance between the package substrates is reduced, or the package
- the values of the parasitic capacitors 41 and 42 with respect to the parasitic capacitors 411 and 421 can be increased, and the influence of the parasitic capacitors 411 and 421 can be reduced. Accordingly, it is possible to handle the same equivalent circuit as in FIG. 11 as before.
- Equation 2 is an expression that the common mode current can be reduced if the impedance products are made equal, but considering the impedance product ratio ⁇ expressed by the following expression: , ⁇ has a large reduction effect within an error range of 3%.
- a radiation electromagnetic field is defined by a tolerance value of an interference characteristic for protection of an in-vehicle receiver and a measurement method (CISPR25) Class 5 which is a standard created by the International Committee on Radio Interference (CISPR).
- CISPR25 measurement method
- CISPR25 measurement method
- it is necessary to set the radiated electromagnetic field distant by d 1 m from a wire harness such as the power cable 202 that connects the vehicle-mounted device and the power source to 12 dB ⁇ V / m or less.
- FIG. 24 is a diagram illustrating a generation state of the common mode current 401 when the semiconductor device of the first embodiment is mounted on a circuit board.
- FIG. 25 is a diagram showing an allowable error in the ratio of impedance products when the semiconductor device of the first embodiment is mounted on a circuit board.
- the impedance ratio Z Cg / Z Cv was variable from 1 to 50.
- the error needs to be 3% or less near the frequencies at which the power cable 202 resonates, 100 MHz, 200 MHz, and 300 MHz. You can see that you are satisfied.
- the impedance adjustment elements 31, 32, 33, and 34 are not all necessary as long as the conditions for balancing the bridge circuits in FIGS. It may be a configuration without a gap. Further, the impedance adjusting elements 31, 32, 33, and 34 do not have to be elements, and may be configured by a circuit wiring pattern and use the wiring impedance.
- the present invention is applicable to a semiconductor device that can reduce noise current.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structure Of Printed Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
以下では、本発明の実施の形態1である半導体装置について説明する。図1および図2は、本実施の形態の半導体装置の構成例を示す図である。
この回路においてコモンモード電流53を抑制する条件を導出する。
このため、回路基板201のレイアウトによってコモンモード電流401の抑制効果にばらつきが生じる。これに対し、導電板11を搭載した構成の半導体装置10では、図6のようにバランス点が一意に定まり、回路基板201の影響を受けずにコモンモード電流401を抑制することができる。
以下では、本発明の実施の形態2である半導体装置について説明する。図7は、本実施の形態の半導体装置の構成例を示す図である。本実施の形態の半導体装置10は、図1に示す半導体装置10の構成における電源層22、GND層23が同一面の層ではなく別層にある場合の例である。
以下では、本発明の実施の形態3である半導体装置について説明する。図8は、本実施の形態の半導体装置の構成例を示す図である。半導体チップ12の電源用端子は、ワイヤ13を介して配線層に形成された電源配線15に接続する。電源配線15は電源層22へ接続すると共に、インピーダンス調整素子33を介して導電板11へ接続する。また、同様に半導体チップ12のGND端子はワイヤ14を介してGND配線16に接続する。GND配線16はGND層23に接続すると共に、インピーダンス調整素子34を介して導電板11へ接続する。パッケージ基板の各層間には誘電体21が充填されている。
以下では、本発明の実施の形態4である半導体装置について説明する。図10は、本実施の形態の半導体装置の構成例を示す図である。半導体チップ12の電源用端子は、ワイヤ13を介して配線層に形成された電源配線15に接続する。電源配線15はインピーダンス調整素子31を介して電源層22へ接続すると共に、インピーダンス調整素子33を介して導電板11へ接続する。また、同様に半導体チップ12のGND端子はワイヤ14を介してGND配線16に接続する。GND配線16はインピーダンス調整素子32を介してGND層23に接続すると共にインピーダンス調整素子34を介して導電板11へ接続する。パッケージ基板の各層間には誘電体21が充填されている。
以下では、本発明の実施の形態5である半導体装置について説明する。図14~図17は、本実施の形態の半導体装置の実装例を示す図である。図14は、半導体装置10の実装例、図15~図17は、それぞれ、半導体装置10の第1層~第3層の実装例を示す図である。
以下では、本発明の実施の形態6である半導体装置について説明する。図18は、本実施の形態の半導体装置の構成例を示す図である。本実施の形態の半導体装置10は、導電板11が回路基板との接触面側ではなく、半導体チップ12と電源層22およびGND層23との間に配置されている場合の例である。
以下では、本発明の実施の形態7である半導体装置について説明する。図20は、本実施の形態の半導体装置の構成例を示す図である。本実施の形態の半導体装置10は、インピーダンス調整用素子31、32がない場合の例である。また、図21は、本実施の形態の半導体装置10の等価回路を示す図である。半導体装置10の電源配線15/GND配線16の等価回路を、電源配線15と導電板11に発生する寄生容量41、GND配線16と導電板11に発生する寄生容量42、電源配線15の寄生インダクタンス43、GND配線16の寄生インダクタンス44を用いて表している。
以下では本発明の実施の形態8である半導体装置について説明する。実施の形態2において説明したように、導電板11は回路基板面側に配置することが望ましいが、電源配線15/GND配線16に対して寄生容量を発生させる位置であれば任意に配置してよい。図22は、本実施の形態の半導体装置の構成例を示す図である。本実施の形態の半導体装置10では、導電板11が半導体チップ12と電源層23との間に配置されている。この場合の等価回路では、図19に示した寄生容量411、421のように、リファレンスGND101に対して容量が発生する。
以下では本発明の実施の形態9である半導体装置について説明する。実施の形態2において説明したように、導電板11は回路基板面側に配置することが望ましいが、電源配線15/GND配線16に対して寄生容量を発生させる位置であれば任意に配置してよい。図23は、本実施の形態の半導体装置の構成例を示す図である。本実施の形態の半導体装置10では、導電板11が電源層22とGND層23との間に配置されている。この場合の等価回路では、図19に示した寄生容量411、421のように、リファレンスGND101に対して容量が発生する。
Claims (7)
- パッケージ基板と、
前記パッケージ基板に搭載された半導体チップと、
前記半導体チップに第1の電源電位を供給する第1の配線と、
前記半導体チップに前記第1の電源電位よりも低い第2の電源電位を供給する第2の配線とを有する半導体装置であって、
前記第1の電源電位及び前記第2の電源電位とは異なる第3の電位を持つ導電板を有し、
さらに、前記第1の配線の経路上に設置され、前記第1の配線と前記第2の配線のインピーダンスを調整するための第1の素子と、
前記第2の配線の経路上に設置され、前記第1の配線と前記第2の配線のインピーダンスを調整するための第2の素子の少なくとも1つを有することを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の配線と前記導電板との間の寄生容量の第1のインピーダンスと、
前記第2の配線と前記導電板との間の寄生容量の第2のインピーダンスと、
前記第1の配線の寄生インダクタンスのインピーダンスと前記第1の素子のインピーダンスとを合成した第3のインピーダンスと、
前記第2の配線の寄生インダクタンスのインピーダンスと前記第2の素子のインピーダンスとを合成した第4のインピーダンスとにおいて、
前記第1のインピーダンスと前記第4のインピーダンスとの積が、前記第2のインピーダンスと前記第3のインピーダンスとの積と誤差3%の範囲で等しくなるように、前記第1の素子と前記第2の素子のインピーダンスが調整されていることを特徴とする半導体装置。 - パッケージ基板と、
前記パッケージ基板に搭載された半導体チップと、
前記半導体チップに第1の電源電位を供給する第1の配線と、
前記半導体チップに前記第1の電源電位よりも低い第2の電源電位を供給する第2の配線とを有する半導体装置であって、
前記第1の電源電位及び前記第2の電源電位とは異なる第3の電位を持つ導電板を有し、
さらに、前記第1の配線と前記導電板との間の経路上に設置され、前記第1の配線と前記第2の配線のインピーダンスを調整するための第1の素子と、
前記第2の配線と前記導電板との間の経路上に設置され、前記第1の配線と前記第2の配線のインピーダンスを調整するための第2の素子の少なくとも1つを有することを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記第1の配線と前記導電板との間の寄生容量のインピーダンスと前記第1の素子のインピーダンスとを合成した第1のインピーダンスと、
前記第2の配線と前記導電板との間の寄生容量のインピーダンスと前記第2の素子のインピーダンスとを合成した第2のインピーダンスと、
前記第1の配線の寄生インダクタンスの第3のインピーダンスと、
前記第2の配線の寄生インダクタンスの第4のインピーダンスとにおいて、
前記第1のインピーダンスと前記第4のインピーダンスとの積が、前記第2のインピーダンスと前記第3のインピーダンスとの積に誤差3%の範囲で等しくなるように、前記第1の素子と前記第2の素子のインピーダンスが調整されていることを特徴とする半導体装置。 - パッケージ基板と、
前記パッケージ基板に搭載された半導体チップと、
前記半導体チップに第1の電源電位を供給する第1の配線と、
前記半導体チップに前記第1の電源電位よりも低い第2の電源電位を供給する第2の配線とを有する半導体装置であって、
前記第1の電源電位及び前記第2の電源電位とは異なる第3の電位を持つ導電板を有し、
さらに、前記第1の配線の経路上に設置され、前記第1の配線と前記第2の配線のインピーダンスを調整するための第1の素子と、
前記第1の配線と前記導電板との間の経路上に設置され、前記第1の配線と前記第2の配線のインピーダンスを調整するための第2の素子と、
前記第2の配線の経路上に設置され、前記第1の配線と前記第2の配線のインピーダンスを調整するための第3の素子と、
前記第2の配線と前記導電板との間の経路上に設置され、前記第1の配線と前記第2の配線のインピーダンスを調整するための第4の素子の少なくとも1つを有することを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記第1の配線と前記導電板との間の寄生容量のインピーダンスと前記第2の素子のインピーダンスとを合成した第1のインピーダンスと、
前記第2の配線と前記導電板との間の寄生容量のインピーダンスと前記第4の素子のインピーダンスとを合成した第2のインピーダンスと、
前記第1の配線の寄生インダクタンスのインピーダンスと前記第1の素子のインピーダンスとを合成した第3のインピーダンスと、
前記第2の配線の寄生インダクタンスのインピーダンスと前記第3の素子のインピーダンスとを合成した第4のインピーダンスとにおいて、
前記第1のインピーダンスと前記第4のインピーダンスとの積が、前記第2のインピーダンスと前記第3のインピーダンスとの積に誤差3%の範囲で等しくなるように、前記第1~第4の素子のインピーダンスが調整されていることを特徴とする半導体装置。 - 請求項1~6のいずれか1項に記載の半導体装置において、
前記第1の配線と前記第2の配線のインピーダンスを調整するための素子が配線パターンで構成されることを特徴とする半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009551443A JPWO2009096203A1 (ja) | 2008-02-01 | 2009-01-07 | 半導体装置 |
US12/747,923 US20100283124A1 (en) | 2008-02-01 | 2009-01-07 | Semiconductor device |
CN2009801013542A CN101919050B (zh) | 2008-02-01 | 2009-01-07 | 半导体器件 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-022750 | 2008-02-01 | ||
JP2008022750 | 2008-02-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009096203A1 true WO2009096203A1 (ja) | 2009-08-06 |
Family
ID=40912556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/050047 WO2009096203A1 (ja) | 2008-02-01 | 2009-01-07 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20100283124A1 (ja) |
JP (1) | JPWO2009096203A1 (ja) |
CN (1) | CN101919050B (ja) |
WO (1) | WO2009096203A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102013216322A1 (de) | 2012-08-29 | 2014-03-06 | Denso Corporation | Elektronische Vorrichtung |
JP6052355B1 (ja) * | 2015-08-24 | 2016-12-27 | 株式会社デンソーEmcエンジニアリングサービス | 試験装置 |
WO2017217118A1 (ja) * | 2016-06-17 | 2017-12-21 | 日立オートモティブシステムズ株式会社 | 電子制御装置、車両および電子制御装置製造方法 |
JP2019039870A (ja) * | 2017-08-28 | 2019-03-14 | ファナック株式会社 | 検出装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6075834B2 (ja) * | 2012-08-16 | 2017-02-08 | キヤノン株式会社 | プリント回路板 |
US8990744B2 (en) | 2013-04-16 | 2015-03-24 | Infineon Technologies Ag | Electrical measurement based circuit wiring layout modification method and system |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11204699A (ja) * | 1998-01-09 | 1999-07-30 | Sony Corp | 半導体装置とその製造方法と電子装置 |
JP2001168266A (ja) * | 1999-12-13 | 2001-06-22 | Hitachi Ltd | 半導体装置 |
JP2003297964A (ja) * | 2002-03-28 | 2003-10-17 | Toshiba Corp | 高周波半導体装置 |
WO2006112010A1 (ja) * | 2005-04-13 | 2006-10-26 | Renesas Technology Corp. | 電子装置 |
JP2006332683A (ja) * | 2001-08-27 | 2006-12-07 | Nec Corp | 可変インダクタおよびそれを備えた高周波回路モジュール |
JP2008311964A (ja) * | 2007-06-14 | 2008-12-25 | Hitachi Ltd | コモンモード電位調整回路および伝送線路構造 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3456442B2 (ja) * | 1999-04-21 | 2003-10-14 | 日本電気株式会社 | プリント配線基板 |
JP3471679B2 (ja) * | 1999-10-15 | 2003-12-02 | 日本電気株式会社 | プリント基板 |
JPWO2004068577A1 (ja) * | 2003-01-27 | 2006-05-25 | 松下電器産業株式会社 | 半導体装置 |
-
2009
- 2009-01-07 US US12/747,923 patent/US20100283124A1/en not_active Abandoned
- 2009-01-07 CN CN2009801013542A patent/CN101919050B/zh not_active Expired - Fee Related
- 2009-01-07 JP JP2009551443A patent/JPWO2009096203A1/ja active Pending
- 2009-01-07 WO PCT/JP2009/050047 patent/WO2009096203A1/ja active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11204699A (ja) * | 1998-01-09 | 1999-07-30 | Sony Corp | 半導体装置とその製造方法と電子装置 |
JP2001168266A (ja) * | 1999-12-13 | 2001-06-22 | Hitachi Ltd | 半導体装置 |
JP2006332683A (ja) * | 2001-08-27 | 2006-12-07 | Nec Corp | 可変インダクタおよびそれを備えた高周波回路モジュール |
JP2003297964A (ja) * | 2002-03-28 | 2003-10-17 | Toshiba Corp | 高周波半導体装置 |
WO2006112010A1 (ja) * | 2005-04-13 | 2006-10-26 | Renesas Technology Corp. | 電子装置 |
JP2008311964A (ja) * | 2007-06-14 | 2008-12-25 | Hitachi Ltd | コモンモード電位調整回路および伝送線路構造 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102013216322A1 (de) | 2012-08-29 | 2014-03-06 | Denso Corporation | Elektronische Vorrichtung |
JP6052355B1 (ja) * | 2015-08-24 | 2016-12-27 | 株式会社デンソーEmcエンジニアリングサービス | 試験装置 |
WO2017217118A1 (ja) * | 2016-06-17 | 2017-12-21 | 日立オートモティブシステムズ株式会社 | 電子制御装置、車両および電子制御装置製造方法 |
US10952311B2 (en) | 2016-06-17 | 2021-03-16 | Hitachi Automotive Systems, Ltd. | Electronic control device, vehicle, and method for manufacturing electronic control device |
JP2019039870A (ja) * | 2017-08-28 | 2019-03-14 | ファナック株式会社 | 検出装置 |
Also Published As
Publication number | Publication date |
---|---|
US20100283124A1 (en) | 2010-11-11 |
CN101919050A (zh) | 2010-12-15 |
CN101919050B (zh) | 2012-02-29 |
JPWO2009096203A1 (ja) | 2011-05-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7679930B2 (en) | Multilayered printed circuit board | |
US8004369B2 (en) | Arrangement structure of electromagnetic band-gap for suppressing noise and improving signal integrity | |
WO2009096203A1 (ja) | 半導体装置 | |
JP2970660B1 (ja) | プリント基板 | |
JP2002335107A (ja) | 伝送線路型コンポーネント | |
WO2006112010A1 (ja) | 電子装置 | |
JP3654136B2 (ja) | 擬似大地化の方法及び装置 | |
US9345126B2 (en) | Semiconductor package and printed circuit board | |
US20110147063A1 (en) | Multilayer board for suppressing unwanted electromagnetic waves and noise | |
US10433420B2 (en) | Circuit board device and printed wiring board | |
JP2008198761A (ja) | 半導体装置 | |
JP2013030528A (ja) | 形成キャパシタ内蔵型多層プリント配線板 | |
JP2007242745A (ja) | プリント回路基板、cadプログラム、電磁界シミュレータ、回路シミュレータ、自動車、半導体装置、ならびにユーザガイド | |
JP5473549B2 (ja) | 半導体装置 | |
JP2010073792A (ja) | 半導体装置および1チップマイコン | |
WO2019111645A1 (ja) | 電子制御装置 | |
JP5264700B2 (ja) | 電子機器 | |
US11889616B2 (en) | Circuit board | |
JP7515588B2 (ja) | 電力変換装置 | |
JP2003347692A (ja) | プリント配線板、及び該プリント配線板で用いられる電磁波シールド方法 | |
JP2001203434A (ja) | プリント配線板及び電気機器 | |
CN114554678A (zh) | 复合布线基板、封装体及电子设备 | |
Matsushima et al. | Common-mode noise reduction using floating conductor in LSI package | |
AP | Design For EMI | |
JP2006120786A (ja) | プリント配線板及び電子機器 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980101354.2 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09706101 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009551443 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12747923 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09706101 Country of ref document: EP Kind code of ref document: A1 |