WO2009093762A1 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- WO2009093762A1 WO2009093762A1 PCT/JP2009/052260 JP2009052260W WO2009093762A1 WO 2009093762 A1 WO2009093762 A1 WO 2009093762A1 JP 2009052260 W JP2009052260 W JP 2009052260W WO 2009093762 A1 WO2009093762 A1 WO 2009093762A1
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- film
- forming
- ridge portion
- etching
- manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 163
- 238000000034 method Methods 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 93
- 238000005530 etching Methods 0.000 claims abstract description 73
- 239000000463 material Substances 0.000 claims abstract description 48
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 64
- 229910002601 GaN Inorganic materials 0.000 claims description 63
- 230000001681 protective effect Effects 0.000 claims description 54
- 239000010931 gold Substances 0.000 claims description 29
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 22
- 239000002253 acid Substances 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 19
- 238000000576 coating method Methods 0.000 claims description 19
- 239000010936 titanium Substances 0.000 claims description 19
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 18
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 7
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 7
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 7
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 7
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 7
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 7
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 6
- 229910017604 nitric acid Inorganic materials 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 85
- 150000001875 compounds Chemical class 0.000 description 39
- 230000015572 biosynthetic process Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 18
- 239000000758 substrate Substances 0.000 description 13
- 238000001020 plasma etching Methods 0.000 description 11
- 238000007740 vapor deposition Methods 0.000 description 10
- 238000000059 patterning Methods 0.000 description 9
- 239000007864 aqueous solution Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 238000010894 electron beam technology Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 230000007257 malfunction Effects 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 4
- 238000005253 cladding Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/2054—Methods of obtaining the confinement
- H01S5/2081—Methods of obtaining the confinement using special etching techniques
- H01S5/2086—Methods of obtaining the confinement using special etching techniques lateral etch control, e.g. mask induced
Definitions
- the present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element including a gallium nitride based semiconductor layer.
- Patent Document 1 a ridge structure is formed by dry etching in a gallium nitride based semiconductor layer using a first protective film made of silicon oxide or a photoresist film as a mask.
- a second protective film made of a material different from the first protective film is formed so as to cover the formed ridge portion (striped waveguide), and a mask for forming the ridge portion
- the upper surface of the ridge portion which is a region that should be in contact with the electrode, is exposed by removing the first protective film used as the substrate with hydrofluoric acid.
- the second protective film covers the side surface of the ridge portion, and its constituent materials are suggested to be oxides such as Ti, V, Zr, Nb, Hf, and Ta, BN, SiC, and AlN.
- Patent Document 2 discloses a structure in which electrodes are formed only on the upper surface of the ridge portion.
- Patent Document 3 discloses the following method as a method of forming the above-described ridge portion and the protective film covering the side surface of the ridge portion.
- a film composed of two layers of a SiO 2 film and a ZrO 2 film is formed on the gallium nitride based semiconductor layer as the first protective film, and the first protective film is subjected to heat treatment in an oxygen atmosphere.
- the ZrO 2 film is not etched by ammonium fluoride.
- the first protective film made of the SiO 2 film and the ZrO 2 film is partially removed by reactive ion etching (RIE), thereby forming a ridge pattern on the first protective film.
- RIE reactive ion etching
- the gallium nitride based semiconductor layer is partially removed by dry etching using an etching gas containing chlorine gas using the first protective film as a mask, thereby forming a ridge portion. Thereafter, by immersing the sample in an ammonium fluoride solution, the side wall portion of the SiO 2 film located under the first protective film is retracted by etching.
- the ZrO 2 film is not etched by ammonium fluoride by the heat treatment described above, only the SiO 2 film can be selectively etched.
- a ZrO 2 film is formed as a second protective film so as to cover the entire first protective film and the ridge portion by using an electron beam vapor deposition method or a sputtering vapor deposition method.
- the ZrO 2 film as the second protective film is not deposited on the side wall of the SiO 2 film.
- the ZrO 2 film located on the SiO 2 film is also removed at the same time.
- the ZrO 2 film as the second protective film covers the side wall of the ridge portion, and the upper surface of the ridge portion is exposed, and an electrode can be formed on the upper surface.
- the conventional semiconductor element manufacturing method described above has the following problems. That is, in the manufacturing method disclosed in Patent Document 1, the second protective film located on the upper surface of the ridge portion is removed by removing the first protective film with hydrofluoric acid while the second protective film is formed. The film portion is removed (the second protective film is removed using a lift-off method). However, at this time, the portion of the second protective film may not be completely removed from the upper surface of the ridge portion, and a part of the second protective film may remain as burrs. In this case, even if the electrode is formed on the upper surface of the ridge portion, the contact between the upper surface of the ridge portion and the electrode may be incomplete, and the manufacturing yield of the semiconductor element may be reduced. In this case, it has been difficult to reduce the manufacturing cost of the semiconductor element.
- the ZrO 2 film constituting the first protective film needs to be heat-treated in an oxygen atmosphere in order to increase resistance to ammonia fluoride (so as not to be etched by ammonia fluoride). In addition, since such heat treatment is necessary, it has been difficult to reduce the manufacturing cost.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a semiconductor element capable of reducing the manufacturing cost.
- a step of preparing a gallium nitride based semiconductor layer constituting a semiconductor element is performed.
- a step of forming a first film on the gallium nitride based semiconductor layer is performed.
- a step of forming a second film having a pattern in which the etching rate by the alkaline etchant is made of a material smaller than the material constituting the first film is performed.
- the first film and the gallium nitride based semiconductor layer are partially removed by etching, whereby a ridge portion is formed in the gallium nitride based semiconductor layer in a region located below the second film.
- the step of forming is performed. Removing the end of the first film located on the ridge by etching using an alkaline etchant, thereby retreating the position of the end face of the first film from the position of the end face of the second film. carry out.
- a step of forming a protective film made of a material whose etching rate by an alkaline etchant is smaller than the material constituting the first film on the side surface of the ridge portion and the upper surface of the second film is performed. By removing the first film by etching using an alkaline etchant, a step of removing the second film and the portion of the protective film formed on the upper surface of the second film is performed.
- a step of forming an electrode on the surface of the ridge portion exposed by removing the first film is performed.
- a step of preparing a gallium nitride based semiconductor layer constituting a semiconductor element is performed.
- a step of forming a first film on the gallium nitride based semiconductor layer is performed.
- a step of forming a second film having a pattern in which an etching rate by a mixed acid composed of phosphoric acid, nitric acid, acetic acid and water is made of a material smaller than the material constituting the first film is performed.
- the first film and the gallium nitride based semiconductor layer are partially removed by etching, so that a ridge is formed on the gallium nitride based semiconductor layer in a region located under the second film.
- the step of forming the part is performed.
- the step of retreating the position of the end face of the first film from the position of the end face of the second film is performed by removing the end of the first film located on the ridge by etching using a mixed acid. .
- a step of forming a protective film made of a material whose etching rate by the mixed acid is smaller than that of the material constituting the first film on the side surface of the ridge portion and the upper surface of the second film is performed.
- a step of removing the second film and the portion of the protective film formed on the upper surface of the second film is performed.
- a step of forming an electrode on the surface of the ridge portion exposed by removing the first film is performed.
- the second film is used as a mask for forming the ridge portion, and at the same time, the first film is removed to expose the upper surface of the ridge portion (the protective film on the upper surface). Since the second film (in which the portion is formed) is removed, the protective film portion can be reliably removed from the upper surface of the ridge portion. Therefore, in order to remove the protective film portion from the upper surface of the ridge portion, the upper surface of the ridge portion is compared with the case where a new resist pattern is formed separately from the mask used for forming the ridge portion. The possibility that the position and the position of the portion where the protective film is removed can be reduced.
- the end of the first film is retracted from the position of the end of the second film in advance before forming the protective film, a part of the protective film is not removed when the protective film is formed.
- the possibility of being formed on the end surface of one film can be reduced.
- the first film cannot be sufficiently removed because a part of the protective film is formed on the end surface of the first film (therefore, the first film is removed). 2) and the portion of the protective film formed on the upper surface of the second film cannot be sufficiently removed).
- the second film is formed of a material whose etching rate by an alkaline etchant or mixed acid is smaller than the material forming the first film, the first film is selectively etched with respect to the second film. Therefore, it is not necessary to perform additional processing such as heat treatment. Therefore, the number of manufacturing steps of the semiconductor element can be reduced as compared with the case where the additional processing as described above is performed. As a result, the manufacturing cost of the semiconductor element can be reduced.
- Embodiment 1 of the manufacturing method of the compound semiconductor device according to this invention It is a cross-sectional schematic diagram for demonstrating each process of the manufacturing method of the compound semiconductor element shown in FIG. It is a cross-sectional schematic diagram for demonstrating each process of the manufacturing method of the compound semiconductor element shown in FIG. It is a cross-sectional schematic diagram for demonstrating each process of the manufacturing method of the compound semiconductor element shown in FIG. It is a cross-sectional schematic diagram for demonstrating each process of the manufacturing method of the compound semiconductor element shown in FIG. It is a cross-sectional schematic diagram for demonstrating each process of the manufacturing method of the compound semiconductor element shown in FIG. It is a cross-sectional schematic diagram for demonstrating each process of the manufacturing method of the compound semiconductor element shown in FIG.
- FIG. 1 is a flowchart showing Embodiment 1 of a method for producing a compound semiconductor device according to the present invention.
- 2 to 11 are schematic cross-sectional views for explaining each process of the method for manufacturing the compound semiconductor device shown in FIG. A method for manufacturing a compound semiconductor device according to the present invention will be described with reference to FIGS.
- a GaN-based semiconductor layer forming step (S10) is performed.
- a GaN-based semiconductor layer 2 is formed on the main surface of the substrate 1 using an epitaxial growth method or the like.
- the substrate 1 for example, a substrate capable of forming a GaN-based semiconductor layer on its main surface, such as a substrate made of GaN or another substrate made of sapphire, can be used.
- the configuration of the GaN-based semiconductor layer 2 a structure in which a plurality of GaN-based semiconductor layers are stacked can be employed according to the required characteristics of the compound semiconductor element to be formed.
- the configuration of the GaN-based semiconductor layer 2 is that when a GaN substrate is used as the substrate 1, an n-type cladding layer and a p-type cladding layer are formed on the substrate 1. In other words, a configuration in which the active layer is sandwiched between the n-type cladding layer and the p-type cladding layer can be used.
- the GaN (gallium nitride) -based semiconductor layer 2 a semiconductor layer having any composition can be used as long as it is a semiconductor layer containing gallium (Ga) and nitrogen (N) in the composition.
- the first film formation step (S20) is performed.
- an aluminum film (Al film 3) as a first film is formed on the GaN-based semiconductor layer 2.
- the Al film 3 can be formed by an arbitrary method such as a vapor deposition method or a sputter vapor deposition method.
- the thickness of the Al film 3 as the first film can be, for example, 0.05 ⁇ m or more and 1 ⁇ m or less.
- the lower limit of the thickness of the Al film 3 is set to 0.05 ⁇ m so that the lift-off of the mask layer 14 and the like in the lift-off process (S80) described later can be performed without problems if the thickness of the Al film 3 is 0.05 ⁇ m or more. It is because it can do.
- a second film forming step (S30) is performed.
- a silicon oxide film (SiO 2 film 4) as a second film is formed on the Al film 3 described above.
- This SiO 2 film 4 is made of, for example, CV It can be formed by using any method such as D (Chemical Vapor Deposition) method, EB (Electron Beam) vapor deposition method, sputtering method or the like.
- the thickness of the SiO 2 film 4 is, for example, 0.1 It can be set to ⁇ m or more and 1 ⁇ m or less.
- the lower limit of the thickness of the SiO 2 film 4 is set to 0.1 ⁇ m because the minimum thickness required for the SiO 2 film 4 to remain until the etching is completed in the etching process in the convex forming process (S50). This is because it was 0.1 ⁇ m.
- the upper limit of the thickness of the SiO 2 film 4 is set to 1 ⁇ m because the upper limit of the thickness at which the patterning of the SiO 2 film 4 can be finished before the resist film 5 disappears in the patterning step (S40) is 1 ⁇ m. It is.
- a patterning step (S40) is performed as shown in FIG.
- a resist film is first formed on the surface of the SiO 2 film 4.
- a predetermined pattern is transferred to the resist film using a photolithography method.
- a resist film 5 having a predetermined pattern is formed on the SiO 2 film 4 as shown in FIG.
- the planar shape of the resist film 5 corresponds to the planar shape of the upper surface of the ridge portion described later.
- a convex part formation process (S50) is implemented as shown in FIG.
- the structure shown in FIG. 5 is obtained by partially removing the SiO 2 film 4 by etching using the resist film 5 described above as a mask. That is, by the etching, a mask layer 14 composed of the SiO 2 film 4 (see FIG. 4) is formed under the resist film 5.
- the planar shape of the mask layer 14 is the same as the planar shape of the resist film 5.
- reactive ion etching (RIE) using a fluorine-based etching gas is used.
- the resist film 5 is removed by wet etching or the like.
- a structure as shown in FIG. 6 is obtained.
- the mask layer 14 made of SiO 2 as a mask
- the Al film 3 and the GaN-based semiconductor layer 2 are partially removed by etching.
- the Al film 3 and the GaN-based semiconductor layer 2 are partially removed by RIE using a chlorine-based etching gas.
- the Al film 13 and the ridge portion 12 as a convex portion that is a part of the GaN-based semiconductor layer are formed under the mask layer 14.
- a structure as shown in FIG. 7 can be obtained.
- the height of the ridge portion 12 as a convex portion (the height from the flat upper surface of the GaN-based semiconductor layer 2 adjacent to the ridge portion 12 to the upper surface of the ridge portion 12) is the etching processing time described above, etc. It can be arbitrarily determined by adjusting the process conditions.
- a step (S60) of retracting the side wall of the first film is performed.
- an arbitrary etching method is used in which the etching rate for the Al film 13 as the first film is higher than the etching rate for the mask layer 14 made of the SiO 2 film as the second film.
- the side wall of the Al film 13 can be partially removed by immersing the substrate having the structure shown in FIG. 7 in an alkaline aqueous solution (for example, Semico Clean 23 manufactured by Furuuchi Chemical Co., Ltd.). In this way, the position of the side wall 23 of the Al film 13 is made to recede from the position of the side wall 24 of the mask layer 14.
- the amount of receding of the side wall 23 of the Al film 13 with respect to the side wall 24 of the mask layer 14 is preferably 0.05 ⁇ m or more.
- the thickness may be 1 ⁇ m or less, more preferably 0.1 ⁇ m or more and 0.5 ⁇ m or less.
- the third film formation step (S70) shown in FIG. 1 is performed.
- the SiO 2 film 6 as the third film is formed on the sidewall of the ridge portion 12, on the upper surface of the GaN-based semiconductor layer 2 other than the ridge portion 12, and on the upper surface of the mask layer 14. To do.
- the thickness of the SiO 2 film 6 as the protective film can be set to 0.05 ⁇ m or more and 0.5 ⁇ m or less, for example.
- any method such as the EB vapor deposition method or the sputter vapor deposition method described above can be used. Further, since the position of the side wall 23 of the Al film 13 is set back from the position of the side wall 24 of the mask layer 14, the SiO 2 film 6 is not formed on the side wall 23 of the Al film 13.
- a lift-off process (S80) is performed.
- a sample having a structure as shown in FIG. 9 is immersed in an alkaline aqueous solution (for example, Semico Clean 23 manufactured by Furuuchi Chemical Co., Ltd.).
- an alkaline aqueous solution for example, Semico Clean 23 manufactured by Furuuchi Chemical Co., Ltd.
- the alkaline aqueous solution selectively etches the Al film 13, so that the Al film 13 is removed.
- the mask layer 14 made of the SiO 2 film located on the Al film 13 and the SiO 2 film 6 formed on the mask layer 14 are also removed at the same time.
- a structure as shown in FIG. 10 is obtained. As can be seen from FIG.
- the state in which the above-described SiO 2 film 6 is formed on the side wall of the ridge portion 12 is maintained.
- the Al film 13 is also used as a mask for forming the ridge portion 12 and a lift-off mask for removing a portion of the SiO 2 film 6 located on the ridge portion 12. is doing. For this reason, the position of the upper surface of the ridge portion 12 and the region where the SiO 2 film 6 is removed using the lift-off method are almost exactly overlapped, and there is no deviation in the positional relationship. Therefore, a semiconductor element with an accurate ridge structure can be obtained.
- an electrode formation step (S90) is performed. Specifically, as shown in FIG. 11, one electrode 7 is formed at a position in contact with the upper surface of the ridge portion 12, and the back surface side of the substrate 1 (the main surface on which the GaN-based semiconductor layer 2 is formed) The other electrode 8 is formed on the opposite back surface.
- any conventionally known method such as lift-off can be used. For example, a resist film having an opening pattern is formed in a region covering the ridge portion where the electrode 7 is to be formed, and a conductor film to be the electrode 7 is formed on the resist film. Then, the resist film is removed by wet etching to form an electrode.
- the method for manufacturing the electrode 8 can use processes such as formation of a mask layer, formation of a conductor film on the mask, and lift-off by wet etching.
- the electrode 7 is formed so that its width is wider than the width of the upper surface of the ridge portion 12 (the distance between the side walls of the ridge portion 12). That is, the electrode 7 extends from the upper surface of the ridge portion 12 onto the SiO 2 film 6. In this way, when the width of the upper surface of the ridge portion 12 is extremely narrow, even when the formation position of the electrode 7 varies to some extent, the electrode 7 is securely connected to the upper surface of the ridge portion 12. can do.
- the semiconductor element according to the present invention can be obtained by dividing the substrate 1 into individual chips using a dicing saw or the like.
- SiO 2 silicon monoxide instead of (SiO), silicon nitride (SiN), zirconium oxide (ZrO 2), tantalum oxide (Ta 2 O 3), lanthanum oxide (La 2 Any of O 5 ), cerium oxide (CeO 3 ), and hafnium oxide (HfO 2 ), or two or more of these materials may be used.
- SiO 2 film 6 a silicon monoxide film (SiO film), a silicon nitride film (SiN film), a zirconium oxide film (ZrO 2 film), a tantalum oxide film (Ta 2 O 3 film), a lanthanum oxide film Any of (La 2 O 5 film), cerium oxide film (CeO 3 film), hafnium oxide film (HfO 2 film), or a composite film thereof may be used.
- FIG. 12 is a schematic cross-sectional view for explaining Embodiment 2 of the method for producing a compound semiconductor element according to the present invention. With reference to FIG. 12, Embodiment 2 of the manufacturing method of the compound semiconductor element by this invention is demonstrated.
- the second embodiment of the method for manufacturing a compound semiconductor device according to the present invention basically includes the same steps as those of the method for manufacturing a compound semiconductor device described with reference to FIGS.
- the layers used as masks when forming are different.
- Embodiment 2 of the method for manufacturing a compound semiconductor device according to the present invention first, the steps (S10) to (S40) in the manufacturing method shown in FIG. 1 are similarly performed. As a result, a structure as shown in FIG. 4 is obtained.
- the resist film 5 is used as a mask, and the SiO 2 film 4 is partially removed by RIE using a fluorine-based etching gas, as shown in FIG. A structure like this is obtained.
- the Al film 3 and the GaN-based semiconductor layer 2 are etched as they are without removing the resist film 5. Specifically, using the resist film 5 and the mask layer 14 as a mask, the Al film 3 and the GaN-based semiconductor layer 2 are partially removed by RIE using a chlorine-based etching gas. As a result, a structure as shown in FIG. 12 is obtained.
- the resist film 5 is removed using wet etching or the like. Thereafter, by performing the steps (S60) to (S90) in the first embodiment described above, a compound semiconductor element as shown in FIG. 11 can be obtained.
- the third embodiment of the method for manufacturing a compound semiconductor device according to the present invention basically has the same configuration as that of the first embodiment of the method for manufacturing a compound semiconductor device according to the present invention shown in FIGS.
- the etchant used in the step of retracting the side wall of the first film (S60) and the lift-off step (S80) is not an alkaline aqueous solution but a mixed acid composed of phosphoric acid, nitric acid, acetic acid and water.
- the mixed acid for example, a mixed acid having a composition in which phosphoric acid is 80 mass%, nitric acid is 5 mass%, acetic acid is 10 mass%, and the balance is water can be used. Even if it does in this way, the effect similar to Embodiment 1 of this invention can be acquired.
- the material of the mask layer 14 described above is changed to SiO 2 instead of SiO 2 , silicon monoxide (SiO), silicon nitride (SiN), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 3 ), lanthanum oxide (La 2 O 5 ), cerium oxide (CeO 3 ), and hafnium oxide (HfO 2 ), or two or more of these materials may be used.
- any one of a SiO film, a SiN film, a ZrO 2 film, a Ta 2 O 3 film, a La 2 O 5 film, a CeO 3 film, and a HfO 2 film, or a composite film thereof is used. It may be used.
- the Al film 3 and the GaN-based semiconductor layer 2 may be etched without removing the resist film 5 as shown in FIG.
- FIGS. 13 to 19 are schematic cross-sectional views for explaining Embodiment 4 of the compound semiconductor device manufacturing method according to the present invention.
- Embodiment 4 of the method for manufacturing a compound semiconductor device according to the present invention will be described.
- the fourth embodiment of the method for manufacturing a compound semiconductor device according to the present invention basically includes the same steps as the method for manufacturing a compound semiconductor device described with reference to FIGS. 1 to 11, but the first film. After forming the Al film 3 as a film and before forming the SiO 2 film 4 as the second film, a film made of gold as a coating film on the Al film 3 (Au film 9 (see FIG. 13)) Is different. This will be specifically described below.
- a GaN-based semiconductor layer forming step (S10) (see FIG. 1) is performed as in the first embodiment of the method for manufacturing a compound semiconductor device according to the present invention.
- the GaN-based semiconductor layer 2 is formed on the main surface of the substrate 1 using an epitaxial growth method or the like.
- the first film formation step (S20) is performed.
- an Al film 3 (see FIG. 13) as a first film is formed on the GaN-based semiconductor layer 2.
- a method for forming the Al film 3 an arbitrary method such as an EB vapor deposition method or a sputtering method can be used.
- the thickness of the Al film 3 can be set to 0.3 ⁇ m, for example.
- a coating film forming step is performed.
- an Au film 9 (see FIG. 13) as a coating film is formed on the Al film 3.
- This Au film 9 can also be formed by an arbitrary method.
- the thickness of the Au film 9 can be set to, for example, 0.005 ⁇ m or more and 0.05 ⁇ m or less (for example, about 0.01 ⁇ m).
- the second film formation step (S30) shown in FIG. 1 is performed.
- the SiO 2 film 4 as the second film is formed on the Au film 9 described above.
- a structure as shown in FIG. 13 is obtained.
- a patterning step (S40) is performed in the same manner as the manufacturing method shown in FIG. As a result, a resist film 5 having a predetermined pattern is formed on the SiO 2 film 4 as shown in FIG.
- the planar shape of the resist film 5 corresponds to the planar shape of the upper surface of the ridge portion described later.
- the convex part formation process (S50) is implemented similarly to the manufacturing method shown in FIG.
- the structure as shown in FIG. 15 is obtained by partially removing the SiO 2 film 4 by etching using the resist film 5 described above as a mask. That is, by the etching, a mask layer 14 composed of the SiO 2 film 4 (see FIG. 14) is formed under the resist film 5.
- the planar shape of the mask layer 14 is the same as the planar shape of the resist film 5.
- reactive ion etching (RIE) using a fluorine-based etching gas is used.
- the resist film 5 is removed by wet etching or the like. As a result, a structure as shown in FIG. 16 is obtained. Then, using the mask layer 14 as a mask, the Au film 9, the Al film 3, and the GaN-based semiconductor layer 2 are partially removed by etching. In this etching process, the Au film 9, the Al film 3, and the GaN-based semiconductor layer 2 are partially removed by RIE using a chlorine-based etching gas. As a result, as shown in FIG. 17, the ridge portion 12 as a convex portion which is a part of the Au film 19, the Al film 13 and the GaN-based semiconductor layer is formed under the mask layer 14.
- the mask layer 14 is formed, and the etching of the Au film 9 is continuously performed when the Al film 3 and the GaN-based semiconductor layer 2 are etched.
- the timing of etching may be different.
- the Au film is partially removed by etching using the resist film 5 as a mask in succession, whereby a pattern similar to the pattern of the resist film 5 is obtained.
- the Au film 19 may be formed. In this case, the Au film 9 is not etched in the partial etching process of the Al film 3 and the GaN-based semiconductor layer 2 described with reference to FIG.
- a step (S60) of retracting the side wall of the first film is performed.
- the etching rate for the Al film 13 as the first film is higher than the etching rate for the mask layer 14 (and preferably the Au film 19) made of the SiO 2 film as the second film, and Any etching method can be used.
- the side wall of the Al film 13 can be partially removed by immersing the substrate having the structure shown in FIG. 17 in an alkaline aqueous solution (for example, Semico Clean 23 manufactured by Furuuchi Chemical Co., Ltd.). In this way, the position of the side wall 23 of the Al film 13 is made to recede inward from the positions of the side wall 24 of the mask layer 14 and the side wall 29 of the Au film 19. As a result, a structure as shown in FIG. 18 is obtained.
- a third film formation step (S70) is performed as in the manufacturing method shown in FIG.
- the SiO 2 film 6 as the third film is formed on the sidewall of the ridge portion 12, the upper surface of the GaN-based semiconductor layer 2 other than the ridge portion 12, and the mask layer. 14 on the upper surface.
- any method such as the EB vapor deposition method or the sputter vapor deposition method described above can be used. Further, since the position of the side wall 23 of the Al film 13 is set back from the position of the side wall 24 of the mask layer 14, the SiO 2 film 6 is not formed on the side wall 23 of the Al film 13.
- a lift-off process (S80) is performed.
- a sample having a structure as shown in FIG. 19 is immersed in an alkaline aqueous solution (for example, Semico Clean 23 manufactured by Furuuchi Chemical Co., Ltd.).
- an alkaline aqueous solution for example, Semico Clean 23 manufactured by Furuuchi Chemical Co., Ltd.
- the alkaline aqueous solution selectively etches the Al film 13, so that the Al film 13 is removed.
- the mask layer 14, the Au film 19, and the SiO 2 film 6 formed on the mask layer 14 are also removed at the same time.
- a structure as shown in FIG. 10 is obtained.
- step (S90) see FIG. 1) in the first embodiment described above, a compound semiconductor element as shown in FIG. 11 can be obtained.
- the etchant used in the step of retracting the side wall of the first film (S60) and the lift-off step (S80) is not an alkaline aqueous solution, but phosphoric acid, nitric acid, acetic acid, and the like described in the third embodiment of the present invention. You may use the mixed acid which consists of water.
- the possibility that the end surface of the ridge portion becomes rough can be reduced. Further, a step of partially removing the Ti film 9, the Al film 3, and the GaN-based semiconductor layer 2 by RIE using a chlorine-based etching gas is performed. At this time, a ridge in which fine debris of the Ti film 9 is etched The possibility of remaining on the surface of the part is small. For this reason, the fine Ti film 9 attached to the ridge portion serves as a fine mask and is less likely to be affected during etching, so that a reduction in the yield of the semiconductor element can be suppressed. Needless to say, when titanium is used as the coating film, the coating film becomes the Ti film 19 after the lift-off process.
- the film forming method, the thickness to be formed, the Al film 3 as the first film at that time, and the second film All other conditions such as the thickness of the SiO 2 film 4 and the like may be the same as in the case where the Au film 9 is used as the coating film.
- the lift-off method may be used in the second film formation step (S30) and the patterning step (S40). Specifically, a resist film having an opening pattern in a region where the ridge portion 12 is to be formed is formed on the Al film 3 as the first film, and SiO 2 as the second film is formed on the resist film. A film 4 is formed. At this time, a part of the SiO 2 film 4 (part to be the mask layer 14) is formed in the state of being in contact with the Al film 3 inside the opening pattern. Then, by removing the resist film by wet etching, the other part of the SiO 2 film 4 is removed together with the resist film, leaving the part to be the mask layer 14. In this way, a structure as shown in FIG. 6 may be formed.
- a step of preparing a gallium nitride based semiconductor layer (GaN based semiconductor layer 2) constituting the semiconductor element (GaN based semiconductor layer forming step (S10)) is performed.
- a step of forming a first film (Al film 3) on the GaN-based semiconductor layer 2 (first film formation step (S20)) is performed.
- a process (second film forming process (S30) and patterning process) of forming a second film (mask layer 14) having an etching rate of an alkaline etchant made of a material smaller than the material constituting the Al film 3 and having a pattern. (S40)) is performed.
- the Al film 3 and the GaN-based semiconductor layer 2 are partially removed by etching, whereby a region located under the second film (mask layer 14) Then, the step of forming the ridge portion 12 in the GaN-based semiconductor layer 2 (convex portion forming step (S50)) is performed.
- the end of the Al film 13 (see FIG. 7) located on the ridge portion 12 is removed by etching using an alkaline etchant, whereby the position of the end face of the Al film 13 (position of the side wall 23) is changed to the mask layer 14.
- a step of retracting from the position of the end face (position of the side wall 24) (step of retracting the side wall of the first film (S60)) is performed.
- a third film formation step (S70)) is performed.
- the Al film 13 is removed by etching using an alkaline etchant, thereby removing the mask layer 14 and the portion of the SiO 2 film 6 formed on the upper surface of the mask layer 14 (lift-off process (S80)). To implement. A step of forming the electrode 7 on the surface of the ridge portion 12 exposed by removing the Al film 13 (electrode forming step (S90)) is performed.
- the mask layer 14 is used as a mask for forming the ridge portion 12, and at the same time by removing the Al film 13 to expose the upper surface of the ridge portion 12 (as a protective film on the upper surface). portion of the SiO 2 film 6 is formed) because the mask layer 14 is removed, it can be reliably removed portion of the SiO 2 film 6 from the upper surface of the ridge portion 12. Therefore, in order to remove the portion of the SiO 2 film 6 from the upper surface of the ridge portion 12, compared to a case where a new resist pattern or the like is formed separately from the mask layer 14 used for forming the ridge portion 12, The possibility that the position of the upper surface of the ridge portion 12 and the position of the portion where the SiO 2 film 6 is removed can be reduced.
- the SiO 2 film 6 is formed when the SiO 2 film 6 is formed.
- the possibility that a part of the two films 6 is formed on the side wall 23 of the Al film 13 can be reduced.
- the Al film 13 cannot be sufficiently removed because a part of the SiO 2 film 6 is formed on the side wall 23 of the Al film 13 (for this reason, the mask layer). 14 and the portion of the SiO 2 film 6 formed on the upper surface of the mask layer 14 cannot be sufficiently removed). For this reason, it is possible to reduce the probability of occurrence of malfunction of the semiconductor element due to the above problems. As a result, an increase in manufacturing cost due to a decrease in manufacturing yield of semiconductor elements can be suppressed.
- the mask layer 14 is made of a material (SiO 2 ) whose etching rate by the alkaline etchant is smaller than the material (Al) constituting the Al film 13, the Al film 13 is selectively formed with respect to the mask layer 14. There is no need to perform additional processing such as heat treatment for etching. Therefore, the number of manufacturing steps of the semiconductor element can be reduced as compared with the case where the additional processing as described above is performed. As a result, the manufacturing cost of the semiconductor element can be reduced.
- a step of preparing a gallium nitride based semiconductor layer (GaN based semiconductor layer 2) constituting the semiconductor element (GaN based semiconductor layer forming step (S10)) is performed.
- a step of forming a first film (Al film 3) on the GaN-based semiconductor layer 2 (first film formation step (S20)) is performed.
- a step of forming a second film (mask layer 14) having a pattern in which an etching rate by a mixed acid composed of phosphoric acid, nitric acid, acetic acid and water is smaller than the material constituting the Al film 3 and having a pattern (second film formation) Step (S30) and patterning step (S40)) are performed.
- the second film (mask layer 14) as a mask, the Al film 3 and the GaN-based semiconductor layer 2 are partially removed by etching, whereby a region located under the second film (mask layer 14)
- the step of forming the ridge portion 12 in the GaN-based semiconductor layer 2 (convex portion forming step (S50)) is performed.
- the position of the end face of the Al film 13 is changed to the position of the end face of the mask layer 14 (position of the side wall 24).
- the step of retreating from the position is performed.
- a step of forming a protective film (SiO 2 film 6) made of a material whose etching rate by the mixed acid is smaller than the material constituting the Al films 3 and 13 on the side surface of the ridge portion 12 and the upper surface of the mask layer 14 (third The film forming step (S70)) is performed.
- the step of removing the Al layer 13 by etching using a mixed acid to remove the mask layer 14 and the portion of the SiO 2 film 6 formed on the upper surface of the mask layer 14 is performed.
- a step of forming the electrode 7 on the surface of the ridge portion 12 exposed by removing the Al film 13 is performed.
- the mask layer 14 is used as a mask for forming the ridge portion 12, and at the same time, by removing the Al film 13 to expose the upper surface of the ridge portion 12, (on the upper surface, SiO 2 Since the mask layer 14 (in which the film 6 portion is formed) is removed, the SiO 2 film 6 portion can be reliably removed from the upper surface of the ridge portion 12. Therefore, in order to remove the portion of the SiO 2 film 6 from the upper surface of the ridge portion 12, compared to a case where a new resist pattern or the like is formed separately from the mask layer 14 used for forming the ridge portion 12, The possibility that the position of the upper surface of the ridge portion 12 and the position of the portion where the SiO 2 film 6 is removed can be reduced.
- the SiO 2 film at the time of forming the SiO 2 film 6 The possibility that part of 6 is formed on the side wall 23 of the Al film 13 can be reduced. For this reason, when the Al film 13 is removed, the probability of occurrence of a problem that the Al film 13 cannot be sufficiently removed due to a part of the SiO 2 film 6 being formed on the side wall 23 of the Al film 13 is increased. Can be reduced. For this reason, it is possible to reduce the probability of occurrence of malfunction of the semiconductor element due to the above problems. As a result, an increase in manufacturing cost due to a decrease in manufacturing yield of semiconductor elements can be suppressed.
- the mask layer 14 is made of a material (SiO 2 ) whose etching rate by the mixed acid is smaller than the material (Al) constituting the Al film 13, the Al film 13 is selectively etched with respect to the mask layer 14. Therefore, there is no need to perform additional processing such as heat treatment. Therefore, the number of manufacturing steps of the semiconductor element can be reduced as compared with the case where the additional processing as described above is performed. As a result, the manufacturing cost of the semiconductor element can be reduced.
- a lift-off method may be used in the step of forming the mask layer 14 as the second film (second film formation step (S30) and patterning step (S40)).
- the mask layer 14 having a predetermined pattern can be formed using a material that is difficult to etch. For this reason, the freedom degree of selection of the material used as the mask layer 14 can be enlarged.
- the material constituting the first film is aluminum.
- the material constituting the mask layer 14 may be at least one selected from the group consisting of silicon dioxide, silicon monoxide, silicon nitride, zirconium oxide, tantalum oxide, lanthanum oxide, cerium oxide, and hafnium oxide.
- the material constituting the protective film corresponding to the SiO 2 film 6 is a group consisting of silicon monoxide, silicon nitride, zirconium oxide, tantalum oxide, lanthanum oxide, cerium oxide, and hafnium oxide instead of the above-described silicon dioxide. It may be at least one selected from
- the first film corresponding to the Al film 3 is made of aluminum, which is a metal having a higher etching rate due to an alkaline etchant or mixed acid than the protective film using the mask layer 14 made of oxide and the SiO 2 film 6.
- the manufacturing method of the semiconductor element by this invention can be implemented reliably.
- the manufacturing method of the semiconductor element is after the first film formation step (S20) and before the second film formation step (S30). ) May be further provided with a step of forming a coating film (Au film 9 or Ti film 9) thereon. Further, in the method of manufacturing the semiconductor element, as shown in FIG. 17, the coating film (Au film 9 or Ti film 9) is partially formed so as to have the same pattern as that of the second film (mask layer 14). The process of removing may be further provided. As a result, an Au film 19 or a Ti film 19 having the same pattern as the mask layer 14 is formed as shown in FIG.
- the Au film 19 or the Ti film 19 as the coating film located on the Al film 3 is also removed.
- the step of partially removing the coating film may be performed continuously with the step of forming the ridge portion 12 as shown in FIG. Prior to the step of forming the portion 12, it may be performed continuously with the step of forming the second film having the pattern (continuously with the etching for forming the mask layer 14 in the patterning step (S40)). Good.
- the Al film 3 is formed by the step of forming the second film (SiO 2 film 4).
- the surface of the can be prevented from being damaged. For this reason, particularly in the case of a configuration in which the width of the ridge portion 12 is narrowed, if the surface of the Al film 3 is damaged (for example, irregularities are formed due to the second film forming step), the ridge portion 12 Since it becomes difficult to form the shape and size as designed, it is particularly effective to protect the surface of the Al film 3 by forming such an Au film 9 or Ti film 9.
- the present invention is particularly applicable to a method for manufacturing a semiconductor element in which a ridge portion is formed in a gallium nitride based semiconductor layer.
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Abstract
Description
図1は、本発明に従った化合物半導体素子の製造方法の実施の形態1を示すフローチャートである。図2~図11は、図1に示した化合物半導体素子の製造方法の各工程を説明するための断面模式図である。図1~図11を参照して、本発明による化合物半導体素子の製造方法を説明する。
形成する。この結果、図3に示すような構造を得る。このSiO2膜4は、たとえばCV
D(Chemical Vapor Deposition)法、EB(Electron Beam)蒸着法、スパッタ法などの任意の方法を用いて形成することができる。このSiO2膜4の厚みは、たとえば0.1
μm以上1μm以下とすることができる。ここで、SiO2膜4の厚みの下限を0.1μmとしたのは、凸部形成工程(S50)でのエッチング工程のときにSiO2膜4がエッチング終了時まで残存するための最低厚みが0.1μmであったためである。また、SiO2膜4の厚みの上限を1μmとしたのは、パターニング工程(S40)においてレジスト膜5が消失する前にSiO2膜4のパターニングを終了させることが可能な厚みの上限が1μmだからである。
図12は、本発明による化合物半導体素子の製造方法の実施の形態2を説明するための断面模式図である。図12を参照して、本発明による化合物半導体素子の製造方法の実施の形態2を説明する。
より、図5に示すような構造を得る。
本発明による化合物半導体素子の製造方法の実施の形態3は、基本的には図1~図11に示した本発明による化合物半導体素子の製造方法の実施の形態1と同様の構成を備えるが、第1の膜の側壁を後退させる工程(S60)およびリフトオフ工程(S80)において用いるエッチャントがアルカリ水溶液ではなく燐酸、硝酸、酢酸および水からなる混酸である点が異なっている。混酸として、たとえば燐酸を80質量%、硝酸を5質量%、酢酸を10質量%、残部を水とした組成の混酸を用いることができる。このようにしても、本発明の実施の形態1と同様の効果を得ることができる。
図13~図19は、本発明による化合物半導体素子の製造方法の実施の形態4を説明するための断面模式図である。図13~図19を参照して、本発明による化合物半導体素子の製造方法の実施の形態4を説明する。
Claims (8)
- 半導体素子を構成する窒化ガリウム系半導体層を準備する工程と、
前記窒化ガリウム系半導体層上に第1の膜を形成する工程と、
アルカリ系エッチャントによるエッチング速度が、前記第1の膜を構成する材料より小さい材料からなり、パターンを有する第2の膜を形成する工程と、
前記第2の膜をマスクとして用いて、前記第1の膜および前記窒化ガリウム系半導体層を部分的にエッチングにより除去することにより、前記第2の膜の下に位置する領域において前記窒化ガリウム系半導体層にリッジ部を形成する工程と、
前記リッジ部上に位置する前記第1の膜の端部を、前記アルカリ系エッチャントを用いたエッチングにより除去することにより、前記第1の膜の端面の位置を前記第2の膜の端面の位置より後退させる工程と、
前記アルカリ系エッチャントによるエッチング速度が、前記第1の膜を構成する材料より小さい材料からなる保護膜を、前記リッジ部の側面および前記第2の膜の上部表面上に形成する工程と、
前記第1の膜を前記アルカリ系エッチャントを用いたエッチングにより除去することにより、前記第2の膜および前記第2の膜の上部表面上に形成された前記保護膜の部分を除去する工程と、
前記第1の膜を除去することにより露出した前記リッジ部の表面に電極を形成する工程とを備える、半導体素子の製造方法。 - 半導体素子を構成する窒化ガリウム系半導体層を準備する工程と、
前記窒化ガリウム系半導体層上に第1の膜を形成する工程と、
燐酸、硝酸、酢酸および水からなる混酸によるエッチング速度が、前記第1の膜を構成する材料より小さい材料からなり、パターンを有する第2の膜を形成する工程と、
前記第2の膜をマスクとして用いて、前記第1の膜および前記窒化ガリウム系半導体層を部分的にエッチングにより除去することにより、前記第2の膜の下に位置する領域において前記窒化ガリウム系半導体層にリッジ部を形成する工程と、
前記リッジ部上に位置する前記第1の膜の端部を、前記混酸を用いたエッチングにより除去することにより、前記第1の膜の端面の位置を前記第2の膜の端面の位置より後退させる工程と、
前記混酸によるエッチング速度が、前記第1の膜を構成する材料より小さい材料からなる保護膜を、前記リッジ部の側面および前記第2の膜の上部表面上に形成する工程と、
前記第1の膜を前記混酸を用いたエッチングにより除去することにより、前記第2の膜および前記第2の膜の上部表面上に形成された前記保護膜の部分を除去する工程と、
前記第1の膜を除去することにより露出した前記リッジ部の表面に電極を形成する工程とを備える、半導体素子の製造方法。 - 前記第2の膜を形成する工程ではリフトオフ法を用いる、請求項1または2に記載の半導体素子の製造方法。
- 前記第1の膜を構成する材料はアルミニウムである、請求項1~3のいずれか1項に記載の半導体素子の製造方法。
- 前記第1の膜を形成する工程の後であって、前記第2の膜を形成する工程の前に、前記第1の膜上に被覆膜を形成する工程と、
前記第2の膜のパターンと同様のパターンを有するように前記被覆膜を部分的に除去する工程とをさらに備え、
前記保護膜の部分を除去する工程では、前記第1の膜上に位置する前記被覆膜も除去される、請求項1~4のいずれか1項に記載の半導体素子の製造方法。 - 前記被覆膜を構成する材料は金またはチタンである、請求項5に記載の半導体素子の製造方法。
- 前記第2の膜を構成する材料は、二酸化珪素、一酸化珪素、窒化珪素、酸化ジルコニウム、酸化タンタル、酸化ランタン、酸化セリウム、および酸化ハフニウムからなる群から選択される少なくとも1種である、請求項1~6のいずれか1項に記載の半導体素子の製造方法。
- 前記保護膜を構成する材料は、二酸化珪素、一酸化珪素、窒化珪素、酸化ジルコニウム、酸化タンタル、酸化ランタン、酸化セリウム、および酸化ハフニウムからなる群から選択される少なくとも1種である、請求項1~7のいずれか1項に記載の半導体素子の製造方法。
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JP5381632B2 (ja) * | 2009-11-13 | 2014-01-08 | 住友電気工業株式会社 | Iii族窒化物半導体発光素子を作製する方法、iii族窒化物半導体素子のための電極を形成する方法 |
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CN103701037B (zh) * | 2013-11-27 | 2016-03-23 | 中国科学院半导体研究所 | 氮化镓激光器腔面的制作方法 |
JP2015195332A (ja) * | 2014-03-27 | 2015-11-05 | 株式会社東芝 | 半導体発光装置及びその製造方法 |
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CN101681828A (zh) | 2010-03-24 |
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JP2009076867A (ja) | 2009-04-09 |
US20110129997A1 (en) | 2011-06-02 |
US20100120231A1 (en) | 2010-05-13 |
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