WO2009075315A1 - 記憶装置および情報再記録方法 - Google Patents

記憶装置および情報再記録方法 Download PDF

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Publication number
WO2009075315A1
WO2009075315A1 PCT/JP2008/072488 JP2008072488W WO2009075315A1 WO 2009075315 A1 WO2009075315 A1 WO 2009075315A1 JP 2008072488 W JP2008072488 W JP 2008072488W WO 2009075315 A1 WO2009075315 A1 WO 2009075315A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
voltage
supplied
reduced
storage device
Prior art date
Application number
PCT/JP2008/072488
Other languages
English (en)
French (fr)
Inventor
Tsunenori Shiimoto
Tomohito Tsushima
Shuichiro Yasuda
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Priority to CN200880119293.8A priority Critical patent/CN101889311B/zh
Priority to US12/747,832 priority patent/US8369128B2/en
Publication of WO2009075315A1 publication Critical patent/WO2009075315A1/ja

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0071—Write using write potential applied to access device gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

　制御を要する電圧を減らし、周辺回路規模を小さくすることのできる記憶装置を提供する。可変抵抗素子１０の電極１１にはビット線ＢＬＲを介して第１電源２１より第１パルス電圧（ＶＢＬＲ）、トランジスタ２０の制御端子２０ｃにはワード線ＷＬを介して第２電源２２よりセル選択用の第２パルス電圧（ＶＷＬ）、トランジスタ２０の第２入出力端子２０ｂにはビット線ＢＬＴを介して第３電源２３より第３パルス電圧（ＶＢＬＴ）がそれぞれ供給される。情報の再書き込み時において、調整回路２４により第３電源２３の電圧値（ＶＢＬＴ）を調整することにより、セル電圧およびセル電流を変更（減少または増加）する。
PCT/JP2008/072488 2007-12-12 2008-12-11 記憶装置および情報再記録方法 WO2009075315A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN200880119293.8A CN101889311B (zh) 2007-12-12 2008-12-11 存储装置及信息再记录方法
US12/747,832 US8369128B2 (en) 2007-12-12 2008-12-11 Storage device and information rerecording method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007320578A JP2009146478A (ja) 2007-12-12 2007-12-12 記憶装置および情報再記録方法
JP2007-320578 2007-12-12

Publications (1)

Publication Number Publication Date
WO2009075315A1 true WO2009075315A1 (ja) 2009-06-18

Family

ID=40755555

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/072488 WO2009075315A1 (ja) 2007-12-12 2008-12-11 記憶装置および情報再記録方法

Country Status (6)

Country Link
US (1) US8369128B2 (ja)
JP (1) JP2009146478A (ja)
KR (1) KR20100097678A (ja)
CN (1) CN101889311B (ja)
TW (1) TWI400706B (ja)
WO (1) WO2009075315A1 (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4635235B2 (ja) * 2008-10-30 2011-02-23 独立行政法人産業技術総合研究所 固体メモリ
JP4846813B2 (ja) * 2009-03-12 2011-12-28 株式会社東芝 不揮発性半導体記憶装置
JP5604844B2 (ja) * 2009-10-02 2014-10-15 日本電気株式会社 記憶装置、及び記憶装置の動作方法
JP5418147B2 (ja) * 2009-10-26 2014-02-19 日本電気株式会社 素子制御回路、スイッチング素子及び素子制御方法
US8921821B2 (en) 2013-01-10 2014-12-30 Micron Technology, Inc. Memory cells
JP5830655B2 (ja) * 2013-04-30 2015-12-09 パナソニックＩｐマネジメント株式会社 不揮発性記憶素子の駆動方法
WO2017150028A1 (ja) * 2016-02-29 2017-09-08 ソニー株式会社 半導体回路、半導体回路の駆動方法、および電子機器
CN108962313A (zh) * 2017-05-23 2018-12-07 旺宏电子股份有限公司 存储器操作方法及存储器操作装置
CN109271742B (zh) * 2018-10-29 2022-11-08 成都师范学院 磁控忆阶元

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004185755A (ja) * 2002-12-05 2004-07-02 Sharp Corp 不揮発性半導体記憶装置
JP2004185723A (ja) * 2002-12-03 2004-07-02 Sharp Corp 半導体記憶装置およびそのデータ書き込み制御方法
JP2006202411A (ja) * 2005-01-20 2006-08-03 Sharp Corp 不揮発性半導体記憶装置及びその制御方法
JP2007018615A (ja) * 2005-07-08 2007-01-25 Sony Corp 記憶装置及び半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909633B2 (en) 2002-12-09 2005-06-21 Applied Spintronics Technology, Inc. MRAM architecture with a flux closed data storage layer
JP4113493B2 (ja) * 2003-06-12 2008-07-09 シャープ株式会社 不揮発性半導体記憶装置及びその制御方法
JP4475174B2 (ja) * 2005-06-09 2010-06-09 ソニー株式会社 記憶装置
KR20070075812A (ko) * 2006-01-16 2007-07-24 삼성전자주식회사 스토리지 노드에 비정질 고체 전해질층을 포함하는 저항성메모리 소자

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004185723A (ja) * 2002-12-03 2004-07-02 Sharp Corp 半導体記憶装置およびそのデータ書き込み制御方法
JP2004185755A (ja) * 2002-12-05 2004-07-02 Sharp Corp 不揮発性半導体記憶装置
JP2006202411A (ja) * 2005-01-20 2006-08-03 Sharp Corp 不揮発性半導体記憶装置及びその制御方法
JP2007018615A (ja) * 2005-07-08 2007-01-25 Sony Corp 記憶装置及び半導体装置

Also Published As

Publication number Publication date
US20110149635A1 (en) 2011-06-23
KR20100097678A (ko) 2010-09-03
TW200943297A (en) 2009-10-16
JP2009146478A (ja) 2009-07-02
CN101889311B (zh) 2013-07-24
US8369128B2 (en) 2013-02-05
CN101889311A (zh) 2010-11-17
TWI400706B (zh) 2013-07-01

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