WO2008153082A1 - 樹脂組成物、埋め込み材、絶縁層および半導体装置 - Google Patents

樹脂組成物、埋め込み材、絶縁層および半導体装置 Download PDF

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Publication number
WO2008153082A1
WO2008153082A1 PCT/JP2008/060713 JP2008060713W WO2008153082A1 WO 2008153082 A1 WO2008153082 A1 WO 2008153082A1 JP 2008060713 W JP2008060713 W JP 2008060713W WO 2008153082 A1 WO2008153082 A1 WO 2008153082A1
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Prior art keywords
resin composition
resin
insulating layer
embedding
embedding material
Prior art date
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PCT/JP2008/060713
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English (en)
French (fr)
Inventor
Toyosei Takahashi
Rie Takayama
Hirohisa Dejima
Junya Kusunoki
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Sumitomo Bakelite Company Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Company Limited filed Critical Sumitomo Bakelite Company Limited
Priority to CN200880019806.8A priority Critical patent/CN101679721A/zh
Priority to US12/664,003 priority patent/US7999354B2/en
Priority to JP2009519293A priority patent/JPWO2008153082A1/ja
Priority to EP08765484A priority patent/EP2166036A4/en
Publication of WO2008153082A1 publication Critical patent/WO2008153082A1/ja

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    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L63/00—Compositions of epoxy resins; Compositions of derivatives of epoxy resins
    • C08L63/10—Epoxy resins modified by unsaturated compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Organic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Polymers & Plastics (AREA)
  • Medicinal Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Macromonomer-Based Addition Polymer (AREA)
  • Materials For Photolithography (AREA)
  • Polymerisation Methods In General (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Phenolic Resins Or Amino Resins (AREA)
  • Laminated Bodies (AREA)

Abstract

　本発明の樹脂組成物は、板厚方向に貫通し、内部に導体部が設けられた貫通孔を有する半導体基板の少なくとも前記貫通孔を埋め込むための埋め込み材に用いる樹脂組成物であって、前記樹脂組成物が、ラジカル重合性二重結合を有する樹脂と、熱硬化性樹脂と、アルカリ可溶性基および二重結合を有する樹脂とを含むもの、環状オレフィン系樹脂を含むもの、または、これらの混合物である。本発明の埋め込み材は、上記に記載の樹脂組成物の硬化物で構成されている。本発明の絶縁層は、上記に記載の樹脂組成物の硬化物で構成され、前記半導体基板の機能面と反対側の面に配置された層状の絶縁部と、該絶縁部と一体的に形成され、前記貫通孔に埋め込まれた埋め込み部とを有する。本発明の半導体装置は、上記に記載の絶縁層を有する。
PCT/JP2008/060713 2007-06-12 2008-06-11 樹脂組成物、埋め込み材、絶縁層および半導体装置 WO2008153082A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN200880019806.8A CN101679721A (zh) 2007-06-12 2008-06-11 树脂组合物、填埋材料、绝缘层以及半导体装置
US12/664,003 US7999354B2 (en) 2007-06-12 2008-06-11 Resin composition, filling material, insulating layer and semiconductor device
JP2009519293A JPWO2008153082A1 (ja) 2007-06-12 2008-06-11 樹脂組成物、埋め込み材、絶縁層および半導体装置
EP08765484A EP2166036A4 (en) 2007-06-12 2008-06-11 RESIN COMPOSITION, COATING MATERIAL, INSULATING LAYER AND SEMICONDUCTOR DEVICE

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007155707 2007-06-12
JP2007-155707 2007-06-12
JP2008-108509 2008-04-18
JP2008108509 2008-04-18

Publications (1)

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WO2008153082A1 true WO2008153082A1 (ja) 2008-12-18

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PCT/JP2008/060713 WO2008153082A1 (ja) 2007-06-12 2008-06-11 樹脂組成物、埋め込み材、絶縁層および半導体装置

Country Status (7)

Country Link
US (1) US7999354B2 (ja)
EP (2) EP2166036A4 (ja)
JP (1) JPWO2008153082A1 (ja)
KR (1) KR20100037589A (ja)
CN (1) CN101679721A (ja)
TW (1) TW200908250A (ja)
WO (1) WO2008153082A1 (ja)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013038165A (ja) * 2011-08-05 2013-02-21 Fujikura Ltd 貫通配線付き接合基板
JP2014217016A (ja) * 2013-04-30 2014-11-17 株式会社ニコン 撮像ユニット、撮像装置及び電子デバイス
JP2016037545A (ja) * 2014-08-07 2016-03-22 パナソニックＩｐマネジメント株式会社 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ
JP2016037546A (ja) * 2014-08-07 2016-03-22 パナソニックＩｐマネジメント株式会社 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ
JP2019156909A (ja) * 2018-03-08 2019-09-19 味の素株式会社 樹脂組成物、シート状積層材料、プリント配線板及び半導体装置
JP2020195116A (ja) * 2019-05-30 2020-12-03 セイコーエプソン株式会社 振動デバイスおよび電子機器
WO2021033269A1 (ja) * 2019-08-20 2021-02-25 三菱電機株式会社 半導体パッケージ
JP2022031285A (ja) * 2018-03-08 2022-02-18 味の素株式会社 樹脂組成物、シート状積層材料、プリント配線板及び半導体装置

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US20120305295A1 (en) * 2010-02-03 2012-12-06 Showa Denko K.K. Thermosetting composition
US8823186B2 (en) 2010-12-27 2014-09-02 Shin-Etsu Chemical Co., Ltd. Fiber-containing resin substrate, sealed substrate having semiconductor device mounted thereon, sealed wafer having semiconductor device formed thereon, a semiconductor apparatus, and method for manufacturing semiconductor apparatus
DE102011100608B4 (de) * 2011-03-03 2024-03-28 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Suspension zum Schutz eines Halbleitermaterials und Verfahren zur Herstellung eines Halbleiterkörpers
US20130015504A1 (en) * 2011-07-11 2013-01-17 Chien-Li Kuo Tsv structure and method for forming the same
CN103946326A (zh) * 2011-11-18 2014-07-23 旭硝子株式会社 固化性组合物、涂布用组合物、固化膜、激光加工方法及多层布线结构体的制造方法
JP6065845B2 (ja) * 2012-01-31 2017-01-25 三菱瓦斯化学株式会社 プリント配線板材料用樹脂組成物、並びにそれを用いたプリプレグ、樹脂シート、金属箔張積層板及びプリント配線板
JP2015039133A (ja) * 2013-08-19 2015-02-26 日本特殊陶業株式会社 パッケージ
KR102086766B1 (ko) 2016-07-29 2020-03-09 주식회사 엘지화학 고리형 올레핀계 공중합체 및 이의 제조 방법
US10741477B2 (en) * 2018-03-23 2020-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of forming the same
WO2020015665A1 (zh) * 2018-07-19 2020-01-23 东丽先端材料研究开发（中国）有限公司 一种半导体器件及太阳能电池
US11639398B2 (en) * 2019-12-30 2023-05-02 Rohm And Haas Electronic Materials Llc Photosensitive bismaleimide composition
JP2023537612A (ja) * 2020-08-14 2023-09-04 ブルーワー サイエンス アイ エヌ シー． 持続的接合及びパターニングの材料

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See also references of EP2166036A4

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013038165A (ja) * 2011-08-05 2013-02-21 Fujikura Ltd 貫通配線付き接合基板
JP2014217016A (ja) * 2013-04-30 2014-11-17 株式会社ニコン 撮像ユニット、撮像装置及び電子デバイス
JP2016037545A (ja) * 2014-08-07 2016-03-22 パナソニックＩｐマネジメント株式会社 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ
JP2016037546A (ja) * 2014-08-07 2016-03-22 パナソニックＩｐマネジメント株式会社 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ
JP2019156909A (ja) * 2018-03-08 2019-09-19 味の素株式会社 樹脂組成物、シート状積層材料、プリント配線板及び半導体装置
JP2022031285A (ja) * 2018-03-08 2022-02-18 味の素株式会社 樹脂組成物、シート状積層材料、プリント配線板及び半導体装置
JP7272405B2 (ja) 2018-03-08 2023-05-12 味の素株式会社 樹脂組成物、シート状積層材料、プリント配線板及び半導体装置
JP2020195116A (ja) * 2019-05-30 2020-12-03 セイコーエプソン株式会社 振動デバイスおよび電子機器
JP7287116B2 (ja) 2019-05-30 2023-06-06 セイコーエプソン株式会社 振動デバイスおよび電子機器
WO2021033269A1 (ja) * 2019-08-20 2021-02-25 三菱電機株式会社 半導体パッケージ
JPWO2021033269A1 (ja) * 2019-08-20 2021-02-25
JP7176641B2 (ja) 2019-08-20 2022-11-22 三菱電機株式会社 半導体パッケージ

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JPWO2008153082A1 (ja) 2010-08-26
US7999354B2 (en) 2011-08-16
EP2477215A2 (en) 2012-07-18
EP2166036A1 (en) 2010-03-24
CN101679721A (zh) 2010-03-24
TW200908250A (en) 2009-02-16
KR20100037589A (ko) 2010-04-09
EP2166036A4 (en) 2011-10-19
US20100181684A1 (en) 2010-07-22
EP2477215A3 (en) 2013-08-14

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