WO2008146760A1 - 記憶素子及びその読み出し方法 - Google Patents

記憶素子及びその読み出し方法 Download PDF

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Publication number
WO2008146760A1
WO2008146760A1 PCT/JP2008/059592 JP2008059592W WO2008146760A1 WO 2008146760 A1 WO2008146760 A1 WO 2008146760A1 JP 2008059592 W JP2008059592 W JP 2008059592W WO 2008146760 A1 WO2008146760 A1 WO 2008146760A1
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section
memory means
memory device
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PCT/JP2008/059592
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English (en)
French (fr)
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Yutaka Hayashi
Kazuhiko Matsumoto
Takashi Uemura
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National Institute Of Advanced Industrial Science And Technology
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Priority to EP08764638.6A priority Critical patent/EP2166571B1/en
Priority to CN2008800217764A priority patent/CN101689547B/zh
Priority to US12/601,788 priority patent/US8223548B2/en
Priority to JP2009516309A priority patent/JP5196500B2/ja
Publication of WO2008146760A1 publication Critical patent/WO2008146760A1/ja

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    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

　記憶素子（１）は、長さと第１表面と第１表面に囲まれた断面とを有する第１の半導体領域（１００）と、第１表面上に設けられた記憶手段（３００）と、記憶手段（３００）上に設けられたゲート（４００）と、から少なくとも構成され、第１の半導体領域（１００）の断面の等価断面半径を、記憶手段（３００）の等価酸化シリコン膜厚以下とすることにより低プログラム電圧を実現する。断面の等価断面半径ｒを１０ｎｍ以下、ゲート長を２０ｎｍ以下とすることにより、ゲート電圧換算の多値レベル間隔を室温で認識できる固有値とする。
PCT/JP2008/059592 2007-05-24 2008-05-23 記憶素子及びその読み出し方法 WO2008146760A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP08764638.6A EP2166571B1 (en) 2007-05-24 2008-05-23 Memory device and its reading method
CN2008800217764A CN101689547B (zh) 2007-05-24 2008-05-23 存储元件及其读取方法
US12/601,788 US8223548B2 (en) 2007-05-24 2008-05-23 Memory device with reduced programming voltage method of reduction of programming voltage and method of reading such memory device
JP2009516309A JP5196500B2 (ja) 2007-05-24 2008-05-23 記憶素子及びその読み出し方法

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Application Number Priority Date Filing Date Title
JP2007-138470 2007-05-24
JP2007138470 2007-05-24

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WO2008146760A1 true WO2008146760A1 (ja) 2008-12-04

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US (1) US8223548B2 (ja)
EP (1) EP2166571B1 (ja)
JP (1) JP5196500B2 (ja)
KR (1) KR101342476B1 (ja)
CN (1) CN101689547B (ja)
WO (1) WO2008146760A1 (ja)

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JP6547702B2 (ja) * 2016-07-26 2019-07-24 信越半導体株式会社 半導体装置の製造方法及び半導体装置の評価方法
US10276697B1 (en) * 2017-10-27 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance FET with improved reliability performance
TWI738202B (zh) 2019-06-03 2021-09-01 旺宏電子股份有限公司 三維快閃記憶體及其陣列佈局
US11088246B2 (en) * 2019-07-18 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a field effect transistor using carbon nanotubes and a field effect transistor
US11165032B2 (en) * 2019-09-05 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistor using carbon nanotubes
US11133329B2 (en) 2019-09-09 2021-09-28 Macronix International Co., Ltd. 3D and flash memory architecture with FeFET
CN112272870B (zh) * 2020-03-19 2024-04-02 厦门三安光电有限公司 发光二极管

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Publication number Publication date
JP5196500B2 (ja) 2013-05-15
KR101342476B1 (ko) 2013-12-17
JPWO2008146760A1 (ja) 2010-08-19
US20100208522A1 (en) 2010-08-19
EP2166571B1 (en) 2017-08-30
CN101689547B (zh) 2012-06-27
KR20100018557A (ko) 2010-02-17
CN101689547A (zh) 2010-03-31
US8223548B2 (en) 2012-07-17
EP2166571A1 (en) 2010-03-24
EP2166571A4 (en) 2010-09-29

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