WO2008123213A1 - 半導体装置及び半導体製造方法 - Google Patents

半導体装置及び半導体製造方法 Download PDF

Info

Publication number
WO2008123213A1
WO2008123213A1 PCT/JP2008/055488 JP2008055488W WO2008123213A1 WO 2008123213 A1 WO2008123213 A1 WO 2008123213A1 JP 2008055488 W JP2008055488 W JP 2008055488W WO 2008123213 A1 WO2008123213 A1 WO 2008123213A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
sic
grown
polarity
semiconductor
Prior art date
Application number
PCT/JP2008/055488
Other languages
English (en)
French (fr)
Inventor
Jun Suda
Tsunenobu Kimoto
Original Assignee
Kyoto University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyoto University filed Critical Kyoto University
Priority to US12/450,424 priority Critical patent/US20100072485A1/en
Priority to JP2009509104A priority patent/JPWO2008123213A1/ja
Publication of WO2008123213A1 publication Critical patent/WO2008123213A1/ja

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00Nanooptics, e.g. quantum optics or photonic crystals
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/35Non-linear optics
    • G02F1/355Non-linear optics characterised by the materials used
    • G02F1/3556Semiconductor materials, e.g. quantum wells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/35Non-linear optics
    • G02F1/355Non-linear optics characterised by the materials used
    • G02F1/3558Poled materials, e.g. with periodic poling; Fabrication of domain inverted structures, e.g. for quasi-phase-matching [QPM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/02447Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02502Layer structure consisting of two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/02554Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00Materials and properties
    • G02F2202/10Materials and properties semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Biophysics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

Si極性面のSiで終端されたSiC表面1aにSi原子3を1原子層成長し、さらにC原子5を1原子層だけ成長する。その後は、SiとCとを供給しSiC層を形成する。この際に成長したSiC層の表面は、Si極性面とは反対のC極性面となる。すなわち、上記の工程によれば、Si極性のSiC層1上に1原子層のSi中間層bを挟んで極性が反転したC極性のSiC層1xを成長することができる。これによりSiCの極性を表面において反転させる技術を提供することが可能になる。
PCT/JP2008/055488 2007-03-26 2008-03-25 半導体装置及び半導体製造方法 WO2008123213A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/450,424 US20100072485A1 (en) 2007-03-26 2008-03-25 Semiconductor device and semiconductor manufacturing method
JP2009509104A JPWO2008123213A1 (ja) 2007-03-26 2008-03-25 半導体装置及び半導体製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-080243 2007-03-26
JP2007080243 2007-03-26

Publications (1)

Publication Number Publication Date
WO2008123213A1 true WO2008123213A1 (ja) 2008-10-16

Family

ID=39830708

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/055488 WO2008123213A1 (ja) 2007-03-26 2008-03-25 半導体装置及び半導体製造方法

Country Status (3)

Country Link
US (1) US20100072485A1 (ja)
JP (1) JPWO2008123213A1 (ja)
WO (1) WO2008123213A1 (ja)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263011A (ja) * 2009-04-30 2010-11-18 Fujitsu Ltd 化合物半導体装置及びその製造方法
JP2011003652A (ja) * 2009-06-17 2011-01-06 Fujitsu Ltd 半導体装置及びその製造方法
JP2012041204A (ja) * 2010-08-13 2012-03-01 Seiko Epson Corp 立方晶炭化ケイ素膜の製造方法及び立方晶炭化ケイ素膜付き基板の製造方法
JP2012054352A (ja) * 2010-08-31 2012-03-15 Fujitsu Ltd 化合物半導体装置及びその製造方法
WO2013038980A1 (ja) * 2011-09-15 2013-03-21 シャープ株式会社 窒化物半導体層を成長させるためのバッファ層構造を有する基板
JP2013069878A (ja) * 2011-09-22 2013-04-18 Sharp Corp 窒化物半導体層を成長させるためのバッファ層構造を有する基板
JP2015146450A (ja) * 2015-04-03 2015-08-13 株式会社東芝 半導体素子
JP2015526902A (ja) * 2012-07-25 2015-09-10 レイセオン カンパニー 複数の装置を集積するモノリシック集積回路チップ
JP2016134609A (ja) * 2015-01-22 2016-07-25 富士通株式会社 化合物半導体装置及びその製造方法
US9748343B2 (en) 2015-07-29 2017-08-29 Kabushiki Kaisha Toshiba Semiconductor device
US11276774B2 (en) 2019-01-04 2022-03-15 Kabushiki Kaisha Toshiba Semiconductor device, inverter circuit, driving device, vehicle, and elevator
US11276758B2 (en) 2019-01-04 2022-03-15 Kabushiki Kaisha Toshiba Semiconductor device, inverter circuit, driving device, vehicle, and elevator having a reduced on-resistance with a silicon carbide layer

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130031598A (ko) * 2011-09-21 2013-03-29 한국전자통신연구원 광 도파로
KR20130076314A (ko) * 2011-12-28 2013-07-08 삼성전자주식회사 파워소자 및 이의 제조방법
US8575657B2 (en) 2012-03-20 2013-11-05 Northrop Grumman Systems Corporation Direct growth of diamond in backside vias for GaN HEMT devices
US9166068B2 (en) * 2012-05-03 2015-10-20 The United States Of America As Represented By The Secretary Of The Army Semiconductor heterobarrier electron device and method of making
JP6149931B2 (ja) * 2013-07-09 2017-06-21 富士電機株式会社 炭化珪素半導体装置の製造方法および炭化珪素半導体装置
JP2015126024A (ja) * 2013-12-25 2015-07-06 株式会社豊田自動織機 半導体基板および半導体基板の製造方法
US10928329B2 (en) * 2017-10-11 2021-02-23 Board Of Regents, The University Of Texas System Method and system for optically detecting and characterizing defects in semiconductors
JP7016311B2 (ja) 2018-11-06 2022-02-04 株式会社東芝 半導体装置
JP7269190B2 (ja) * 2020-02-27 2023-05-08 株式会社東芝 窒化物結晶、光学装置、半導体装置、窒化物結晶の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11504139A (ja) * 1996-02-16 1999-04-06 ベル コミュニケーションズ リサーチ,インコーポレイテッド ウェーハ結合により達成された異なる結晶学的配列を有する非線形光導波路
JP2004140339A (ja) * 2002-09-25 2004-05-13 Univ Chiba 窒化物系ヘテロ構造を有するデバイス及びその製造方法
JP2004259738A (ja) * 2003-02-24 2004-09-16 Sharp Corp 窒化物系iii−v族化合物半導体の製造方法およびそれを含む半導体装置
WO2006114999A1 (ja) * 2005-04-18 2006-11-02 Kyoto University 化合物半導体装置及び化合物半導体製造方法
JP2007272063A (ja) * 2006-03-31 2007-10-18 Furukawa Electric Co Ltd:The 波長変換素の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1237272A (zh) * 1997-08-27 1999-12-01 松下电器产业株式会社 碳化硅衬底及其制造方法以及使用碳化硅衬底的半导体元件
US6488771B1 (en) * 2001-09-25 2002-12-03 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method for growing low-defect single crystal heteroepitaxial films
JP2005011915A (ja) * 2003-06-18 2005-01-13 Hitachi Ltd 半導体装置、半導体回路モジュールおよびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11504139A (ja) * 1996-02-16 1999-04-06 ベル コミュニケーションズ リサーチ,インコーポレイテッド ウェーハ結合により達成された異なる結晶学的配列を有する非線形光導波路
JP2004140339A (ja) * 2002-09-25 2004-05-13 Univ Chiba 窒化物系ヘテロ構造を有するデバイス及びその製造方法
JP2004259738A (ja) * 2003-02-24 2004-09-16 Sharp Corp 窒化物系iii−v族化合物半導体の製造方法およびそれを含む半導体装置
WO2006114999A1 (ja) * 2005-04-18 2006-11-02 Kyoto University 化合物半導体装置及び化合物半導体製造方法
JP2007272063A (ja) * 2006-03-31 2007-10-18 Furukawa Electric Co Ltd:The 波長変換素の製造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263011A (ja) * 2009-04-30 2010-11-18 Fujitsu Ltd 化合物半導体装置及びその製造方法
JP2011003652A (ja) * 2009-06-17 2011-01-06 Fujitsu Ltd 半導体装置及びその製造方法
JP2012041204A (ja) * 2010-08-13 2012-03-01 Seiko Epson Corp 立方晶炭化ケイ素膜の製造方法及び立方晶炭化ケイ素膜付き基板の製造方法
JP2012054352A (ja) * 2010-08-31 2012-03-15 Fujitsu Ltd 化合物半導体装置及びその製造方法
WO2013038980A1 (ja) * 2011-09-15 2013-03-21 シャープ株式会社 窒化物半導体層を成長させるためのバッファ層構造を有する基板
JP2013069878A (ja) * 2011-09-22 2013-04-18 Sharp Corp 窒化物半導体層を成長させるためのバッファ層構造を有する基板
JP2015526902A (ja) * 2012-07-25 2015-09-10 レイセオン カンパニー 複数の装置を集積するモノリシック集積回路チップ
JP2016134609A (ja) * 2015-01-22 2016-07-25 富士通株式会社 化合物半導体装置及びその製造方法
JP2015146450A (ja) * 2015-04-03 2015-08-13 株式会社東芝 半導体素子
US9748343B2 (en) 2015-07-29 2017-08-29 Kabushiki Kaisha Toshiba Semiconductor device
US11276774B2 (en) 2019-01-04 2022-03-15 Kabushiki Kaisha Toshiba Semiconductor device, inverter circuit, driving device, vehicle, and elevator
US11276758B2 (en) 2019-01-04 2022-03-15 Kabushiki Kaisha Toshiba Semiconductor device, inverter circuit, driving device, vehicle, and elevator having a reduced on-resistance with a silicon carbide layer

Also Published As

Publication number Publication date
JPWO2008123213A1 (ja) 2010-07-15
US20100072485A1 (en) 2010-03-25

Similar Documents

Publication Publication Date Title
WO2008123213A1 (ja) 半導体装置及び半導体製造方法
WO2007124209A3 (en) Stressor integration and method thereof
TW200633022A (en) Method of manufacturing an epitaxial semiconductor substrate and method of manufacturing a semiconductor device
TWI263709B (en) Structure of strain relaxed thin Si/Ge epitaxial layer and fabricating method thereof
WO2007025062A3 (en) Photovoltaic template
WO2009059128A3 (en) Crystalline-thin-film photovoltaic structures and methods for forming the same
TW200710927A (en) Compound semiconductor device and method of manufacturing the compound semiconductor device
TW200703716A (en) Nitride semiconductor element and its fabrication process
WO2010151857A3 (en) Method for forming iii-v semiconductor structures including aluminum-silicon nitride passivation
MY147106A (en) Method for manufacturing epitaxial wafer
PT1745165E (pt) Método para produzir substratos virtuais de ge para integração de iii/v sobre si(001)
TW200741043A (en) GaN crystal substrate and method of manufacturing the same, and method of manufacturing semiconductor device
TW200701335A (en) Nitride semiconductor device and manufacturing mathod thereof
WO2009063844A1 (ja) 半導体素子ならびに半導体素子製造法
WO2010025218A3 (en) Composite semiconductor substrates for thin-film device layer transfer
WO2007024186A3 (en) Interconnects and heat dissipators based on nanostructures
WO2009137556A3 (en) Group iii nitride templates and related heterostructures, devices, and methods for making them
WO2008152945A1 (ja) 半導体発光装置及びその製造方法
TW200612204A (en) Silicon rich dielectric antireflective coating
WO2007076250A3 (en) Semiconductor device fabricated using sublimation
WO2010059419A3 (en) Method of forming a semiconductor layer
WO2004012243A3 (en) Selective placement of dislocation arrays
EP1850373A3 (en) Method of forming highly orientated silicon film, method of manufacturing three-dimensional semiconductor device, and three-dimensional semiconductor device
WO2010029656A3 (en) Mems device and method for manufacturing the same
EP2053645A3 (en) Method for manufacturing semiconductor substrate

Legal Events

Date Code Title Description
DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08722751

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009509104

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 12450424

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08722751

Country of ref document: EP

Kind code of ref document: A1