WO2008117509A1 - Ｓｏｉウエーハの製造方法 - Google Patents

Ｓｏｉウエーハの製造方法 Download PDF

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Publication number
WO2008117509A1
WO2008117509A1 PCT/JP2008/000339 JP2008000339W WO2008117509A1 WO 2008117509 A1 WO2008117509 A1 WO 2008117509A1 JP 2008000339 W JP2008000339 W JP 2008000339W WO 2008117509 A1 WO2008117509 A1 WO 2008117509A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
soi
base
bond
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/000339
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
Isao Yokokawa
Hiroshi Takeno
Nobuhiko Noto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of WO2008117509A1 publication Critical patent/WO2008117509A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
PCT/JP2008/000339 2007-03-26 2008-02-26 Ｓｏｉウエーハの製造方法 Ceased WO2008117509A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-080313 2007-03-26
JP2007080313A JP5194508B2 (ja) 2007-03-26 2007-03-26 Ｓｏｉウエーハの製造方法

Publications (1)

Publication Number Publication Date
WO2008117509A1 true WO2008117509A1 (ja) 2008-10-02

Family

ID=39788251

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/000339 Ceased WO2008117509A1 (ja) 2007-03-26 2008-02-26 Ｓｏｉウエーハの製造方法

Country Status (2)

Country Link
JP (1) JP5194508B2 (enExample)
WO (1) WO2008117509A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2484506A (en) * 2010-10-13 2012-04-18 Univ Warwick Heterogrowth

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5643488B2 (ja) * 2009-04-28 2014-12-17 信越化学工業株式会社 低応力膜を備えたｓｏｉウェーハの製造方法
JP2011071193A (ja) * 2009-09-24 2011-04-07 Sumco Corp 貼合せｓｏｉウェーハ及びその製造方法
JP5978764B2 (ja) * 2012-05-24 2016-08-24 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP6186984B2 (ja) 2013-07-25 2017-08-30 三菱電機株式会社 半導体装置の製造方法
JP7334698B2 (ja) * 2020-09-11 2023-08-29 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
JP7380517B2 (ja) * 2020-10-21 2023-11-15 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01186612A (ja) * 1988-01-14 1989-07-26 Fujitsu Ltd 半導体基板の製造方法
JPH05217826A (ja) * 1992-01-31 1993-08-27 Canon Inc 半導体基体及びその作製方法
JPH0837286A (ja) * 1994-07-21 1996-02-06 Toshiba Microelectron Corp 半導体基板および半導体基板の製造方法
JPH098124A (ja) * 1995-06-15 1997-01-10 Nippondenso Co Ltd 絶縁分離基板及びその製造方法
JPH1032321A (ja) * 1995-12-30 1998-02-03 Hyundai Electron Ind Co Ltd Ｓｏｉ基板およびその製造方法
JPH10116897A (ja) * 1996-10-09 1998-05-06 Mitsubishi Materials Shilicon Corp 張り合わせ基板およびその製造方法
JP2000030996A (ja) * 1998-07-07 2000-01-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
WO2005022610A1 (ja) * 2003-09-01 2005-03-10 Sumco Corporation 貼り合わせウェーハの製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059704A (ja) * 2005-08-25 2007-03-08 Sumco Corp 貼合せ基板の製造方法及び貼合せ基板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01186612A (ja) * 1988-01-14 1989-07-26 Fujitsu Ltd 半導体基板の製造方法
JPH05217826A (ja) * 1992-01-31 1993-08-27 Canon Inc 半導体基体及びその作製方法
JPH0837286A (ja) * 1994-07-21 1996-02-06 Toshiba Microelectron Corp 半導体基板および半導体基板の製造方法
JPH098124A (ja) * 1995-06-15 1997-01-10 Nippondenso Co Ltd 絶縁分離基板及びその製造方法
JPH1032321A (ja) * 1995-12-30 1998-02-03 Hyundai Electron Ind Co Ltd Ｓｏｉ基板およびその製造方法
JPH10116897A (ja) * 1996-10-09 1998-05-06 Mitsubishi Materials Shilicon Corp 張り合わせ基板およびその製造方法
JP2000030996A (ja) * 1998-07-07 2000-01-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
WO2005022610A1 (ja) * 2003-09-01 2005-03-10 Sumco Corporation 貼り合わせウェーハの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2484506A (en) * 2010-10-13 2012-04-18 Univ Warwick Heterogrowth

Also Published As

Publication number Publication date
JP2008244019A (ja) 2008-10-09
JP5194508B2 (ja) 2013-05-08

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