WO2008117509A1 - Soi wafer manufacturing method - Google Patents

Soi wafer manufacturing method Download PDF

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Publication number
WO2008117509A1
WO2008117509A1 PCT/JP2008/000339 JP2008000339W WO2008117509A1 WO 2008117509 A1 WO2008117509 A1 WO 2008117509A1 JP 2008000339 W JP2008000339 W JP 2008000339W WO 2008117509 A1 WO2008117509 A1 WO 2008117509A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
soi
base
bond
forming
Prior art date
Application number
PCT/JP2008/000339
Other languages
French (fr)
Japanese (ja)
Inventor
Isao Yokokawa
Hiroshi Takeno
Nobuhiko Noto
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Publication of WO2008117509A1 publication Critical patent/WO2008117509A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

An SOI wafer manufacturing method includes a step of preparing a base wafer composed of a p+ silicon single crystal wafer, and a bond wafer composed of a silicon single crystal wafer containing a dopant at concentration lower than that in the base wafer; a step of forming a silicon film on a surface of the base wafer by thermal oxidation; a step of bonding the bond wafer and the base wafer by having the silicon oxide film in between; and a step of forming an SOI layer by thinning the bond wafer. The SOI wafer manufacturing method has a step of forming a diffusion preventing film on a surface of the bond wafer prior to the bonding step, and the thickness of the diffusion preventing film is made thinner than that of the silicon oxide film. Thus, an SOI wafer wherein the p-type dopant contained in the base wafer is prevented from mixing in the SOI layer and has a small warp is provided.
PCT/JP2008/000339 2007-03-26 2008-02-26 Soi wafer manufacturing method WO2008117509A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007080313A JP5194508B2 (en) 2007-03-26 2007-03-26 Manufacturing method of SOI wafer
JP2007-080313 2007-03-26

Publications (1)

Publication Number Publication Date
WO2008117509A1 true WO2008117509A1 (en) 2008-10-02

Family

ID=39788251

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/000339 WO2008117509A1 (en) 2007-03-26 2008-02-26 Soi wafer manufacturing method

Country Status (2)

Country Link
JP (1) JP5194508B2 (en)
WO (1) WO2008117509A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2484506A (en) * 2010-10-13 2012-04-18 Univ Warwick Heterogrowth

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5643488B2 (en) * 2009-04-28 2014-12-17 信越化学工業株式会社 Manufacturing method of SOI wafer having low stress film
JP2011071193A (en) * 2009-09-24 2011-04-07 Sumco Corp Lamination soi wafer and manufacturing method of the same
JP5978764B2 (en) * 2012-05-24 2016-08-24 信越半導体株式会社 Manufacturing method of SOI wafer
JP6186984B2 (en) 2013-07-25 2017-08-30 三菱電機株式会社 Manufacturing method of semiconductor device
JP7334698B2 (en) * 2020-09-11 2023-08-29 信越半導体株式会社 SOI WAFER MANUFACTURING METHOD AND SOI WAFER
JP7380517B2 (en) * 2020-10-21 2023-11-15 信越半導体株式会社 SOI wafer manufacturing method and SOI wafer

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01186612A (en) * 1988-01-14 1989-07-26 Fujitsu Ltd Manufacture of semiconductor substrate
JPH05217826A (en) * 1992-01-31 1993-08-27 Canon Inc Semiconductor base body and its manufacture
JPH0837286A (en) * 1994-07-21 1996-02-06 Toshiba Microelectron Corp Semiconductor substrate and manufacture thereof
JPH098124A (en) * 1995-06-15 1997-01-10 Nippondenso Co Ltd Insulation separation substrate and its manufacture
JPH1032321A (en) * 1995-12-30 1998-02-03 Hyundai Electron Ind Co Ltd Soi substrate and its manufacture
JPH10116897A (en) * 1996-10-09 1998-05-06 Mitsubishi Materials Shilicon Corp Laminated board and its manufacture
JP2000030996A (en) * 1998-07-07 2000-01-28 Shin Etsu Handotai Co Ltd Soi wafer and manufacture thereof
WO2005022610A1 (en) * 2003-09-01 2005-03-10 Sumco Corporation Method for manufacturing bonded wafer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059704A (en) * 2005-08-25 2007-03-08 Sumco Corp Method for manufacturing laminated board and laminated board

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01186612A (en) * 1988-01-14 1989-07-26 Fujitsu Ltd Manufacture of semiconductor substrate
JPH05217826A (en) * 1992-01-31 1993-08-27 Canon Inc Semiconductor base body and its manufacture
JPH0837286A (en) * 1994-07-21 1996-02-06 Toshiba Microelectron Corp Semiconductor substrate and manufacture thereof
JPH098124A (en) * 1995-06-15 1997-01-10 Nippondenso Co Ltd Insulation separation substrate and its manufacture
JPH1032321A (en) * 1995-12-30 1998-02-03 Hyundai Electron Ind Co Ltd Soi substrate and its manufacture
JPH10116897A (en) * 1996-10-09 1998-05-06 Mitsubishi Materials Shilicon Corp Laminated board and its manufacture
JP2000030996A (en) * 1998-07-07 2000-01-28 Shin Etsu Handotai Co Ltd Soi wafer and manufacture thereof
WO2005022610A1 (en) * 2003-09-01 2005-03-10 Sumco Corporation Method for manufacturing bonded wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2484506A (en) * 2010-10-13 2012-04-18 Univ Warwick Heterogrowth

Also Published As

Publication number Publication date
JP5194508B2 (en) 2013-05-08
JP2008244019A (en) 2008-10-09

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