Classifications

• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
  • C23F1/00—Etching metallic material by chemical means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
  • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
  • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
  • H01B13/00—Apparatus or processes specially adapted for manufacturing conductors or cables
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/3065—Plasma etching; Reactive-ion etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31105—Etching inorganic layers
  • H01L21/31111—Etching inorganic layers by chemical means
  • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
  • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/011—Manufacture or treatment of multistable switching devices
  • H10N70/061—Shaping switching materials
  • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/20—Multistable switching devices, e.g. memristors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/801—Constructional details of multistable switching devices
  • H10N70/821—Device geometry
  • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/801—Constructional details of multistable switching devices
  • H10N70/881—Switching materials
  • H10N70/883—Oxides or nitrides
  • H10N70/8833—Binary metal oxides, e.g. TaOx
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes

Definitions

• transition metals and transition metal compounds are difficult to etch since most common etchants produce non-volatile byproducts which remain on the etched surface. Therefore it would be highly desirable to have a new and improved method of plasma etching transition metal and transition metal compounds while simultaneously reducing defect levels significantly.
• a method of plasma etching comprises using a primary etchant of carbon monoxide gas to etch a transition metal oxide and form a volatile metal carbonyl by-product that can be efficiently removed during the plasma etch.
• the carbon monoxide is diluted with an inert gas, such as argon.
• the transition metal oxide is a thin film.
• the transition metal oxide is part of an electronic device structure being fabricated on a semiconductor substrate.
• a magnetic field is applied during etching.
• Carbonyl etch chemistry can be used without heating. • Cumulative time-at-temperature can be minimized.
• FIG. 1 is a scanning electron microscope (SEM) photograph of a top down view of a sputter etched nickel oxide structure showing excessive residue;
• FIG. 2 is an SEM photograph of an undesirable etch profile associated with etching a sandwiched transition metal oxide stack using a sputter etch process
• FIG. 3 is diagrammatic illustration of a portion of an integrated circuit with a sandwiched transition metal oxide stack similar to that shown in the photograph of FIG. 2; and
• FIG. 4 is a flowchart of a processing method which is in accordance with a preferred embodiment of the present invention.
• a method of plasma etching transition metals and transition metal compounds, including transition metal oxides, with carbon monoxide is disclosed.
• the following description is presented to enable any person skilled in the art to make and use the invention.
• specific nomenclature is set forth to provide a thorough understanding of the present invention.
• Descriptions of specific applications and methods are provided only as examples.
• Various modifications to the preferred embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention.
• the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and steps disclosed herein.
• FIG. 4 there is shown a flow chart of a plasma etching process 400 for etching a transition metal or transition metal compound, which method 400 is in accordance with a preferred embodiment of the present invention.
• the disclosed plasma etching method 400 results in a reaction between a primary etchant of carbon monoxide or carbon monoxide- based plasma and a transition metal or transition metal compound, which in turn, forms a volatile by-product of metal carbonyl, thereby promoting the quick and easy removal of metal carbonyl by-product by pumping it away from the plasma etcher as it is generated.
• transition metals and transition metal oxides such as nickel oxide.
• transition metals and transition metal oxides such as nickel oxide.
• nickel oxide there is very little information on plasma etching nickel oxide in the available literature.
• wet etching and sputter etching in a plasma tool there are some references to wet etching and sputter etching in a plasma tool; however, none of the prior art specifically addresses plasma etching nickel oxide or other transition metals or transition metal compounds.
• nickel oxide as well as other transition metals and transition metal compounds are difficult to etch since most of the common etchants produce non-volatile by- products, such as nickel fluoride and nickel chloride in the case of nickel or nickel oxide in a fluorine or chlorine based plasma respectively.
• the prior art has required a high sputter component to etch, which leaves unwanted and undesired by-products as well as residues. Illustrative examples of excessive residue and poor etch profiles are depicted in the SEM photographs of FIGS. 1 - 2.
• FIG. 1 is an SEM photograph showing a cross-section of an etched stack including a layer of nickel oxide between titanium nitride layers, showing a poor etch profile.
• the process begins in a plasma etcher (not shown) at a start step 402.
• a chamber within the plasma etcher is loaded at a loading step 404 with one or more wafers or some other appropriate substrate having at least a layer thereon of a transition metal or a transition metal compound to be patterned.
• a layer of a transition metal or transition metal compound deposited over the wafer or other suitable substrate can be patterned and etched using methods of the present invention.
• Any suitable transition metal can be used, including nickel, iron, cobalt, tungsten, molybdenum, manganese, and ruthenium.
• transition metal compounds can be patterned and etched, including oxides, nitrides, and suicides of suitable transition metals.
• the process advances to a stabilizing step 406, where the chamber is sealed and set to a relative low pressure to facilitate plasma etching.
• the stabilizing step which extends over a predetermined period of time, the gas sources connected to the chamber are allowed to flow into the chamber and to be pumped out and to stabilize at a given pressure set point.
• the gas sources allowed to flow into the chamber are a matter of choice depending upon the primary etchant desired and any additives that may be required.
• an RF power source is activated at an activation step 408 to strike the plasma to etch the wafers.
• the plasma is a carbon monoxide plasma, comprising carbon monoxide and any additives.
• simultaneous on-going events occur within the chamber: 1) a plasma etch is in process relative to the wafers, 2) a volatile by-product is generated due to a chemical reaction between the gases flowing into the chamber and the material being etched, and 3) volatile by-products of the etch process are evacuated from the chamber as they are generated. These simultaneous events continue for a sufficient period of time to complete the desired etch of the transition metal or transition metal compound. When the desired etch is accomplished, the process goes to an end step 410.
• a primary etchant of carbon monoxide gas hereinafter simply called CO
• CO carbon monoxide gas
• a primary benefit of using CO as a primary etchant is that it reacts with most transition metals and transition metal compounds to form metal carbonyls that are volatile or that have relatively low boiling points.
• gases such as passivant gases that produce by-products that stick to the chamber walls or to the side walls of the wafer (s) being etched are deliberately added and are an integral part of the gas flow into the chamber. The addition of such passivant gases is done either to control the etch profile on the individual wafers and/or to maintain a particular chamber condition. Particular passivant gases that facilitate this process will be described hereinafter in greater detail.
• etching While etching, it is necessary to ensure that the surface that is being etched stays free of residue while a passivating by-product sticks to the etched sidewalls. Ion assistance helps in ensuring that any passivating by-product does not stay on the surface being etched. Such ion assistance may be provided by added gases. This is important because if the passivating by-product stays on the surface being etched, it may cause the etch to stop or to be incomplete. In any event, by-products that stick to the sidewalls are removed in a subseguent conventional cleaning process that will not be described hereinafter in greater detail.
• the primary etchant which is carbon monoxide (CO) plasma and any required additives, facilitate the plasma etch of the wafers disposed within the chamber.
• CO carbon monoxide
• the term carbon monoxide based plasma will refer to a plasma which is largely carbon monoxide but which may include other additives.
• the CO reacts with the material to be etched (whether it be a transition metal or a transition metal compound, including oxides, nitrides and suicides) yielding a metal carbonyl by-product which is immediately evacuated from the chamber as quickly as it is formed.
• Additives that may be flowing with the CO can include either individually or in any combination such additives as reducing agents like H 2 and hydrofluorocarbons, passivants like N2 and fluorocarbons, and additives that provide ion assistance, such as argon and BCI 3 .
• the volatile metal carbonyl by-product has been described as a gas, it will be understood by those skilled in the art that the metal carbonyl by-product may also be a liguid. There is no intention of limiting the preferred embodiment to a gaseous type of metal carbonyl as a liquid type of metal carbonyl is also contemplated. In either case however, the metal carbonyl by-product may be easily and conveniently removed from the plasma etcher by a pumping action during etch. Referring now to FIG. 3, a specific example will be provided to illustrate how the plasma etch process 400 can be applied to specific types of applications. As a first example, a process for forming a nonvolatile memory cell will be described in greater detail.
• the process for forming a nonvolatile memory cell begins by providing layers to be etched above a wafer surface.
• the structure to be formed includes a bottom conductor 500, a barrier layer 502, a vertically oriented semiconductor junction diode 504, a compound stack 514, and a top conductor 512.
• the compound stack 514 includes titanium nitride layer 506, nickel oxide layer 508, and titanium nitride layer 510.
• the word stack is utilized in this specification to mean an operative layer of material which may or may not be associated with other layers of operative materials that may be disposed below or above, or below and above, the first mentioned material layer.
• the layers in such a stack may be conducting or insulating.
• Fig. 3 is one of a large array of such structures formed at the same time on a single wafer. Only one such structure is shown for simplicity.
• bottom conductor 500, barrier layer 502, and junction diode 504 have already been formed by conventional deposition and pattern ai ⁇ d etch processes.
• dielectric fill (not shown) which has been planarized, forming a top planar surface.
• the layers of the compound stack 514 (titanium nitride layer 506, nickel oxide layer 508, and titanium nitride layer 510) have been deposited, and are to be patterned and etched to form the structure shown in Fig. 3 (Top conductor 512 will be formed in later conventional processes which will not be described herein.)
• Fig. 3 shows the compound stack 514 in perfect alignment with the underlying diode 504. In reality there may be some misalignment.
• a photolithographic step will be performed. A layer of photoresist (not shown) is spun on top of top titanium nitride layer 510. Using a photomask in a conventional process, some areas of the photoresist are exposed, while others are not.
• a developing process removes the photoresist that has been exposed, while leaving behind the photoresist that was not exposed. In this way a pattern is transferred from a photomask to the photoresist.
• the etch step of the present invention will transfer the pattern from the photoresist above the compound stack to the underlying layers of the compound stack.
• additional layers such as a hard mask, may exist.
• the pattern may be transferred from the photoresist to the hard mask, then from the hard mask to the compound stack.
• the wafer including compound stack 514 is then loaded into a plasma etcher at the load step 404 to allow the plasma etch.
• the activate or etch/evacuate process begins.
• the etch/evacuate process is performed in two parts as will be explained hereinafter in greater detail.
• the stack 514 (FIG. 3) of titanium nitride on bottom, nickel oxide in the middle, and titanium nitride on top needs to be patterned as a post/pillar on top of junction diode 504.
• U.S. Patent Application Serial No.: 11/125,939 entitled “Rewritable Memory Cell Comprising a Diode and Resistance-Switching Material", by S. Brad Herner and Christopher J. Petti, hereby incorporated by reference, describes a rewriteable memory cell like the structure of Fig. 3, comprising a vertically oriented polycrystalline semiconductor diode arranged in series with nickel oxide layer, wherein the nickel oxide layer can be switched between resistivity states.
• the nickel oxide layer is between barrier layers or electrode layers, for example, as in the structure of Fig. 3, of titanium nitride.
• the stack to be etched includes, from the top, a titanium nitride layer (or other suitable electrode) , a nickel oxide layer, and a second titanium nitride layer. This etch can be performed using embodiments of the present invention.
• the TiN-NiO-TiN stack is deposited before the polycrystalline diode 504 has been etched, and all of these layers are etched in a single pattern and etch step.
• Equation 1 a carbon monoxide based chemistry is used to plasma etch the nickel oxide in the stack 310, and thus, produces a volatile by-product of nickel carbonyl.
• Equation 1 The foregoing chemical reaction is expressed by Equation 1:
• TM means transition metal
• top and bottom titanium nitride layers can be etched using conventional fluorine-based chemistry. These can be done as part of the NiO etching in separate sub-steps performed before and after the NiO etch.
• a metal or poly etcher may be used if CO is made available.
• a Cl 2 /BCl 3 based chemistry or a Cl 2 /HBr chemistry is used to etch the titanium nitride. The etch of the structure 514 occurs in three steps.
• an oxide etcher is used to provide a fluorine plasma to etch titanium nitride layer 508 within the stack 514, and then to provide the carbon monoxide plasma to etch nickel oxide layer 508 in the stack 514. Finally the etch chemistry is changed back to a fluorine-based chemistry to etch titanium nitride layer 506. The areas of the wafer surface that are not protected by photoresist are etched during this etch step, while the protected areas remain. In this way the structure shown in Fig. 3 is formed. As described earlier, the by-product resulting from the CO gas etch is immediately evacuated as fast as it is formed during the etch.
• a carbon monoxide plasma for etching a transition metal such as nickel oxide
• carbon monoxide as an etchant is not limited to etching only nickel and nickel oxide as noted earlier. That is, the process can be applied equally well to other transition metals and other transition metal compounds, such as iron and oxides of iron, for example. In this regard, the same methodology can be utilized to etch other transition metals, their oxides or other associated compounds.
• one of the key benefits of using carbon monoxide as an etchant is that it reacts with most transition metals to form metal carbonyls that are volatile or that have relatively low boiling points. This, in turn results in significantly lower defect levels. This is an important aspect of the present invention.
• carbon monoxide can also act as a reducing agent and hence transition metal oxides can also be etched in a carbon monoxide containing plasma.
• other gases may be required and used in a plasma etcher.
• Ar/BCl 3 may provide energetic ion bombardment; hydrogenated fluorocarbons or H 2 may be useful in providing a reducing ambient, if needed.
• carbon monoxide plasma as a primary etchant
• a process has been described relative to a stack of titanium nitride, nickel oxide, titanium nitride.
• Other examples would include forming a vertically oriented semiconductor junction diode with a transition metal or transition metal oxide above or below the semiconductor junction diode and then plasma etching the structure above or below the semiconductor junction diode with carbon monoxide-based plasma.
• a first memory level has been formed. Additional memory levels can be formed above the first one, forming a monolithic three dimensional memory array. Each nonvolatile memory cell resides in the monolithic three dimensional memory array.
• a monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates.
• the layers forming one memory level are deposited or grown directly over the layers of an existing level or levels.
• stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, US Patent No.
• the substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
• a monolithic three dimensional memory array formed above a substrate comprises at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or indeed any number of memory levels can be formed above the substrate in such a multilevel array.
• a sandwiched structure is for providing an example of the application of carbon monoxide plasma as a primary etchant only.
• the method of using carbon monoxide as an etchant can be applied to many other types of transition metals, their oxides and compounds of transition metal oxides.
• a blanket plasma etching experiment was conducted in a standard oxide etcher. A flow of predominantly carbon monoxide (as specified below) was supplied. The test sample was a wafer having an un-patterned nickel oxide (“NiO") layer that was sputtered onto TiN over an SiO 2 base. Plasma etching was conducted under the following conditions :
• A was achieved.
• the range in etch across the wafer was about 10 A. Note that the etch is the average NiO loss between the center and the edge of the wafer as determined by a cross-section measurement.
• Example 2 Another etching experiment was run using the same apparatus as used in Example 1. The experiment was conducted on a TiN/NiO/TiN stack with photo resist masking. A first etch was conducted using CF 4 /CHF 3 to etch the top TiN layer. A second etch was conducted using carbon monoxide to etch the NiO layer. For the second etch, the process conditions were the same as that used for Example 1, except that three different power/etching time combinations were used. The following measured data was obtained.
• Example 1 For example, one variation of Example 1 process conditions which is predicted to achieve satisfactory etching results is:
• Example 1 Another variation of Example 1 which is predicted to achieve satisfactory etching results is:

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