WO2008072826A1 - Tec de type métal-ferroélectrique-métal-semi-conducteur (mfms) et mémoire ferroélectrique de type mfms - Google Patents

Tec de type métal-ferroélectrique-métal-semi-conducteur (mfms) et mémoire ferroélectrique de type mfms Download PDF

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Publication number
WO2008072826A1
WO2008072826A1 PCT/KR2007/002881 KR2007002881W WO2008072826A1 WO 2008072826 A1 WO2008072826 A1 WO 2008072826A1 KR 2007002881 W KR2007002881 W KR 2007002881W WO 2008072826 A1 WO2008072826 A1 WO 2008072826A1
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WO
WIPO (PCT)
Prior art keywords
ferroelectric
mfms
electrode layer
polymer
memory device
Prior art date
Application number
PCT/KR2007/002881
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English (en)
Inventor
Byung-Eun Park
Original Assignee
University Of Seoul Foundation Of Industry-Academic Cooperation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020070057534A external-priority patent/KR100866314B1/ko
Application filed by University Of Seoul Foundation Of Industry-Academic Cooperation filed Critical University Of Seoul Foundation Of Industry-Academic Cooperation
Priority to JP2009541206A priority Critical patent/JP5440852B2/ja
Publication of WO2008072826A1 publication Critical patent/WO2008072826A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/10—Organic polymers or oligomers
    • H10K85/111—Organic polymers or oligomers comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
    • H10K85/113—Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
    • H10K85/1135—Polyethylene dioxythiophene [PEDOT]; Derivatives thereof

Definitions

  • the present invention relates to a metal- ferroelectric-metal-semiconductor (MFMS) field-effect transistor (FET) and an MFMS-ferroelectric memory device having a simple structure and excellent data retention characteristics.
  • MFMS metal- ferroelectric-metal-semiconductor
  • FET field-effect transistor
  • FIG. 1 is a cross-sectional view showing a typical structure of a metal-ferroelectric- semiconductor (MFS) type memory device using a ferroelectric material .
  • MFS metal-ferroelectric- semiconductor
  • source and drain regions 2 and 3 are formed in predetermined areas of a silicon substrate 1, and a ferroelectric layer 5 is formed on a channel region 4 between the source and drain regions 2 and 3.
  • the ferroelectric layer 5 comprises an inorganic material having ferroelectric properties such as PbZr x Tii_ x ⁇ 3 (PZT) , SrBi 2 Ta 2 O 9 (SBT), (Bi, La) 4 Ti 3 Oi 2 (BLT), and the like.
  • a source electrode 6, a drain electrode 7 and a gate electrode 8 formed of a metal material, respectively, are arranged on the top of the source and drain regions 2 and 3 and the ferroelectric layer 5.
  • the ferroelectric layer 5 has polarization characteristics in accordance with a voltage applied through the gate electrode 8, and a conductive channel is formed between the source region 2 and the drain region 3 by the polarization characteristics. As a result, a current flows between the source electrode 6 and the drain electrode 7. Especially, in the above-described structure, even in a case where the voltage applied through the gate electrode 8 is cut off, the polarization characteristics of the ferroelectric layer 5 are continuously maintained.
  • the ferroelectric memory having the above- described structure has the following problems. That is, when the ferroelectric layer 5 is directly formed on the silicon substrate 1, a transition layer of low quality is formed on the boundary between the ferroelectric layer 5 and the silicon substrate 1 during the formation of the ferroelectric layer 5, and chemical elements such as Pb and Bi in the ferroelectric layer 5 are diffused into the silicon substrate 1, thus making it difficult to form a ferroelectric layer 5 of high quality. As a result, there occurs a problem that the polarization characteristics of the ferroelectric layer 5 are deteriorated, that is, the data retention time of the ferroelectric memory becomes very short.
  • MFIS metal-ferroelectric-insulator- semiconductor
  • FIG. 3 is a diagram showing an equivalent circuit in a state where a gate voltage applied to the gate electrode 8 is cut off in the MFIS structure.
  • a capacitor Cl corresponds to the ferroelectric layer 5 and a capacitor C2 corresponds to the buffer layer 20.
  • an inner potential is set to 0.
  • the ferroelectric material has a constant polarization value Q due to a spontaneous polarization even in a case where the external voltage is cut off. That is, in the equivalent circuit of FIG. 3, the capacitor Cl corresponding to the ferroelectric layer 5 has a polarization value Q.
  • an inverse polarization field is generated in the capacitor C2 to make the potential of the closed loop become 0 in general by offsetting the polarization value Q of the capacitor Cl. Since the direction of the inverse polarization field is opposite to that of the polarization field by the capacitor Cl, the polarization value Q of the capacitor Cl may be continuously deteriorated. As described above, in the MFIS type ferroelectric memory shown in FIG. 2, the polarization characteristics of the ferroelectric layer 5 are deteriorated due to the depolarization field caused by the buffer layer 20 and thereby the data retention characteristics are degraded. As a result, the data retention time cannot exceed 30 days even in case of an excellent product manufactured in a laboratory.
  • an object of the present invention is to provide a metal- ferroelectric-metal-semiconductor (MFMS) field-effect transistor (FET) and an MFMS-ferroelectric memory device having a simple structure and excellent data retention characteristics .
  • MFMS metal- ferroelectric-metal-semiconductor
  • FET field-effect transistor
  • a metal-ferroelectric-metal-semiconductor (MFMS) memory device including: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the upper side of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer.
  • MFMS metal-ferroelectric-metal-semiconductor
  • a metal-ferroelectric-metal- semiconductor (MFMS) field-effect transistor (FET) including: a substrate including source and drain regions, and a channel region formed therebetween; a lower electrode layer formed on the upper side of the channel region of the substrate; a ferroelectric layer formed on the lower electrode layer; and an upper electrode layer formed on the ferroelectric layer.
  • MFMS metal-ferroelectric-metal- semiconductor
  • the lower electrode layer is a data electrode.
  • the upper electrode layer is a ground electrode.
  • the lower and upper electrode layers comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt) , indium tin oxide (ITO) , and strontiumtitanate (SrTiO 3 ) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
  • conductive metals including gold (Au) , silver (Ag) , aluminum (Al) , platinum (Pt) , indium tin oxide (ITO) , and strontiumtitanate (SrTiO
  • the ferroelectric layer comprises at least one selected from the group consisting of a ferroelectric oxide, a polymer ferroelectric material, a ferroelectric fluoride, a ferroelectric semiconductor, and solid solutions thereof.
  • the ferroelectric oxide comprises at least one selected from the group consisting of perovskite ferroelectric materials such as PbZr x Tii_ x O 3 (PZT) , BaTiO 3 and PbTiO 3 , pseudo-ilmenite ferroelectric materials such as LiNbO 3 and LiTaO 3 , tungsten-bronze (TB) ferroelectric materials such as PbNb 3 O ⁇ and Ba 2 NaNb S Ui S , ferroelectric materials having a bismuth layer structure such as SrBi 2 Ta 2 Og (SBT), (Bi, La) 4Ti 3 Oi 2 (BLT) and Bi 4 Ti 3 Oi 2 , pyrochlore ferroelectric materials such as La 2 Ti 2 O 7 , and ferroelectric
  • the polymer ferroelectric material comprises at least one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano- polymer, and polymer or copolymer thereof.
  • PVDF polyvinylidene fluoride
  • the polymer ferroelectric material comprises PVDF having a ⁇ -phase crystal structure.
  • the ferroelectric semiconductor comprises at least one selected from the group consisting of 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe.
  • the lower electrode layer and the upper electrode layer are arranged to extend in a direction that the two layers intersect each other.
  • the lower electrode layer is a ground electrode and the upper electrode layer is a data electrode
  • FIG. 1 is a cross-sectional view showing a structure of a conventional metal-ferroelectric-semiconductor (MFS) type memory device;
  • MFS metal-ferroelectric-semiconductor
  • FIG. 2 is a cross-sectional view showing a structure of a conventional metal-ferroelectric-insulator- semiconductor (MFIS) type memory device;
  • MFIS metal-ferroelectric-insulator- semiconductor
  • FIG. 3 is a diagram illustrating problems of the conventional structure shown in FIG. 2;
  • FIG. 4 is a cross-sectional view showing a metal- ferroelectric-metal-semiconductor (MFMS) field-effect transistor (FET) or an MFMS-ferroelectric memory device in accordance with a preferred embodiment of the present invention.
  • MFMS metal- ferroelectric-metal-semiconductor
  • FET field-effect transistor
  • FIG. 4 is a cross-sectional view showing a metal- ferroelectric-metal-semiconductor (MFMS) field-effect transistor (FET) or an MFMS-ferroelectric memory device in accordance with a preferred embodiment of the present invention.
  • MFMS metal- ferroelectric-metal-semiconductor
  • FET field-effect transistor
  • the memory device in accordance with the present invention has a metal-ferroelectric-metal-semiconductor (MFMS) structure, differently from a conventional metal- ferroelectric-semiconductor (MFS) structure and a metal- ferroelectric-insulator-semiconductor (MFIS) structure.
  • MFMS metal-ferroelectric-metal-semiconductor
  • source and drain regions 2 and 3 are formed in predetermined areas of a silicon substrate 1, and a data electrode 30, for example, is formed as a lower electrode layer on a channel region 4 between the source and drain regions 2 and 3.
  • the data electrode 30 is provided to generate a polarization voltage in a ferroelectric layer 31 to be described later.
  • the data electrode 30 may comprise at least one selected from the group consisting of conductive metals including gold (Au), silver (Ag), aluminum (Al), platinum (Pt) , indium tin oxide (ITO) , and strontiumtitanate (SrTiOa) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
  • conductive metals including gold (Au), silver (Ag), aluminum (Al), platinum (Pt) , indium tin oxide (ITO) , and strontiumtitanate (Sr
  • the ferroelectric layer 31 is formed on the data electrode 30.
  • a ferroelectric oxide having ferroelectric characteristics a polymer ferroelectric material, a ferroelectric fluoride such as BaMgF 4 (BMF) , and a ferroelectric semiconductor may be used.
  • the ferroelectric oxide may comprise at least one selected from the group consisting of perovskite ferroelectric materials such as PbZr x Tii_ x O 3 (PZT) , BaTiO 3 and PbTiO 3 , pseudo-ilmenite ferroelectric materials such as LiNbO 3 and LiTaO 3 , tungsten-bronze (TB) ferroelectric materials such as PbNb 3 Oe and Ba 2 NaNb S Ui S , ferroelectric materials having a bismuth layer structure such as SrBi 2 Ta 2 Og (SBT), (Bi, La) 4Ti 3 Oi 2 (BLT) and Bi 4 Ti 3 Oi 2 , pyrochlore ferroelectric materials such as La 2 Ti 2 O 7 , and ferroelectric materials such as RMnO 3 , Pb 5 Ge 3 On (PGO) and BiFeO 3 (BFO) including a rare earth element (R) such as Y, Er, Ho, Tm, Yb and Lu.
  • the polymer ferroelectric material may comprises at least one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano- polymer, and polymer or copolymer thereof.
  • PVDF polyvinylidene fluoride
  • the ferroelectric layer 31 comprises PVDF having a ⁇ -phase crystal structure.
  • the ferroelectric semiconductor comprises at least one selected from the group consisting of 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe.
  • a ground electrode 32 is formed as an upper electrode layer on the ferroelectric layer 31.
  • the ground electrode 32 may comprise at least one selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO 3 ), conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
  • conductive metals including gold (Au) , silver (Ag) , aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO 3
  • conductive metal oxides conductive metal alloys
  • conductive metal compounds and, further, conductive organics
  • the data electrode 30 and the ground electrode 32 extend to intersect each other so as to select the memory cell arranged at the intersection selected by the data electrode 30 and the ground electrode 32.
  • the polarization is generated in the ferroelectric layer 31 by applying a predetermined voltage through the data electrode 30 in a state where the ground electrode 32 is connected to the ground.
  • a predetermined voltage is applied to a drain electrode 7 and, at the same time, it is determined whether the data stored in a corresponding memory cell is X ⁇ l" or "0" based on whether or not the transistor is in a conductive state while grounding a source electrode 6.
  • the ferroelectric layer 31 is not directly in contact with the silicon substrate 1 but connected thereto through the data electrode 30. Accordingly, it is possible to solve the problem that a transition layer of low quality is formed on the boundary between the ferroelectric layer 5 and the silicon substrate 1 during the formation of the ferroelectric layer 5.
  • a buffer layer is not provided between the ferroelectric layer 31 and the substrate 1 in the above structure, it is possible to solve the problem that data retention characteristics are degraded due to the deterioration of the polarization characteristics caused by a depolarization field, for example.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne un transistor à effet de champ (TEF) de type métal-ferroélectrique-métal-semi-conducteur (MFMS) et une mémoire ferroélectrique de type MFMS. Le TEF et la mémoire ferroélectrique comprennent: un substrat 1 comportant des régions de source et de drain 2 et 3, ainsi qu'une région de canal 4 formée entre celles-ci; une couche d'électrode inférieure 30 formée sur le côté supérieur de la région de canal 4 du substrat 1; une couche ferroélectrique 31 formée sur la couche d'électrode inférieure 30; et une couche d'électrode supérieure 32 formée sur la couche ferroélectrique 31.
PCT/KR2007/002881 2006-12-13 2007-06-14 Tec de type métal-ferroélectrique-métal-semi-conducteur (mfms) et mémoire ferroélectrique de type mfms WO2008072826A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009541206A JP5440852B2 (ja) 2006-12-13 2007-06-14 Ｍｆｍｓ型電界効果トランジスタ及び強誘電体メモリ装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20060127494 2006-12-13
KR10-2006-0127494 2006-12-13
KR10-2007-0057534 2007-06-12
KR1020070057534A KR100866314B1 (ko) 2006-12-13 2007-06-12 엠에프엠에스형 전계효과 트랜지스터 및 강유전체 메모리장치

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WO2008072826A1 true WO2008072826A1 (fr) 2008-06-19

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942776A (en) * 1997-03-07 1999-08-24 Sharp Laboratories Of America, Inc. Shallow junction ferroelectric memory cell and method of making the same
US6236076B1 (en) * 1999-04-29 2001-05-22 Symetrix Corporation Ferroelectric field effect transistors for nonvolatile memory applications having functional gradient material

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942776A (en) * 1997-03-07 1999-08-24 Sharp Laboratories Of America, Inc. Shallow junction ferroelectric memory cell and method of making the same
US6236076B1 (en) * 1999-04-29 2001-05-22 Symetrix Corporation Ferroelectric field effect transistors for nonvolatile memory applications having functional gradient material

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