WO2008047333A3 - Modulateur delta-sigma - Google Patents

Modulateur delta-sigma Download PDF

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Publication number
WO2008047333A3
WO2008047333A3 PCT/IE2007/000099 IE2007000099W WO2008047333A3 WO 2008047333 A3 WO2008047333 A3 WO 2008047333A3 IE 2007000099 W IE2007000099 W IE 2007000099W WO 2008047333 A3 WO2008047333 A3 WO 2008047333A3
Authority
WO
WIPO (PCT)
Prior art keywords
modulator
output
stage
delta
sigma modulator
Prior art date
Application number
PCT/IE2007/000099
Other languages
English (en)
Other versions
WO2008047333A2 (fr
Inventor
Michael Peter Kennedy
Zhipeng Ye
Original Assignee
Univ College Cork Nat Univ Ie
Michael Peter Kennedy
Zhipeng Ye
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ College Cork Nat Univ Ie, Michael Peter Kennedy, Zhipeng Ye filed Critical Univ College Cork Nat Univ Ie
Publication of WO2008047333A2 publication Critical patent/WO2008047333A2/fr
Publication of WO2008047333A3 publication Critical patent/WO2008047333A3/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3022—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

L'invention concerne un modulateur delta-sigma numérique qui comprend un nombre m (par exemple trois) d'étages modulateurs delta-sigma montés en cascade selon une topologie de circuit de type MASH. Une entrée (30) reçoit un mot de commande et un premier étage modulateur N1 bits (31) produit une sortie de retenue y et une sortie d'erreur de quantification N2 bits g, N2 ≤ N1. Les étages modulateurs additionnels présentent chacun une longueur de mot Ni qui est inférieure ou égale à celle de l'étage précédent, et Ni<Ni-1 pour au moins un i, 2 ≤ i ≤ m. Des moyens de filtrage combinent les sorties de retenue des étages modulateurs pour produire un signal de sortie de modulateur avec mise en forme du bruit. La longueur des mots est réduite par des quantificateurs entre étages (QM) qui ne requièrent pas d'espace supplémentaire étant donné qu'ils suppriment simplement un nombre de bits de poids faible. Dans un exemple, dans lequel m = 3 et les filtres présentent la fonction de transfert 1-z-1, N1 = 20, N2 = 14 et N3 = 12. Un tremblement peut être ajouté à l'entrée, auquel cas les contributions des quantificateurs entre étages à l'erreur de sortie sont masquées par le quantificateur de sortie et les contributions de tremblement filtré.
PCT/IE2007/000099 2006-10-17 2007-10-16 Modulateur delta-sigma WO2008047333A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IE2006/0763 2006-10-17
IE20060763 2006-10-17

Publications (2)

Publication Number Publication Date
WO2008047333A2 WO2008047333A2 (fr) 2008-04-24
WO2008047333A3 true WO2008047333A3 (fr) 2008-06-05

Family

ID=39171431

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IE2007/000099 WO2008047333A2 (fr) 2006-10-17 2007-10-16 Modulateur delta-sigma

Country Status (2)

Country Link
IE (1) IE20070748A1 (fr)
WO (1) WO2008047333A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10623008B2 (en) * 2015-04-30 2020-04-14 Xilinx, Inc. Reconfigurable fractional-N frequency generation for a phase-locked loop
CN106788443B (zh) * 2016-11-25 2020-05-08 福州大学 一种改进型的MASH结构Sigma-Delta调制器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0366229A2 (fr) * 1988-09-06 1990-05-02 Plessey Semiconductors Limited Convertisseurs analogique-numériques à réduction de bruit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0366229A2 (fr) * 1988-09-06 1990-05-02 Plessey Semiconductors Limited Convertisseurs analogique-numériques à réduction de bruit

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
BORNOOSH B ET AL: "Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications - General articles", IEE PROCEEDINGS: CIRCUITS DEVICES AND SYSTEMS, INSTITUTION OF ELECTRICAL ENGINEERS, STENVENAGE, GB, vol. 152, no. 5, 7 October 2005 (2005-10-07), pages 471 - 477, XP006025231, ISSN: 1350-2409 *
HOSSEINI K ET AL: "Mathematical Analysis of Digital MASH Delta-Sigma Modulators for Fractional-N Frequency Synthesizers", RESEARCH IN MICROELECTRONICS AND ELECTRONICS 2006, PH. D. OTRANTO, ITALY 12-15 JUNE 2006, PISCATAWAY, NJ, USA,IEEE, 12 June 2006 (2006-06-12), pages 309 - 312, XP010937693, ISBN: 1-4244-0157-7 *
MILLER B ET AL: "A MULTIPLE MODULATOR FRACTIONAL DIVIDER", IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 40, no. 3, 1 June 1991 (1991-06-01), pages 578 - 583, XP000259711, ISSN: 0018-9456 *
ZHIPENG YE AND MICHAEL PETER KENNEDY: "Reduced Complexity MASH Delta-Sigma Modulator", 20 November 2006 (2006-11-20), University College Cork, Ireland, XP002473910, Retrieved from the Internet <URL:http://sscs.ucc.ie/061120%20Zhipeng%20Ye.pdf> [retrieved on 20080326] *

Also Published As

Publication number Publication date
IE20070748A1 (en) 2008-06-11
WO2008047333A2 (fr) 2008-04-24

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