WO2008047333A2 - Modulateur delta-sigma - Google Patents

Modulateur delta-sigma Download PDF

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Publication number
WO2008047333A2
WO2008047333A2 PCT/IE2007/000099 IE2007000099W WO2008047333A2 WO 2008047333 A2 WO2008047333 A2 WO 2008047333A2 IE 2007000099 W IE2007000099 W IE 2007000099W WO 2008047333 A2 WO2008047333 A2 WO 2008047333A2
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Prior art keywords
output
stage
sigma modulator
delta
bit
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PCT/IE2007/000099
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English (en)
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WO2008047333A3 (fr
Inventor
Michael Peter Kennedy
Zhipeng Ye
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University College Cork - National University Of Ireland, Cork
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Publication of WO2008047333A2 publication Critical patent/WO2008047333A2/fr
Publication of WO2008047333A3 publication Critical patent/WO2008047333A3/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3022—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Definitions

  • the invention relates to a delta-sigma modulator, and particularly a digital Multi- stAge noise SHaping (MASH) delta-sigma modulator, and to applications of such modulators such as in frequency synthesisers.
  • MASH digital Multi- stAge noise SHaping
  • Figs. 1-9 illustrate aspects of the prior art.
  • the synthesizer 29 comprises a phase- frequency detector (PFD) 15, a charge pump (CP) 16, a loop filter (LF) 17, and a voltage-controlled oscillator (VCO) 18.
  • a reference frequency f re f is applied at the input 14 of the PFD 15.
  • a multi-modulus frequency divider 21 is located in the feedback loop between the VCO output 20 and an input 25 of the PFD 15.
  • the PFD 15 compares the phases of its two input signals and produces a control signal 26 that corresponds to the phase difference between the two signals obtained.
  • the control signal 26 is supplied to a CP 16 while the output 27 of the CP 16 is supplied to a LF 17 that is a low-pass filter and smoothes the control signal 27.
  • the output 28 of the loop filter 17 is supplied to a VCO 18.
  • the VCO 18 generates a frequency signal/, ⁇ at the VCO output 19 in response to the signal at its input 28.
  • the output of the VCO is fed back to the PFD 15 as a frequency divider signal 25 via a programmable frequency divider 21.
  • the programmable frequency divider 21 is normally in the form of a multi-modulus frequency divider.
  • the action of the synthesiser 29 is such that the frequency f out of the output signal from the VCO in the state of equilibrium corresponds exactly to the reference- frequency f re f multiple stipulated by the frequency divider 21.
  • the frequency f out at the VCO output 19 is a fraction multiple of the input reference frequency ⁇ e/ Since the frequency divider 21 in actuality is not dividing by a fractional division ratio, but rather an integer value, fractional-N frequency synthesis is achieved through division ratio averaging, that is the division ratio is dynamically switched between two or more values, effectively causing the divider to divide by a non-integer number.
  • the delta-sigma modulator (DSM) 23 controls the division ratio of the frequency divider 21 in accordance with information in an N-bit control word x coupled to the input 22 of the DSM 23.
  • the input control word x includes all the necessary information to be provided to the multi-modulus frequency divider 21, including any pre-dividers.
  • the multi-modulus frequency divider may take on different forms and implementations and, for purposes of explanation in Fig. 1, the multi-modulus frequency divider produces the loop phase error signal 27.
  • the clock signal 24 of the DSM is shown here as the output signal of the frequency divider 21 in Fig. 1.
  • the output signal 24 of the frequency divider 21 is the clock signal, which ensures that the output signal of the DSM is correctly synchronized with the frequency divider.
  • the shape, spurious level and spurious content of the output spectrum of the fractional -N synthesizer is dependent upon the order of the DSM 23.
  • the output noise spectral density of higher order digital delta-sigma modulators is shown to increase monotonically at greater rates and to shift quantization noise to higher frequencies.
  • the higher out-of-band noise level is suppressed by using a loop filter, which is set one order higher than or equal to the order of the DSM.
  • Higher order digital DSMs increase the complexity of the circuits, chip size, and power consumption. There are a number of considerations that must be taken into account to improve the performance and to minimize the fractional spurious levels.
  • Fig. 2 shows an N-bit accumulator structure and its model is shown in Fig. 3.
  • the nonlinear difference equations governing the structure shown in Fig. 3 can be summarized as:
  • N-bit accumulator The block diagram of the N-bit accumulator is shown in Fig. 4, where (1, N, N, 1) means 1st order, N-bit input, N-bit quantization error output, and 1-bit carry output, respectively, x, y and w are the input, carry output, and quantization error output of the modulator, respectively.
  • a state of the art embodiment of an mth-order MASH digital delta- sigma modulator is illustrated. It is comprised of m cascaded first order delta-sigma modulators designated generally as digital accumulators DSM (I 5 N 5 N 5 I).
  • DSM digital accumulators
  • the N-bit input control word x corresponding to the desired channel or frequency band appears at the input line 60 of the N-bit accumulator 61 comprising the first delta-sigma modulator.
  • the quantization error output 70 of the first modulator 61 is coupled to the input of the second N-bit accumulator 71.
  • the quantization error output 80 of the second accumulator 71 is coupled to the input of the third accumulator.
  • the quantization error output 81 of the (m-7)th accumulator is coupled to the input of the Mh accumulator 81.
  • the carry signal at the output 62 of the first N-bit accumulator 61 is coupled to the delay cell 63 with the transfer function Z ⁇ 1 K
  • the output 64 of this delay cell 63 is coupled to one of the inputs of the adder 65.
  • the carry signal at the output 72 of the second N-bit accumulator 71 is coupled to the delay cell 73 with the transfer function z - (m - 2) ⁇ jt ⁇ g ou - ⁇ U t 74 o f this delay cell 73 is coupled to one of the inputs of another adder 76.
  • the carry signal output 83 of the r ⁇ th accumulator 82 is coupled to the input of the filter cell 79 with the transfer function 1-z "1 .
  • the output of the filter cell is coupled to one of the inputs of an adder.
  • the output of this adder is coupled to the input of another, and so on, until, in the second stage, it is coupled to the input 77 of the adder 76, whose output is coupled to another filter cell 69 with the transfer function 1-z '1 .
  • the output 68 of the filter cell 69 is coupled to one of the inputs of the adder 65.
  • the output 67 of the adder 65 is coupled to the delta-sigma modulator output control lead.
  • the network of delay cells, filter cells, and adders that takes as inputs the m quantizer outputs y ⁇ , y 2 , ..., y m and produces a single output ⁇ , is known as the error cancellation network.
  • a 3 rd -order MASH DSM is taken as an example, which comprises three cascaded first-order DSMs.
  • the output of the MASH DSM can be expressed in the Z-domain as:
  • STF and NTF are the signal and noise transfer functions, respectively
  • Es(z) is the z-transform of the error introduced by the quantizer in the third stage.
  • NTF (I - Z ' ') 3 . (5)
  • f re f is the sample frequency
  • the simulated output spectrum of a prior 19-bit MASH DSM is shown in Fig. 7, where the slope of 60 dB/decade is again observable.
  • Fig. 7 The deviation of the power spectrum from the linear NTF, as shown in Fig. 8, which is normalized by the sequence length of 2 20 .
  • the sequence length and the effective number of bits in the modulator determine the closeness of the power spectrum to the white noise linear approximation shown in Fig. 6.
  • DDSM digital DSM
  • Another object is to provide a digital MASH delta-sigma modulator for applications such as in a phase-locked loop fractional-N frequency synthesizer that achieves a prescribed spur performance but with reduced hardware complexity compared to the prior art.
  • a digital delta-sigma modulator comprising: a plurality of delta-sigma modulator stages cascaded in a MASH circuit topology and defining an Mh order delta-sigma modulator; input means for receiving a control word; a first N 1 -Wt modulator stage that produces a carry output and an N 2 -Mt error quantization output, where N 2 - - ⁇ N 1 ; additional modulator stages each with a word length Nj that is less than or equal to that of the preceding stage, and N ⁇ NH for at least one i, 2 ⁇ i ⁇ m; and filtering means for combining the carry outputs of the modulator stages to produce a noise-shaped modulator output signal.
  • said delta-sigma modulator comprises an N 1 -bit accumulator in the first stage, and Nj-Mt (Nj ⁇ NM) accumulators in the following stages, and N ⁇ Ni -1 for at least one /, 2 ⁇ i ⁇ m .
  • the input means comprises an input for receiving an N 1 -bit signal
  • the first stage comprises a first (N 1 -bit) accumulator; - the first stage provides a first carry signal output yi indicative of an overflow condition;
  • the first stage provides an N 2 -bit feed forward output g] coupled to the input of a second (N 2 -Mt) accumulator;
  • the second stage comprises a second (N 2 -Mt) accumulator; - the second stage provides a second carry signal output y 2 indicative of an overflow condition; - the second stage provides an N 3 -bit feed forward output g2 coupled to the input of a third (N 3 -bit) accumulator in a third stage;
  • a third stage provides a third carry signal output jj indicative of an overflow condition; and - the filtering means comprises means for combining the carry output signals yj, y ⁇ , and ys from said three accumulators, such that the output signal y has an average value proportional to x; and Ni >N 2 ⁇ N 3 , and Ni ⁇ N i-1 for at least one i, 2 ⁇ i ⁇ 3.
  • the modulator further comprises at least one inter-stage quantizer for decreasing the word length N; between a pair of stages.
  • said inter-stage quantizer is configured to delete a number of least significant bits.
  • the word lengths of the stages are chosen such that the contributions of the inter-stage quantizers to the output error are negligible compared to that of the output quantizer.
  • the filtering means comprises adders, delay elements, and filters with transfer functions of 1-z "1 , and there are three stages with word lengths Ni, N 2 , and N 3 which satisfy the inequalities 4N 1 - 5N 2 - 4 ⁇ 4 log 2 ( ⁇ ) and 2N 1 - 3N 3 - 2 ⁇ 2 log 2 O).
  • the modulator further comprises an adder for receiving a filtered dither signal and for delivering it to the first stage.
  • the invention provides a fractional-N frequency synthesizer comprising any digital delta-sigma modulator as defined above, wherein said delta- sigma modulator is used for controlling a multi-modulus divider in the synthesiser.
  • Fig. 1 is a schematic functional block diagram showing a delta-sigma based fractional-N phase locked loop frequency synthesizer
  • Fig. 2 is a schematic representation of a digital accumulator
  • Fig. 3 is a model of a digital accumulator
  • Fig. 4 is a block diagram representation of a digital accumulator
  • Fig. 5 is a block diagram representation of a conventional N-bit mth. order MASH delta-sigma modulator
  • Fig. 6 is a magnitude plot of the normalized linear noise transfer function (NTF) of a MASH modulator
  • Fig. 7 is the power spectrum plot of the output y of a conventional 19-bit MASH delta-sigma modulator
  • Fig. 8 is the difference between the simulated spectrum and the normalized linear NTF for a conventional 19-bit MASH delta-sigma modulator;
  • Fig. 9 is an autocorrelation plot of the output ⁇ of a conventional 19-bit delta- sigma modulator;
  • Fig. 10 is a schematic representation of a digital accumulator with an additional M-bit inter-stage quantizer
  • Fig. 11 is a model of a digital accumulator with an additional M-bit inter-stage quantizer
  • Fig. 12 is a block diagram representation of a digital accumulator with an additional M-bit inter-stage quantizer
  • Fig. 13 is a block diagram representation of the new (N 1 , N 2 ,...,N m )-bit mth order MASH delta-sigma modulator;
  • Fig. 13(A) shows the power spectra of the error signals N ⁇ fz), Nn(Z) and N 23 (z) of the new (N 1 , N 2 , N 3 )-bit 3rd order MASH delta-sigma modulator;
  • the invention provides a digital MASH delta-sigma modulator (henceforth also referred to as a "DSM”) having a high-bit first stage, then further shaping the spectrum using additional modulator stages with smaller word lengths compared with the first stage.
  • DSM digital MASH delta-sigma modulator
  • the modulator may, for example, control a multi-modulus divider in a fractional-N frequency synthesizer.
  • the modulator has reduced hardware complexity compared with conventional MASH delta-sigma modulators.
  • the first stage of the DSM not only randomizes the constant input but also performs filtering.
  • the following stages, which perform additional filtering, have fewer bits than the first stage.
  • the DSM comprises an N-bit modulator stage for receiving the input signal and for generating a digital output signal having N bits, of which the M Most Significant Bits (MSBs) are forwarded to the next stage as its input, where M ⁇ N.
  • MSBs Most Significant Bits
  • An advantage of the DSM is that the hardware complexity is reduced due to the fact that fewer bits are required in each successive stage. A further advantage is that the power and area consumption are reduced since the hardware complexity is reduced. Another advantage is that better performance is achieved with a given amount of hardware compared with the conventional MASH DSM .
  • the function of the DSM is to produce or generate a long pseudo-random sequence of numbers averaging to a fraction equal to the desired fractional ratio.
  • the sequence length is related to the number of bits in the accumulator used in the DSMs and in general it is desired to make the sequence length as long as possible.
  • the present invention obtains a prescribed spectrum at the DSM output with reduced hardware complexity. It is intended for use with known and future types of DSM s, regardless of design or implementation or order.
  • the DSM uses fewer bits in the accumulators in each successive DSM stage in a cascade of two or more DSMs.
  • the DSM of the invention is economical, efficient, and practical to implement to achieve the desired benefits.
  • the inter-stage quantizer QM in Fig. 10 is realized simply by passing only the most significant M bits of its input to its output (and discarding the N-M least significant bits).
  • the other accumulators in the MASH chain use fewer bits (Nj-bit where Nj ⁇ Ni -1 ) to do the shaping. This allows one to reduce the word lengths in the following stages without changing the sequence length.
  • the block diagram of the reduced complexity mth-order MASH delta-sigma modulator is shown in Fig. 13, where N 1 > N 2 > ... ⁇ N m and Nj ⁇ N j.i for at least one i, 2 ⁇ i ⁇ m.
  • the N 1 -Wt input control word x corresponding to the desired channel or frequency band appears at the input line 30 of the N 1 -bit accumulator 31 comprising the delta-sigma modulator.
  • the N 2 -Mt quantization error output gi 40 of the accumulator 31 is coupled to the input of the second N 2 -bit accumulator 41.
  • the N 2 -Mt quantization error output g ⁇ can be derived from the quantization error wj of the first accumulator by means of an inter-stage quantizer QM ⁇ that passes only the N 2 most significant bits to the next stage.
  • the quantized output 50 of the second accumulator 41 is coupled to the input of the third N 3 -bit accumulator.
  • the N 3 -Mt quantization error output g 2 can be derived from the quantization error w ⁇ of the second accumulator by means of an inter-stage quantizer Qm that passes only the N 3 most significant bits to the next stage.
  • the quantization output 51 of the (m - l)th accumulator is coupled to the input of the mih accumulator 52.
  • the carry signal at the output 32 of the first Nj-bit accumulator 31 is coupled to the delay cell 33 with the transfer function z ⁇ (m'v .
  • the output 34 of this delay cell 33 is coupled to one of the inputs of the adder 35.
  • the carry signal at the output 42 of the second accumulator 41 is coupled to the delay cell 43 with the transfer function z '(m'2) .
  • the output 44 of this delay cell 43 is coupled to the input of another adder 46.
  • the output of the carry signal 53 of the r ⁇ th accumulator 52 is coupled to the input of the filter cell 49 with the transfer function 1-z "1 .
  • the output of the filter cell is coupled to one of the inputs of an adder.
  • the output of this adder is coupled to the input of another, and so on, until, in the second stage, it is coupled to the input 47 of the adder 46, whose output is coupled to another filter cell 39 with the transfer function 1-z '1 .
  • the output 38 of the filter cell 39 is coupled to one of the inputs of the adder 35.
  • the output 37 of the adder 35 is coupled to the delta-sigma modulator output control lead.
  • the error cancellation network comprising the delay cells, filter cells, and adders cancels the quantization errors from all stages except the last.
  • E 3 (z) is the z-transform of the error introduced by the quantizer in the last (third) stage.
  • Ej 2 (z) and E 23 (z) are the z-transforms of the errors introduced by the inter-stage quantizers between the first and second and second and third stages, respectively. These are not cancelled by the error cancellation network.
  • N 3 (z), Nj 2 (z), and N 23 (z) are the z- transforms of the filtered errors introduced by the third quantizer and the inter-stage quantizers between the first and second and second and third stages, respectively.
  • the noise-shaped errors due introduced by the reduction in bit widths can be masked by the larger noise-shaped error N 3 (z) component if the integer values of the word lengths Ni, N 2 and N 3 are chosen such that:
  • the resulting output power spectrum is shown in Fig. 14.
  • the expected 60 dB/decade slope is observed.
  • the peak deviation from the linear NTF model of only 4 dB in Fig. 15 is 9 dB less than in the case of the conventional 19-bit modulator.
  • the autocorrelation result shown in Fig. 16 confirms the expected sequence length of 2 .
  • sequence length can be maximized by a number of other means, including additive filtered LSB input dither.
  • FIG. 17 A reduced complexity delta-sigma modulator with additive filtered input dither is shown in Fig. 17.
  • a dither signal d is applied to the input 111 of a filter 113 with transfer function V(z).
  • the input x is applied to the first input 101 of an adder
  • the output 112 of the filter is applied to the second input 102 of the adder.
  • the output 103 of the adder is applied to the input 30 of the MASH delta-sigma modulator described in Fig. 13.
  • the output is defined by
  • E 3 (Z) is the z-transform of the error introduced by the quantizer in the third stage.
  • En(z) and E 23 (z) are the z-transforms of the errors introduced by the inter-stage quantizers between the first and second and second and third stages, respectively, as before.
  • N 3 (z), Nn(z), and N 23 (z) are the z-transforms of the filtered errors introduced by the third quantizer and the inter-stage quantizers between the first and second and second and third stages, respectively.
  • V(z) is the transfer function of the filter 113 and D(z) is the z-transform of the dither signal.
  • Additive filtered dither causes the output Y(z) [defined by equation (11)] to contain an extra term compared to equation (7).
  • error masking can be used to hide the noise-shaped quantization errors Nn(z) and N 23 (z) below [N 3 (z) + STF(z) V(z)D(z)] such that
  • V(z) (1-z '1 ).
  • the digital MASH delta-sigma modulator of the invention may be used in a fractional-N frequency synthesizer having the same architecture as shown in Fig.l, the DSM of the invention replacing that of the prior art. It will be understood that numerous modifications may be made to the example described above by those skilled in the art, for example, other delta-sigma modulator circuit topologies may be used, other choices of word lengths may be used in the accumulators, fewer bits may be used in each successive stage in the case of modulators with more than two stages, and the order of the delta-sigma modulators may be higher than the exemplary third order described herein, without departing from the spirit and scope of the invention. Therefore, the invention has been described by way of illustration rather than limitation. The invention is not limited to the embodiments described but may be varied in construction and detail.

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Abstract

L'invention concerne un modulateur delta-sigma numérique qui comprend un nombre m (par exemple trois) d'étages modulateurs delta-sigma montés en cascade selon une topologie de circuit de type MASH. Une entrée (30) reçoit un mot de commande et un premier étage modulateur N1 bits (31) produit une sortie de retenue y et une sortie d'erreur de quantification N2 bits g, N2 ≤ N1. Les étages modulateurs additionnels présentent chacun une longueur de mot Ni qui est inférieure ou égale à celle de l'étage précédent, et Ni<Ni-1 pour au moins un i, 2 ≤ i ≤ m. Des moyens de filtrage combinent les sorties de retenue des étages modulateurs pour produire un signal de sortie de modulateur avec mise en forme du bruit. La longueur des mots est réduite par des quantificateurs entre étages (QM) qui ne requièrent pas d'espace supplémentaire étant donné qu'ils suppriment simplement un nombre de bits de poids faible. Dans un exemple, dans lequel m = 3 et les filtres présentent la fonction de transfert 1-z-1, N1 = 20, N2 = 14 et N3 = 12. Un tremblement peut être ajouté à l'entrée, auquel cas les contributions des quantificateurs entre étages à l'erreur de sortie sont masquées par le quantificateur de sortie et les contributions de tremblement filtré.
PCT/IE2007/000099 2006-10-17 2007-10-16 Modulateur delta-sigma WO2008047333A2 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106788443A (zh) * 2016-11-25 2017-05-31 福州大学 一种改进型的MASH结构Sigma‑Delta调制器
CN107534444A (zh) * 2015-04-30 2018-01-02 赛灵思公司 为锁相环生成可重构的小数分频频率

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EP0366229A2 (fr) * 1988-09-06 1990-05-02 Plessey Semiconductors Limited Convertisseurs analogique-numériques à réduction de bruit

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EP0366229A2 (fr) * 1988-09-06 1990-05-02 Plessey Semiconductors Limited Convertisseurs analogique-numériques à réduction de bruit

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Title
BORNOOSH B ET AL: "Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications - General articles" IEE PROCEEDINGS: CIRCUITS DEVICES AND SYSTEMS, INSTITUTION OF ELECTRICAL ENGINEERS, STENVENAGE, GB, vol. 152, no. 5, 7 October 2005 (2005-10-07), pages 471-477, XP006025231 ISSN: 1350-2409 cited in the application *
HOSSEINI K ET AL: "Mathematical Analysis of Digital MASH Delta-Sigma Modulators for Fractional-N Frequency Synthesizers" RESEARCH IN MICROELECTRONICS AND ELECTRONICS 2006, PH. D. OTRANTO, ITALY 12-15 JUNE 2006, PISCATAWAY, NJ, USA,IEEE, 12 June 2006 (2006-06-12), pages 309-312, XP010937693 ISBN: 1-4244-0157-7 cited in the application *
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107534444A (zh) * 2015-04-30 2018-01-02 赛灵思公司 为锁相环生成可重构的小数分频频率
CN107534444B (zh) * 2015-04-30 2021-09-28 赛灵思公司 为锁相环生成可重构的小数分频频率
CN106788443A (zh) * 2016-11-25 2017-05-31 福州大学 一种改进型的MASH结构Sigma‑Delta调制器

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