IE20070748A1

IE20070748A1 - A delta-sigma modulator

Info

Publication number: IE20070748A1
Application number: IE20070748A
Authority: IE
Inventors: Michael Peter Kennedy; Zhipeng Ye
Original assignee: Univ College Cork Nat Univ Ie
Priority date: 2006-10-17
Filing date: 2007-10-16
Publication date: 2008-06-11
Also published as: WO2008047333A3; WO2008047333A2

Abstract

A digital delta-sigma modulator has a member m (for example three) of delta-sigma modulator stages cascaded in a MASH circuit topology. An input (30) receives a control word, and a first N1-bit modulator stage (31) produces a carry output y and an N2-bit quantization error output g, where N2<N1. The additional modulator stages each have a word length Ni that is less than or equal to that of the preceding stage, and Ni <Ni-! for at least one i, 2<i<m. Filtering means combine the carry outputs of the modulator stages to produce a noise-shaped modulator output signal. The word lengths are reduced by inter-stage quantizers (QM) which require no additional area as they merely remove a number of LSBs. In one example, where m = 3, and the filters have the transfer function 1-z-1, N1 = 20, N 2 = 14, and N3 = 12. Dither may be added to the input. In this case, the contribution of the inter-stage quantizers to the output error are masked by the output quantizer and filtered dither contributions.

Description

The invention relates to a delta-sigma modulator, and particularly a digital MultistAge noise SHaping (MASH) delta-sigma modulator, and to applications of such modulators such as in frequency synthesisers.

Figs. 1-9 illustrate aspects of the prior art. First considering Fig. 1, to gain a better understanding of the invention, a schematic functional block diagram of a representative prior delta-sigma modulator based fractional-N phase locked loop frequency synthesizer 29 is illustrated. The synthesizer 29 comprises a phasefrequency detector (PFD) 15, a charge pump (CP) 16, a loop filter (LF) 17, and a voltage-controlled oscillator (VCO) 18. A reference frequency //is applied at the input 14 of the PFD 15. A multi-modulus frequency divider 21 is located in the feedback loop between the VCO output 20 and an input 25 of the PFD 15. The PFD 15 compares the phases of its two input signals and produces a control signal 26 that corresponds to the phase difference between the two signals obtained. The control signal 26 is supplied to a CP 16 while the output 27 of the CP 16 is supplied to a LF 17 that is a low-pass filter and smoothes the control signal 27. The output 28 of the loop filter 17 is supplied to a VCO 18. The VCO 18 generates a frequency signal f0M at the VCO output 19 in response to the signal at its input 28. The output of the VCO is fed back to the PFD 15 as a frequency divider signal 25 via a programmable frequency divider 21. The programmable frequency divider 21 is normally in the form of a multi-modulus frequency divider.

The action of the synthesiser 29 is such that the frequency foM of the output signal from the VCO in the state of equilibrium corresponds exactly to the referencefrequency fre/ multiple stipulated by the frequency divider 21. In the fractional-N frequency synthesizer, the frequency fou, at the VCO output 19 is a fraction multiple of the input reference frequency //. Since the frequency divider 21 in actuality is not dividing by a fractional division ratio, but rather an integer value, fractional-N frequency synthesis is achieved through division ratio averaging, that is the division I 07 48 '« -2ratio is dynamically switched between two or more values, effectively causing the divider to divide by a non-integer number.

The delta-sigma modulator (DSM) 23 controls the division ratio of the frequency divider 21 in accordance with information in an N-bit control word x coupled to the input 22 of the DSM 23. For the purposes of understanding in Fig. 1, the input control word x includes all the necessary information to be provided to the multi-modulus frequency divider 21, including any pre-dividers. Likewise, the multi-modulus frequency divider may take on different forms and implementations and, for purposes of explanation in Fig. 1, the multi-modulus frequency divider produces the loop phase error signal 27. The clock signal 24 of the DSM is shown here as the output signal of the frequency divider 21 in Fig. 1. However, it can be frefmax is the VCO output frequency fout. As discussed further herein, it is preferable to use the output signal 24 of the frequency divider 21 as the clock signal, which ensures that the output signal of the DSM is correctly synchronized with the frequency divider.

The shape, spurious level and spurious content of the output spectrum of the fractional-N synthesizer is dependent upon the order of the DSM 23. The output noise spectral density of higher order digital delta-sigma modulators is shown to increase monotonically at greater rates and to shift quantization noise to higher frequencies. The higher out-of-band noise level is suppressed by using a loop filter, which is set one order higher than or equal to the order of the DSM. Higher order digital DSMs increase the complexity of the circuits, chip size, and power consumption. There are a number of considerations that must be taken into account to improve the performance and to minimize the fractional spurious levels. Better fractional spurious performance is achieved in some instances when a smaller channel step is used, which is achieved by adding bits to the accumulator in order to get a long sequence length at the output. However, the hardware complexity is dramatically increased when using high-bit accumulators in DSMs. 0707 48 -3Fig. 2 shows an N-bit accumulator structure and its model is shown in Fig. 3. The nonlinear difference equations governing the structure shown in Fig. 3 can be summarized as: v[«] = x[«] + w[n] (1) vM>2w j[«] = fl(v[n]) = ( w (2) λι j ν/,κ ρ |θ v w[«] = v[n -1] - 2W · y[n -1] (3) where 0 and 1 denote the output levels of a single-bit (or binary) quantizer, and Qi (·) is the quantization function.

The block diagram of the N-bit accumulator is shown in Fig. 4, where (1, N, N, 1) means 1st order, N-bit input, N-bit quantization error output, and 1-bit carry output, respectively, x, y and w are the input, cany output, and quantization error output of the modulator, respectively.

Turning to Fig. 5, a state of the art embodiment of an wth-order MASH digital deltasigma modulator is illustrated. It is comprised of m cascaded first order delta-sigma modulators designated generally as digital accumulators DSM (Ι,Ν,Ν,Ι). The N-bit input control word x corresponding to the desired channel or frequency band appears at the input line 60 of the N-bit accumulator 61 comprising the first delta-sigma modulator. The quantization error output 70 of the first modulator 61 is coupled to the input of the second N-bit accumulator 71. The quantization error output 80 of the second accumulator 71 is coupled to the input of the third accumulator. Likewise, the quantization error output 81 of the (m-/)th accumulator is coupled to the input of the mth accumulator 81.

The carry signal at the output 62 of the first N-bit accumulator 61 is coupled to the delay cell 63 with the transfer function ζ'^Ά The output 64 of this delay cell 63 is coupled to one of the inputs of the adder 65. The carry signal at the output 72 of the second N-bit accumulator 71 is coupled to the delay cell 73 with the transfer function z- The outpUt 74 of thjs deiay cen 73 is coupled to one of the inputs of another adder 76. Likewise, the carry signal at the output 83 of the wth N-bit accumulator 82 is coupled to the delay cell with the transfer function z'^^l; no delay cell is needed in this case, as shown in Fig. 5.

The carry signal output 83 of the /nth accumulator 82 is coupled to the input of the filter cell 79 with the transfer function 1-z1. The output of the filter cell is coupled to one of the inputs of an adder. The output of this adder is coupled to the input of another, and so on, until, in the second stage, it is coupled to the input 77 of the adder 76, whose output is coupled to another filter cell 69 with the transfer function 1-z'1. The output 68 of the filter cell 69 is coupled to one of the inputs of the adder 65. The output 67 of the adder 65 is coupled to the delta-sigma modulator output control lead.

The network of delay cells, filter cells, and adders that takes as inputs the m quantizer outputs yi, y2, ..., ym and produces a single output y, is known as the error cancellation network.

A 3rd-order MASH DSM is taken as an example, which comprises three cascaded first-order DSMs. The output of the MASH DSM can be expressed in the Z-domain as: Y(z) = STF(z) X(z) + NTF(z) E3(z), (4) where STF and NTF are the signal and noise transfer functions, respectively, and E3(z) is the z-transform of the error introduced by the quantizer in the third stage.

In this example, STF(z)=l and the noise transfer function is given by: NTF = (1-z'1)3. (5) -5070748 Replacing z by in (5), where /fe/is the sample frequency, one can plot the magnitude of the NTF, as shown in Fig. 6. For low frequencies, the slope of the curve is 60 dB/decade.

The simulated output spectrum of a prior 19-bit MASH DSM is shown in Fig. 7, where the slope of 60 dB/decade is again observable. Consider the deviation of the power spectrum from the linear NTF, as shown in Fig. 8, which is normalized by the sequence length of 220. The simulated power spectrum exceeds the NTF in the worst case by 13 dB. From the autocorrelation shown in Fig. 9, one finds that the sequence length is 20(l9+l) when x = 104857. The sequence length and the effective number of bits in the modulator determine the closeness of the power spectrum to the white noise linear approximation shown in Fig. 6.

In order to minimize the area and power consumption of a digital DSM (DDSM), it is desirable to reduce its hardware complexity.

Williams, III et al. (US 7176821, published Feb. 13, 20007) have presented a reduced area third-order DDSM employing multiple integration stages in tandem, a singlequantizer, and a feedback path, known to those skilled in the art as a single-quantizer output feedback DDSM. Higher order single-quantizer output feedback DDSMs are prone to stability problems.

It is desirable to provide a delta-sigma modulator for frequency synthesizer applications that achieves low phase noise, fast settling time, fine-channel resolution and wide tuning bandwidth, and to minimize the hardware requirements of the implementation.

Another object is to provide a digital MASH delta-sigma modulator for applications such as in a phase-locked loop fractional-N frequency synthesizer that achieves a prescribed spur performance but with reduced hardware complexity compared to the prior art. -6References US 6,707,855 US 7,176,821.

V. Reinhardt et al., “A Short Survey of Frequency Synthesizer Techniques,” in Proc. 40th Annual Frequency Control Symp., May 1986, pp. 355-365.

T.A. Riley et al., “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE J. Solid-State Circuits, vol, 8, pp. 553-559, May 1993.

B. Miller et al., “A Multiple Modulator Fractional Divider,” IEEE Trans. Instrum. Meas., vol. 40, no. 3, pp. 576-583, Jun. 1991.

M. Kozak et al., “Rigorous analysis of delta-sigma modulator for fractional-Ν PLL frequency synthesis,” IEEE Transactions on Circuit and Systemsl : Regular Papers, vol. 51, no. 6, pp. 1148-1162, June 2004.

M.J. Borkowski et al., “A Practical Delta-Sigma Modulator Design Method Based on Periodical Behavior Analysis,” IEEE Transactions on Circuits and Systems II : Express Briefs, vol. 52, no. 10, pp. 626-630, Oct. 2005.

B. Bomoosh et al., “Reduced Complexity 1-bit High Order Digital Delta-Sigma Modulator for Low-Voltage Fractional-N Frequency Synthesis Applications,” IEE Proc.-Circuits Devices Syst., vol. 152, no.5, pp. 471-476, Oct. 2005 K. Hosseini et al., “Mathematical Analysis of Digital MASH Delta-Sigma Modulator for Fractional-N Frequency Synthesizers,” in Proc. of PRIME 2006., pp. 309-312, Jun. 2006. -7» SUMMARY OF THE INVENTION According to the invention, there is provided a digital delta-sigma modulator comprising: a plurality of delta-sigma modulator stages cascaded in a MASH circuit topology and defining an wth order delta-sigma modulator; input means for receiving a control word; a first N|-bit modulator stage that produces a carry output and an N2-bit error quantization output, where Ni additional modulator stages each with a word length Nj that is less than or equal to that of the preceding stage, and Nj Using error masking, the bit widths of signals in the modulator stages of a MASH structure are reduced, without compromising modulator accuracy.

In one embodiment, said delta-sigma modulator comprises an Ni-bit accumulator in the first stage, and Nj-bit (N, In another embodiment: - the input means comprises an input for receiving an Nj-bit signal; - the first stage comprises a first (Ni-bit) accumulator; - the first stage provides a first carry signal output yi indicative of an overflow condition; the first stage provides an N2-bit feed forward output gi coupled to the input of a second (N2-bit) accumulator; - the second stage comprises a second (N2-bit) accumulator; the second stage provides a second carry signal output y2 indicative of an overflow condition; » 070748 -8the second stage provides an N3-bit feed forward output g; coupled to the input of a third (N3-bit) accumulator in a third stage; - a third stage provides a third carry signal output yj indicative of an overflow condition; and - the filtering means comprises means for combining the carry output signals yh y?, and yi from said three accumulators, such that the output signal y has an average value proportional to x; and N]>N2>N3, and Nj In a further embodiment, the modulator further comprises at least one inter-stage quantizer for decreasing the word length Ni between a pair of stages.

In one embodiment, said inter-stage quantizer is configured to delete a number of least significant bits.

In a further embodiment, the word lengths of the stages are chosen such that the contributions of the inter-stage quantizers to the output error are negligible compared to that of the output quantizer.

In one embodiment, the filtering means comprises adders, delay elements, and filters with transfer functions of 1-z'1, and there are three stages with word lengths Ni, N2, and N3 which satisfy the inequalities 4N| - 5N2 - 4 < 4 log2 (#) and 2Ni 3N3 - 2 < 2 log2 U).

In a further embodiment, the modulator further comprises an adder for receiving a filtered dither signal and for delivering it to the first stage.

In one embodiment, there are three stages and N2 and N3 are chosen such that the contributions of the inter-stage quantizers to the output error are masked by the output quantizer and filtered dither. -9°>07<β In another aspect, the invention provides a fractional-Ν frequency synthesizer comprising any digital delta-sigma modulator as defined above, wherein said deltasigma modulator is used for controlling a multi-modulus divider in the synthesiser.

Detailed Description of the Invention The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which Figs. 1 to 9 inclusive are referred to in the above prior art discussion and the invention is illustrated in Figs. 10 to 18, and in which:Fig. 1 is a schematic functional block diagram showing a delta-sigma based fractional-N phase locked loop frequency synthesizer; Fig. 2 is a schematic representation of a digital accumulator; Fig. 3 is a model of a digital accumulator; Fig. 4 is a block diagram representation of a digital accumulator; Fig. 5 is a block diagram representation of a conventional N-bit /nth order MASH delta-sigma modulator; Fig. 6 is a magnitude plot of the normalized linear noise transfer function (NTF) of a MASH modulator; Fig. 7 is the power spectrum plot of the output y of a conventional 19-bit MASH delta-sigma modulator; Fig. 8 is the difference between the simulated spectrum and the normalized linear NTF for a conventional 19-bit MASH delta-sigma modulator; -10®70?4β Fig. 9 is an autocorrelation plot of the output y of a conventional 19-bit deltasigma modulator; Fig. 10 is a schematic representation of a digital accumulator with an additional M-bit inter-stage quantizer; Fig. 11 is a model of a digital accumulator with an additional M-bit inter-stage quantizer; Fig. 12 is a block diagram representation of a digital accumulator with an additional M-bit inter-stage quantizer; Fig. 13 is a block diagram representation of the new (Ni, N2,...,Nm)-bit mth order MASH delta-sigma modulator; Fig. 13(A) shows the power spectra of the error signals N3(z), Nn(z) and of the new (Ni, N2, N3)-bit 3rd order MASH delta-sigma modulator; Fig. 14 is the power spectrum plot of the output 7 of a the new MASH deltasigma modulator, in the case m=3, Ni=20, N2=14, N3=12; Fig. 15 is the difference between the simulated spectrum and the normalized linear NTF for the new MASH delta-sigma modulator in the case m=3, Ni=20, N2=14, N3=12; Fig. 16 is an autocorrelation plot of the output y of the new MASH delta-sigma modulator in the case m=3, N)=20, N2=14, N3=12.; Fig. 17 is a block diagram representation of a (Ni, N2,...,Nm)-bit wth order MASH delta-sigma modulator with additive filtered input dither; and Fig. 18 is the power spectrum plot of the output y of the new MASH deltasigma modulator with additive first order filtered input dither, in the case m=3, Nl=19,N2=19,N3=10. -11The invention provides a digital MASH delta-sigma modulator (henceforth also referred to as a “DSM”) having a high-bit first stage, then further shaping the spectrum using additional modulator stages with smaller word lengths compared with the first stage.

The modulator may, for example, control a multi-modulus divider in a fractional-N frequency synthesizer. The modulator has reduced hardware complexity compared with conventional MASH delta-sigma modulators. The first stage of the DSM not only randomizes the constant input but also performs filtering. The following stages, which perform additional filtering, have fewer bits than the first stage.

The DSM comprises an N-bit modulator stage for receiving the input signal and for generating a digital output signal having N bits, of which the M Most Significant Bits (MSBs) are forwarded to the next stage as its input, where M An advantage of the DSM is that the hardware complexity is reduced due to the fact that fewer bits are required in each successive stage. A further advantage is that the power and area consumption are reduced since the hardware complexity is reduced. Another advantage is that better performance is achieved with a given amount of hardware compared with the conventional MASH DSM .

The function of the DSM is to produce or generate a long pseudo-random sequence of numbers averaging to a fraction equal to the desired fractional ratio. The sequence length is related to the number of bits in the accumulator used in the DSMs and in general it is desired to make the sequence length as long as possible. The present invention obtains a prescribed spectrum at the DSM output with reduced hardware complexity. It is intended for use with known and future types of DSM s, regardless of design or implementation or order. The DSM uses fewer bits in the accumulators in each successive DSM stage in a cascade of two or more DSMs. Thus, the DSM of the invention is economical, efficient, and practical to implement to achieve the desired benefits.

In the MASH DSM of the invention, only the first or the first few accumulators have an N-bit word. The error signal in each stage is quantized by an M-bit inter-stage quantizer Qm before feeding forward to the next stage. This is shown in Fig. 10, while the corresponding model and block diagrams are shown in Figs. 11 and 12.

The inter-stage quantizer Qm in Fig. 10 is realized simply by passing only the most significant M bits of its input to its output (and discarding the N-M least significant bits).

The other accumulators in the MASH chain use fewer bits (Ni-bit where NjN2>... >Nm and Nj In Fig. 13, the Nj-bit input control word x corresponding to the desired channel or frequency band appears at the input line 30 of the Ni-bit accumulator 31 comprising the delta-sigma modulator. The N2-bit quantization error output gi 40 of the accumulator 31 is coupled to the input of the second N2-bit accumulator 41.

The N2-bit quantization error output gi can be derived from the quantization error wj of the first accumulator by means of an inter-stage quantizer Qm that passes only the N2 most significant bits to the next stage.

The quantized output 50 of the second accumulator 41 is coupled to the input of the third Nj-bit accumulator.

The N3-bit quantization error output g2 can be derived from the quantization error w? of the second accumulator by means of an inter-stage quantizer Qm that passes only the N3 most significant bits to the next stage.

Likewise, the quantization output 51 of the (m - l)th accumulator is coupled to the input of the with accumulator 52.

The carry signal at the output 32 of the first Ni-bit accumulator 31 is coupled to the delay cell 33 with the transfer function The output 34 of this delay cell 33 is coupled to one of the inputs of the adder 35. The carry signal at the output 42 of the second accumulator 41 is coupled to the delay cell 43 with the transfer function z(m ~2>. The output 44 of this delay cell 43 is coupled to the input of another adder 46. Likewise, the carry signal at the output 53 of the wth accumulator 52 is coupled to the delay cell with the transfer function = l.

The output of the carry signal 53 of the mth accumulator 52 is coupled to the input of the filter cell 49 with the transfer function 1-z'1. The output of the filter cell is coupled to one of the inputs of an adder. The output of this adder is coupled to the input of another, and so on, until, in the second stage, it is coupled to the input 47 of the adder 46, whose output is coupled to another filter cell 39 with the transfer function 1-z'1. The output 38 of the filter cell 39 is coupled to one of the inputs of the adder 35. The output 37 of the adder 35 is coupled to the delta-sigma modulator output control lead.

In the prior art, the error cancellation network comprising the delay cells, filter cells, and adders cancels the quantization errors from all stages except the last. In the reduced complexity modulator of the invention, Y(z) = STF(z) X(z) + NTF(z) E3(z) + z'/l-z') E,2(z) + (1-z')2 E23(z) (6) = STF(z)X(z)+N3(z)+Nl2(z)+N23(z) (7) where STF and NTF are the signal and noise transfer functions, as before. E3(z) is the z-transform of the error introduced by the quantizer in the last (third) stage. Et2(z) and E23(z) are the z-transforms of the errors introduced by the inter-stage quantizers between the first and second and second and third stages, respectively. These are not cancelled by the error cancellation network. N3(z), Nj2(z), and N23(z) are the z-14- transforms of the filtered errors introduced by the third quantizer and the inter-stage quantizers between the first and second and second and third stages, respectively.

Assuming that the power spectra of the quantization errors E$(z), Eu(z) and Eh(z) are white, then the power spectra of the filtered errors Ns(z), Nj2(z), and N23O are as shown in Fig. 13(A).

If the input x is odd and constant, then the first spectral components of Ε^(ζ) and E23(z) occur at fu and f23, where fn = l/2(N!'N2) and/23 = 1/2'N3), respectively.

Furthermore, if the spectra of Νπ(ζ) and N23(z) lie below that of JVjfz) at fy and /23,, respectively, then Y(z) ^STF(z) X(z) + N3(z), (8) where « denotes “approximately equal to”, and Nu(z) and N23(z), although not cancelled, are “masked” by the larger N3(z).

Specifically, the noise-shaped errors due introduced by the reduction in bit widths can be masked by the larger noise-shaped error Ns(z) component if the integer values of the word lengths N/, N2 and N3 are chosen such that: 4Ni - 5N2 -4 < 4 log2 (λ) and 2Nj SN3 -2 <2 log2 (λ) . (9) In order to compare the performance of the new topology with the conventional one, simulation results for an example of the new MASH delta-sigma modulator are presented. Since the maximum output sequence length for the first order delta-sigma modulator is 2\ a 20-bit first accumulator is required to obtain the same maximum sequence length 220 as a conventional 19-bit MASH delta-sigma modulator. Additionally, the maximum output sequence length for the first-order delta-sigma modulator can be achieved when the input is odd and has no relationship with the initial condition. Therefore, we set the LSB of the input to “1” to ensure that the -15°7074ί maximum output sequence length will always be achieved. Applying (9), a 14-bit accumulator and a 12-bit accumulator are used after the first 20-bit accumulator to perform the noise shaping, i.e. Ni=20, N2=14, N3=12.

The resulting output power spectrum is shown in Fig. 14. The expected 60 dB/decade slope is observed. The peak deviation from the linear NTF model of only 4 dB in Fig. 15 is 9 dB less than in the case of the conventional 19-bit modulator. The autocorrelation result shown in Fig. 16 confirms the expected sequence length of 2 .

In this topology, while the same output sequence length is obtained as the conventional 19-bit delta-sigma modulator, less hardware is used and the spectral spurs are lower.

In the embodiment described above, we have augmented the number of bits in the first stage and have made the input odd in order to maximize the sequence length. The sequence length can be maximized by a number of other means, including additive filtered LSB input dither.

A reduced complexity delta-sigma modulator with additive filtered input dither is shown in Fig. 17. Here, a dither signal d is applied to the input 111 of a filter 113 with transfer function V(z). The input x is applied to the first input 101 of an adder 104. The output 112 of the filter is applied to the second input 102 of the adder. The output 103 of the adder is applied to the input 30 of the MASH delta-sigma modulator described in Fig. 13.

In the reduced complexity modulator with additive filtered dither, the output is defined by Y(z) = STF(z) X(z) + NTF(z) E3(z) + +(1-+) E,2(z) + (1-+)2 E23(z) + STF(z) V(z)D(z) = STF(z) X(z) + N3(z) + N,2(z) + N23(z) + STF(z) V(z)D(z), (10) (11) -16•'Ο where STF and NTF are the signal and noise transfer functions, as before. E3(z) is the z-transform of the error introduced by the quantizer in the third stage. Ei2(z) and E23(z) are the z-transforms of the errors introduced by the inter-stage quantizers between the first and second and second and third stages, respectively, as before. N3(z), Nnfz), and N33(z) are the z-transforms of the filtered errors introduced by the third quantizer and the inter-stage quantizers between the first and second and second and third stages, respectively.

V(z) is the transfer function of the filter 113 and D(z) is the z-transform of the dither signal.

Additive filtered dither causes the output Y(z) [defined by equation (11)] to contain an extra term compared to equation (7). In this case, error masking can be used to hide the noise-shaped quantization errors Ni3(z) and N23(z) below [N3(z) + STF(z) V(z)D(z)] such that Y(z) ^STF(z) X(z) + N3(z) + STF(z) V(z)D(z). (11) Fig. 18 shows the power spectrum plot of the output^ of the delta-sigma modulator with additive first order filtered input dither, in the case m=3, N)=19, N2=19, N3=10. In this example, V(z) = (1-z'1).

The digital MASH delta-sigma modulator of the invention may be used in a fractional-N frequency synthesizer having the same architecture as shown in Fig.l, the DSM of the invention replacing that of the prior art. It will be understood that numerous modifications may be made to the example described above by those skilled in the art, for example, other delta-sigma modulator circuit topologies may be used, other choices of word lengths may be used in the accumulators, fewer bits may be used in each successive stage in the case of modulators with more than two stages, and the order of the delta-sigma modulators may be higher than the exemplary third order described herein, without departing from the spirit and scope of the invention. Therefore, the invention has been described by way of illustration rather than limitation.

The invention is not limited to the embodiments described but may be varied in construction and detail.

Claims

1. A digital delta-sigma modulator comprising: a plurality of delta-sigma modulator stages cascaded in a MASH circuit topology and defining an with order delta-sigma modulator; input means for receiving a control word; a first Ni-bit modulator stage that produces a carry output and an N2-bit error quantization output, where N2 additional modulator stages each with a word length Ni that is less than or equal to that of the preceding stage, and Nj

2. A digital delta-sigma modulator as claimed in claim 1, wherein said deltasigma modulator comprises an N|-bit accumulator in the first stage, and Nj-bit (Nj

3. A digital delta-sigma modulator as claimed in claims 1 or 2, wherein: - the input means comprises an input for receiving an N ( -bit signal; - the first stage comprises a first (Ν i -bit) accumulator; - the first stage provides a first carry signal output yi indicative of an overflow condition; - the first stage provides an N2-bit feed forward output gi coupled to the input of a second (N2-bit) accumulator; - the second stage comprises a second (N2-bit) accumulator; - the second stage provides a second carry signal output y 3 indicative of an overflow condition; - the second stage provides an N3-bit feed forward output g2 coupled to the input of a third (Nj-bit) accumulator in a third stage; - a third stage provides a third carry signal output y 3 indicative of an overflow condition; and -19the filtering means comprises means for combining the carry output signals yi,y 2 , andy 3 from said three accumulators, such that the output signal y has an average value proportional to x; and N] >N2>N 3 , and Nj

4. A digital delta-sigma modulator as claimed in any preceding claim, further comprising at least one inter-stage quantizer for decreasing the word length Nj between a pair of stages.

5. A digital delta-sigma modulator as claimed in claim 4, wherein said interstage quantizer is configured to delete a number of least significant bits.

6. A digital delta-sigma modulator as claimed in any preceding claim wherein the word lengths of the stages are chosen such that the contributions of the inter-stage quantizers to the output error are negligible compared to that of the output quantizer.

7. A digital delta-sigma modulator as claimed in any preceding claim, wherein the filtering means comprises adders, delay elements, and filters with transfer functions of 1-z' 1 , and there are three stages with word lengths Νι, N2, and N 3 which satisfy the inequalities 4Ni - 5N2 - 4 < 4 log2 (π) and 2N| -3N 3 - 2 < 2 log2 (π).

8. A digital delta-sigma modulator as claimed in any of claims 1 to 6, further comprising an adder for receiving a filtered dither signal and for delivering it to the first stage.

9. A digital delta-sigma modulator as claimed in claim 8, wherein there are three stages and N2 and N 3 are chosen such that the contributions of the inter-stage quantizers to the output error are masked by the output quantizer and filtered dither.

10. A fractional-N frequency synthesizer comprising a digital delta-sigma modulator as claimed in any preceding claim, wherein said delta-sigma modulator is used for controlling a multi-modulus divider in the synthesiser.