WO2008041519A1 - Procédé de fabrication d'un semi-conducteur au nitrure - Google Patents

Procédé de fabrication d'un semi-conducteur au nitrure Download PDF

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Publication number
WO2008041519A1
WO2008041519A1 PCT/JP2007/068391 JP2007068391W WO2008041519A1 WO 2008041519 A1 WO2008041519 A1 WO 2008041519A1 JP 2007068391 W JP2007068391 W JP 2007068391W WO 2008041519 A1 WO2008041519 A1 WO 2008041519A1
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gallium nitride
nitride semiconductor
layer
single crystal
gan
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PCT/JP2007/068391
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English (en)
Japanese (ja)
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Kuniyoshi Okamoto
Hiroaki Ohta
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Rohm Co., Ltd.
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Publication of WO2008041519A1 publication Critical patent/WO2008041519A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C23C16/303—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds

Definitions

  • the present invention is applicable to the production of nitride semiconductor light emitting devices (light emitting diodes, laser diodes, etc.) and nitride semiconductor electronic devices (transistors, diodes, etc.) such as power device high frequency devices.
  • the present invention relates to a method for manufacturing a physical semiconductor.
  • Semiconductors using nitrogen as a group V element in m-v group semiconductors are group m nitride semiconductors.
  • Typical examples are aluminum nitride (A1N), gallium nitride (GaN), and indium nitride (InN).
  • Al In Ga N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x y 1-x-y
  • gallium nitride semiconductor gallium nitride semiconductor
  • GaN semiconductor gallium nitride semiconductor
  • a nitride semiconductor manufacturing method is known in which a group III nitride semiconductor is grown on a gallium nitride (GaN) substrate having a c-plane as a main surface by metal organic chemical vapor deposition (MOCVD).
  • MOCVD metal organic chemical vapor deposition
  • a GaN semiconductor multilayer structure having an N-type layer and a P-type layer can be formed, and a light-emitting device using this multilayer structure can be fabricated.
  • Such a light emitting device can be used as a light source of a backlight for a liquid crystal panel, for example.
  • the main surface of the GaN semiconductor regrowth on the GaN substrate having the c-plane as the main surface is the c-plane.
  • the light extracted from the c-plane is in a randomly polarized (non-polarized) state. For this reason, when entering the liquid crystal panel, other than the specific polarized light corresponding to the incident side polarizing plate is shielded, and does not contribute to the luminance toward the emission side. Therefore, there is a problem that it is difficult to realize a high brightness display (efficiency is 50% at the maximum).
  • a GaN semiconductor having a main surface other than the c-plane that is, a nonpolar (nonpolar) surface such as a-plane or m-plane, or a semipolar (semipolar) surface is grown.
  • a nonpolar (nonpolar) surface such as a-plane or m-plane, or a semipolar (semipolar) surface
  • the production of light-emitting devices is being considered!
  • a light-emitting device having a P-type layer and an N-type layer with a GaN semiconductor layer with a nonpolar or semipolar surface as the main surface is produced, strong polarization Light emission of the state is possible.
  • the conditions for forming a GaN semiconductor regrowth layer with few dislocations (crystal defects) and a good surface state on a nonpolar or semipolar surface are extremely severe. More specifically, when a GaN semiconductor is regrowth on a GaN substrate with the c-plane as the main surface, the V / III ratio, which is the ratio (molar ratio) of the nitrogen source to the gallium source, is about 3000.
  • the MOCVD method is applied.
  • the nonpolar surface is not stable compared to the c-plane
  • a buffer layer is formed on the GaN substrate, and the GaN semiconductor layer is regrown by MOCVD on this buffer layer.
  • the proposed force S in this case, a lot of dislocations from the buffer layer surface penetrates and prevents the growth of a GaN semiconductor layer with good crystallinity.
  • Non-Patent Document 1 T. Takeuchi et al., Jap. J. Appl. Phys. 39, 413-416, 2000
  • Non-Patent Document 2 A. Chakraborty, B. A. Haskell, H. S. Keller, J. S. Speck, S. P. DenBa ars, S. Nakamura and U.. Mishra: Jap. J. Appl. Phys. 44 (2005) L173
  • An object of the present invention is to provide a nitrogen nitride that is flat and has extremely few crystal defects (preferably without dislocations). It is an object of the present invention to provide a nitride semiconductor manufacturing method capable of forming a gallium arsenide semiconductor layer on a gallium nitride substrate having a main surface other than the c-plane.
  • the present invention provides a method of growing a group III nitride semiconductor on a gallium nitride single crystal substrate having a principal surface other than the c-plane by metal organic chemical vapor deposition.
  • This method uses a condition in which the ratio (molar ratio) of the nitrogen source to the group II element raw material (specifically, the gallium source) is a v / m ratio of 1000 or more, and the v / m ratio
  • a gallium nitride semiconductor is grown by an organic metal chemical vapor deposition method (preferably 0.1 ⁇ or more) without interposing a buffer layer on the surface of the gallium nitride single crystal substrate that uses conditions. Includes semiconductor growth process.
  • an organometallic chemical vapor is used under the condition of a v / m ratio of 1000 or more, which has been conventionally considered inappropriate, using a gallium nitride single crystal substrate having a principal surface other than the c-plane.
  • a flat and dislocation-free gallium nitride semiconductor crystal can be grown without using a buffer layer. That is, for example, as in the case of growth of a gallium nitride semiconductor on a substrate having a C-plane as a main surface, a dislocation-free flat gallium nitride semiconductor crystal is grown under the condition of a v / m ratio of 3000 or more.
  • the grown gallium nitride semiconductor has, as a main surface, a surface other than the c-plane which is a polar surface, that is, a nonpolar surface or a semipolar surface. Therefore, if a light emitting device is manufactured using this gallium nitride semiconductor layer, strongly polarized light can be extracted. However, since the crystallinity of the gallium nitride semiconductor is good, high external quantum efficiency can be realized without impairing the theoretically predicted performance.
  • the gallium nitride semiconductor growth step includes a step of stacking and growing a plurality of gallium nitride semiconductor layers under the condition that the V / III ratio is 1000 or more.
  • the v / m ratio is 3000 or more.
  • V preferably a process of growing a gallium nitride semiconductor.
  • the method includes a step of raising the temperature of the gallium nitride single crystal substrate to 1000 ° C. to 1100 ° C. while supplying at least a nitrogen source gas to the gallium nitride single crystal substrate. Furthermore, it is preferable to include. According to this method, the substrate temperature can be raised to 1000 ° C. to 1100 ° C. while supplying the nitrogen source gas, and subsequent gallium nitride semiconductor crystal growth can be performed while suppressing the surface roughness of the substrate.
  • the gallium nitride semiconductor growth step includes a step of growing a stacked structure having an N-type layer and a P-type layer.
  • an electronic device having an N-type layer and a P-type layer can be manufactured.
  • a light emitting device having a light emitting layer is manufactured, a device capable of polarized light emission with excellent external quantum efficiency can be realized.
  • the main surface of the gallium nitride single crystal substrate is preferably a nonpolar (nonpolar) surface or a semipolar (semipolar) surface, and the off angle from each surface orientation is preferably within ⁇ 1 °.
  • Off-angular force on the main surface of the gallium nitride single crystal substrate Soil is within 1 ° with respect to the surface orientation of the nonpolar surface, or within ⁇ 1 ° with respect to the surface orientation of the semipolar surface.
  • a flat gallium nitride semiconductor crystal can be grown.
  • the main surface of the gallium nitride single crystal substrate is preferably an m-plane.
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of a light-emitting diode according to an embodiment of the present invention.
  • FIG. 2 is an illustrative view showing a unit cell of a crystal structure of a group m nitride semiconductor.
  • FIG. 3 is an illustrative view for explaining the configuration of a processing apparatus for growing each layer constituting the GaN semiconductor layer.
  • FIG. 4A is an electron micrograph showing an example of device fabrication by the present inventor, showing a layer cross section on the a-plane.
  • FIG. 4B is an electron micrograph showing an example of device fabrication by the present inventor, with the layer cross section enlarged on the a-plane.
  • FIG. 4C is an optical micrograph showing a device fabrication example by the present inventor, showing the surface of the GaN semiconductor layer.
  • FIG.5 GaN semiconductor layer grown on m-plane GaN single crystal substrate with 2 ° off angle It is the optical microscope photograph which image
  • FIG. 6 shows the results of measuring the electroluminescence (EL) characteristics of the light-emitting diode element having the configuration of this embodiment.
  • FIG. 7 shows EL spectra for various drive currents in the light-emitting diode element.
  • FIG. 8 is an illustrative view for illustrating the structure of a light emitting diode according to a second embodiment of the invention.
  • FIG. 9 is an illustrative view for illustrating the structure of a light emitting diode according to a third embodiment of the invention.
  • FIG. 10 is an illustrative view for explaining the structure of a light emitting diode according to a fourth embodiment of the invention.
  • Metal post 21 ⁇ ⁇ -type contact layer, 21 & ⁇ ⁇ -type contact layer surface (GaN semiconductor layer surface: mirror surface), 22 ⁇ Quantum well layer, 23 ⁇ ⁇ -type electron blocking layer, 24 ⁇ ⁇ Contact type layer, 25 ⁇ Finanorenolia layer, ⁇ Processing chamber, 31 ⁇ Heater, 32 ⁇ Susceptor, 33 ⁇ Rotating wheel, 34 ⁇ Rotating drive mechanism, 35 ⁇ Wafer, 36 ⁇ Exhaust piping, 40 ⁇ Material gas supply passage, 41 ⁇ , Indium raw material piping, 45 ... Magnesium material piping, 46 ⁇ Silicon material piping
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of a light emitting diode according to an embodiment of the present invention.
  • This light emitting diode is configured by growing a GaN semiconductor layer 2 as a group III nitride semiconductor layer on a GaN (gallium nitride) single crystal substrate 1! /.
  • GaN half The conductor layer 2 includes, in order from the GaN single crystal substrate 1 side, an N-type contact layer 21, a quantum well (QW) layer 22 as a light emitting layer, a GaN final barrier layer 25, a P-type electron blocking layer 23, and It has a laminated structure in which P-type contact layers 24 are laminated.
  • QW quantum well
  • An anode electrode 3 as a transparent electrode is formed on the surface of the P-type contact layer 24, and a connection portion 4 for wiring connection is joined to a part of the anode electrode 3.
  • a force sword electrode 5 is joined to the N-type contact layer 21. Thus, a light emitting diode structure is formed.
  • the GaN single crystal substrate 1 is bonded to a support substrate (wiring substrate) 10.
  • Wirings 11 and 12 are formed on the surface of the support substrate 10.
  • the connecting portion 4 and the wiring 11 are connected by a bonding wire 13, and the force sword electrode 5 and the wiring 12 are connected by a bonding wire 14.
  • the light emitting diode element is configured by sealing the light emitting diode structure and the bonding wires 13 and 14 with a transparent resin such as an epoxy resin.
  • the N-type contact layer 21 is composed of an N-type GaN layer to which silicon is added as an N-type dopant.
  • the layer thickness is preferably 3 m or more.
  • the doping concentration of silicon is, for example, 10 cm.
  • the quantum well layer 22 is formed by alternately laminating InGaN layers doped with silicon (for example, 3 nm thick) and GaN layers (for example, 9 nm thick) for a predetermined period (for example, 5 periods).
  • a GaN final barrier layer 25 (for example, 40 nm thick) is laminated between the quantum well layer 22 and the P-type electron blocking layer 23.
  • the P-type electron blocking layer 23 is composed of an AlGaN layer to which magnesium as a P-type dopant is added.
  • the layer thickness is, for example, 28 nm.
  • the doping concentration of magnesium is, for example, 3 ⁇ 10 19 cm ⁇ 3 .
  • the p-type contact layer 24 is composed of a GaN layer to which magnesium as a P-type dopant is added at a high concentration.
  • the layer thickness is, for example, 70 nm.
  • Doping concentration of magnesium For example other, it is 10 2 ° cm_ 3.
  • the surface 2a is a light extraction side surface from which light generated in the quantum well layer 22 is extracted.
  • the anode electrode 3 is composed of a transparent thin metal layer (for example, 200 A or less) composed of Ni (refractive index 1.8) and Au (refractive index 1.6). Since the surface 2a of the GaN semiconductor layer 2 is a mirror surface, the surface 3a (light extraction side surface) of the anode electrode 3 formed in contact with the surface 2a is also a mirror surface. That is, the unevenness of the surface 3a is, for example, l OOnm or less.
  • the refractive index of the anode electrode 3 is n (n is from 1.6 to 1.8) and the emission wavelength is calculated, if the unevenness of the surface 3a is less than or equal to ⁇ / ⁇ , this unevenness is substantially It can be said that the mirror surface does not affect the surface.
  • the light extraction side surface 2a of the GaN semiconductor layer 2 and the light extraction side surface 3a of the anode electrode 3 are both mirror surfaces, the light generated from the quantum well layer 22 has almost no influence on the polarization state. It will be taken out to the anode electrode 3 side without giving.
  • the force sword electrode is a film composed of a Ti layer and an A1 layer.
  • the GaN single crystal substrate 1 is a GaN single crystal substrate having a main surface other than the c-plane. More specifically, the main surface is a nonpolar surface or a semipolar surface. More specifically, the main surface of the GaN single crystal substrate 1 is a surface having an off angle within ⁇ 1 ° from the plane orientation of the nonpolar plane, or within ⁇ 1 ° from the plane orientation of the semipolar plane. A surface having an off angle.
  • FIG. 2 is an illustrative view showing a unit cell having a crystal structure of a group III nitride semiconductor.
  • the crystal structure of group III nitride semiconductors can be approximated by a hexagonal system, and the surface (the top surface of the hexagonal column) force S c plane (0001) is normal to the c axis along the axial direction of the hexagonal column. is there.
  • the polarization direction force is along the axis.
  • the c-plane is called a polar plane because it exhibits different properties on the + c-axis side and the c-axis side.
  • the side surfaces of the hexagonal cylinder are m-planes (10-10), respectively, and are surface force surfaces (11-20) that pass through a pair of ridge lines that are not adjacent to each other.
  • These are crystal planes perpendicular to the c-plane and orthogonal to the polarization direction, so they are nonpolar planes, that is, non-polar planes.
  • the crystal plane tilted with respect to the c-plane (not parallel nor perpendicular) intersects the polarization direction diagonally, so that it has a slightly polar plane, that is, It is a semipolar plane.
  • Semipolar Specific examples of the property surface include surfaces such as the (10-; 1-1) surface, the (10-; 1-3) surface, and the (11-22) surface.
  • Non-Patent Document 1 shows the relationship between the declination of the crystal plane relative to the c-plane and the polarization in the normal direction of the crystal plane. From this non-patent document 1, the (11-24) plane, (10-12) plane, etc. are also crystal planes with little polarization, and are promising crystals that may be used to extract light in a large polarization state. It can be said that it is a surface.
  • a GaN single crystal substrate with the m-plane as the main surface can be produced by cutting it from a GaN single crystal with the c-plane as the main surface.
  • the m-plane of the cut substrate is polished by, for example, a chemical mechanical polishing process, and the orientation error for both the (0001) direction and the (11 20) direction is within ⁇ 1 ° (preferably ⁇ 0.3 ° Within).
  • a GaN single crystal substrate having the m-plane as the main surface and free from crystal defects such as dislocations and stacking faults can be obtained. There is only an atomic level step on the surface of such a GaN single crystal substrate.
  • a light emitting diode (LED) structure is grown on the GaN single crystal substrate thus obtained by MOCVD.
  • FIG. 3 is an illustrative view for explaining the configuration of a processing apparatus for growing each layer constituting the GaN semiconductor layer 2.
  • a susceptor 32 including a heater 31 is disposed in the processing chamber 30.
  • the susceptor 32 is coupled to a rotation shaft 33, and the rotation shaft 33 is rotated by a rotation drive mechanism 34 disposed outside the processing chamber 30.
  • a rotation drive mechanism 34 disposed outside the processing chamber 30.
  • An exhaust pipe 36 is connected to the processing chamber 30.
  • the exhaust pipe 36 is connected to an exhaust facility such as a rotary pump.
  • the pressure in the processing chamber 30 is set to 1/10 atm to normal pressure (preferably about 1/5 atm), and the atmosphere in the processing chamber 30 is always exhausted.
  • a raw material gas supply path 40 for supplying a raw material gas toward the surface of the wafer 35 held by the susceptor 32 is introduced into the processing chamber 30! /.
  • the source gas supply path 40 includes an ammonia source pipe 41 for supplying ammonia as a nitrogen source gas, a gallium source pipe 42 for supplying trimethylgallium (TMG) as a gallium source gas, and trimethyl as an aluminum source gas.
  • TMA1 Aluminum raw material to supply aluminum (TMA1) Piping 43, Indium raw material piping 44 for supplying trimethylindium (TMIn) as an indium raw material gas, Magnesium raw material piping 45 for supplying ethylcyclopentadiene magnesium (EtCp Mg) as a magnesium raw material gas, and , As silicon source gas
  • a silicon raw material pipe 46 for supplying all silane (SiH) is connected.
  • Valves 5;! -56 are installed in the self-tube 4;!-46, respectively.
  • Each source gas is supplied together with a carrier gas composed of hydrogen, nitrogen, or both.
  • a GaN single crystal wafer having an m-plane as a main surface is held on the susceptor 32 as a wafer 35.
  • the valves 52 to 56 are closed, the ammonia material valve 51 is opened, and carrier gas and ammonia gas (nitrogen material gas) are supplied into the processing chamber 30.
  • the heater 31 is energized, and the wafer temperature is raised to 1000 ° C. to 1100 ° C. (for example, 1 050 ° C.).
  • the force S can be used to grow GaN semiconductors without causing surface roughness.
  • gallium raw material anolev 52 and silicon raw material anolev 56 are opened.
  • ammonia, trimethylgallium and silane are supplied from the raw material gas supply path 40 together with the carrier gas.
  • an N-type contact layer 21 made of a GaN layer doped with silicon grows on the surface of the wafer 35.
  • the silicon source valve 56 is closed, and the quantum well layer 22 is grown.
  • the quantum well layer 22 is grown by the steps of growing the InGaN layer by opening the ammonia source valve 51, the gallium source valve 52 and the indium source valve 54 and supplying ammonia, trimethylgallium and trimethylindium to the wafer 35.
  • the indium source valve 54 is closed, the ammonia source valve 51 and the gallium source valve 52 are opened, and ammonia and trimethylgallium are supplied to the wafer 35, so that an additive-free GaN layer is grown alternately. You can do that. For example, a GaN layer is formed first, and then an InGaN layer is formed on it.
  • the GaN final barrier layer 25 is formed on the InGaN layer.
  • the temperature of the wafer 35 is, for example, 700 ° C.
  • the P-type electron blocking layer 23 is formed. That is, the ammonia material valve 51, the gallium material valve 52, the aluminum material valve 53 and the magnesium material valve 55 are opened, and the other valves 54 and 56 are closed. As a result, ammonia, trimethylenogallium, trimethylaluminum, and ethylcyclopentagenyl magnesium are supplied toward the wafer 35, and a P-type electron blocking layer 23 made of an AlGaN layer doped with magnesium is formed. It will be.
  • the temperature of the wafer 35 is preferably set to 1000 ° C. to 1100 ° C. (for example, 1000 ° C.).
  • the P-type contact layer 24 is formed. That is, the ammonia material valve 51, the gallium material valve 52, and the magnesium material valve 55 are opened, and the other valves 53, 54, and 56 are closed. As a result, ammonia, trimethylgallium, and ethylcyclopentagenylmagnesium were supplied toward the wafer 35 and doped with magnesium.
  • a P-type contact layer 24 made of a GaN layer is formed.
  • the temperature of the wafer 35 is preferably set to 1000 ° C to 1100 ° C (for example, 1000 ° C).
  • the wafer 35 is transferred to an etching apparatus, and an N-type contact layer 21 is formed by plasma etching, for example, as shown in FIG.
  • a recess 7 for exposure is formed.
  • the recess 7 may be formed so as to surround the quantum well layer 22, the P-type electron blocking layer 23, and the P-type contact layer 24 in an island shape, whereby the quantum well layer 22, the P-type electron blocking layer 23, and the P-type
  • the mold contact layer 24 may be shaped into a mesa shape.
  • anode electrode 3, the connection portion 4, and the force sword electrode 5 are formed by a metal vapor deposition apparatus using resistance heating or an electron beam.
  • the force S can be obtained to obtain the light emitting diode structure shown in FIG.
  • Such a high V / III ratio has been applied to the growth of GaN crystals with the c-plane as the main surface, S, and can be applied to the growth of group III nitride semiconductor layers with a surface other than the c- plane as the main surface. No reports have been made.
  • such a high V / III ratio is used, and an m-plane or the like without a buffer layer interposed between the GaN single crystal substrate 1 and the GaN semiconductor layer 2 is a main surface.
  • the GaN semiconductor layer 2 grows flat in a dislocation-free state.
  • FIG. 4A, 4B, and 4C are photomicrographs showing examples of device fabrication by the present inventors.
  • a GaN semiconductor layer 2 having an m-plane as a main surface is grown on a GaN single crystal substrate 1 having an m-plane as a main surface.
  • 4A and 4B are electron microscope (STEM: scanning transmission electron microscope) photographs showing a cross section along the a-plane, and the left-right direction of the photographs is parallel to the c-axis.
  • Figure 4B is an enlarged photograph of the vicinity of the quantum well layer 22.
  • FIG. 4C is an optical micrograph of the surface of the N-type contact layer 21 before the anode electrode 3 is formed. From these FIG. 4A, FIG. 4B, and FIG.
  • the surface state is flat (in this example, mirror surface).
  • the m-plane GaN semiconductor layer 2 having a dislocation-free and flat surface state can be grown.
  • the low V / III ratio which has been conventionally required, is unnecessary.
  • the off-angle of the main surface of the GaN single crystal substrate 1 must be controlled within the aforementioned range. Since the surface 2a of the GaN semiconductor layer 2 is flat, the surface 3a of the anode electrode 3 formed on the surface 2a is also a flat surface.
  • FIG. 5 is an optical micrograph showing the surface state when a GaN semiconductor layer is grown on an m-plane GaN single crystal substrate with an off angle of 2 °.
  • the GaN crystal grows in a terrace shape, and it is not possible to achieve a flat surface state as when the off angle is within ⁇ 1 °.
  • FIG. 6 shows the results of measurement of the electoric luminescence (EU characteristics) of the light-emitting diode element having the configuration of this embodiment.
  • the curve L1 shows various continuous wave (CW) driving currents (Forward Current). Shows EL Output Power, shows curve 2 shows the external quantum efficiency for various continuous wave drive currents.
  • CW continuous wave
  • Shows EL Output Power shows curve 2 shows the external quantum efficiency for various continuous wave drive currents.
  • the EL output power is 1 ⁇ 79mW, and the external quantum efficiency at this time is 3.1%.
  • This EL output power is, for example, 7 times larger than the value reported in Non-Patent Document 2! /, Which is 240 ⁇ W at a drive current of 20 mA. This high EL output power is thought to have been brought about by the reduction of dislocations.
  • the EL output node has a good linearity with respect to the increase of the drive current up to 100mA.
  • the internal quantum efficiency (ratio of the emission intensity at 300K to the emission intensity at 12K) was measured by photoexcitation with a He-Cd laser with a wavelength of 325nm and was 5.5%.
  • Figure 7 shows the EL spectra for various drive currents.
  • the horizontal axis is wavelength (Wavelength), and the vertical axis is EL intensity (EL Intensity) in arbitrary units.
  • the peak wavelength at a drive current of 20 mA is 435 nm (blue region).
  • the peak wavelength at a drive current of 1 mA is 437 nm, and the peak wavelength at a drive current of 100 mA is 434 nm. That is, the peak wavelength variation due to the drive current is 3 nm.
  • the unevenness of the surface 2a of the GaN semiconductor layer 2 and the surface 3a of the anode electrode 3 is not more than lOOnm, so that it hardly affects the polarization of light in the wavelength region.
  • FIG. 8 is an illustrative view for illustrating the structure of a light emitting diode according to a second embodiment of the present invention. In FIG. 8, portions corresponding to the respective portions shown in FIG. 1 are denoted by the same reference numerals.
  • the GaN single crystal substrate 1 is removed by a grinding process or the like. As a result, the N-type contact layer 21 is exposed. A force sword electrode 5 is formed on the exposed surface (lower surface) of the contact layer 21. The force sword electrode 5 is bonded (die-bonded) to the wiring 12 on the support substrate 10. This supports the light emitting diode structure It is fixed to the substrate 10.
  • the anode electrode (transparent electrode) 3 formed in contact with the surface 2a on the light extraction side of the GaN semiconductor layer 2 is connected to the wiring 11 on the support substrate 10 by the bonding wire 13 through the connection portion 4. /!
  • FIG. 9 is an illustrative view for explaining the structure of a light emitting diode according to a third embodiment of the present invention.
  • portions corresponding to the respective portions shown in FIG. 1 are denoted by the same reference numerals.
  • the N-type contact layer 21 is exposed by removing the GaN single crystal substrate 1 by a grinding process or the like.
  • the surface 21a is directed to the side opposite to the support substrate 10 and serves as a light extraction surface.
  • the anode electrode 3 formed on the surface of the P-type contact layer 24 is bonded (die-bonded) to the wiring 11 on the support substrate 10.
  • the light emitting diode structure is fixed to the support substrate 10 in a posture reverse to that in the case of FIG. 1 or FIG. In this case, the anode electrode 3 does not need to be a transparent electrode.
  • a force sword electrode 5 is formed on the surface 21a of the N-type contact layer 21 so as to be joined to a part of the surface 21a.
  • the force sword electrode 5 is connected to the wiring 12 on the support substrate 10 by a bonding wire 14.
  • the surface 21a on the light extraction side of the GaN semiconductor layer 2 is a mirror surface, so that the polarization state of the light generated from the quantum well layer 22 is hardly affected. The light can be extracted outside.
  • FIG. 10 is a view for explaining the structure of a light emitting diode according to the fourth embodiment of the invention.
  • FIG. 10 parts corresponding to the respective parts shown in FIG. 9 are denoted by the same reference numerals as those in FIG.
  • the structure of this embodiment is similar to the structure of the third embodiment, and the connection structure between the N-type contact layer 21 and the wiring 12 on the support substrate 10 is different.
  • the surface 21a (light extraction side surface) located on the opposite side of the support substrate 10 of the N-type contact layer 21 is finished to a mirror surface as in the case of the third embodiment.
  • the GaN semiconductor 2 is etched (for example, plasma etching) from the support substrate 10 side until the N-type contact layer 21 is exposed, and a recess 17 is formed.
  • a force sword electrode 5 in contact with the N-type contact layer 21 is formed in the recess 17. This power sword is connected by 5 and the wiring 12 on the support substrate 10 and the force S and the metal post 18
  • the light extraction side surface 21a of the GaN semiconductor layer 2 is a mirror surface, the polarization state of the light generated from the quantum well layer 22 is hardly affected. The light can be extracted outside.
  • the present invention can also be implemented in other forms.
  • the power described in the example in which the present invention is applied to the formation of the light emitting diode structure is not limited to other light emitting devices such as laser diodes, transistors and diodes! It can also be applied to the fabrication of other electronic devices.
  • the transparent electrode made of a metal oxide film such as the force S, ZnO or ITO described in the example in which the anode electrode 3 as the transparent electrode is formed of a Ni / Au film is used. It may be applied to the node electrode 3.

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Abstract

L'invention concerne la formation d'un semi-conducteur au nitrure de groupe III sur un substrat cristallin unique en nitrure de gallium présentant un plan principal différent d'un plan c. Cette formation est mise en oeuvre à l'aide d'un procédé de dépôt chimique en phase vapeur d'un métal organique. Le procédé de l'invention comprend une étape de formation de semi-conducteur au nitrure de gallium dans laquelle le semi-conducteur au nitrure de gallium est formé par le dépôt chimique en phase vapeur d'un métal organique dans un état de rapport V/III, à savoir un état dans lequel le rapport azote / matière du groupe III est supérieur ou égal à 1000, excluant un état dans lequel le rapport V/III est strictement inférieur à 1000 et excluant la présence d'une couche tampon sur la surface du substrat cristallin unique en nitrure de gallium.
PCT/JP2007/068391 2006-09-29 2007-09-21 Procédé de fabrication d'un semi-conducteur au nitrure WO2008041519A1 (fr)

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JP2010027924A (ja) * 2008-07-22 2010-02-04 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物発光ダイオード
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JPWO2009128468A1 (ja) * 2008-04-17 2011-08-04 株式会社東芝 白色発光装置、バックライト、液晶表示装置および照明装置
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JP2010027924A (ja) * 2008-07-22 2010-02-04 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物発光ダイオード
JP4647723B2 (ja) * 2009-03-06 2011-03-09 パナソニック株式会社 窒化物半導体の結晶成長方法および半導体装置の製造方法
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CN102719887B (zh) * 2012-06-13 2014-12-10 中国电子科技集团公司第五十五研究所 一种基于氮化镓衬底的高质量氮化镓外延薄膜的生长方法
JP2016199468A (ja) * 2016-07-12 2016-12-01 住友電気工業株式会社 ＧａＮ結晶基板

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