WO2008030960A2 - Structures à déformation contrôlée dans des interconnexions de semi-conducteurs et des nanomembranes pour dispositifs électroniques étirables - Google Patents

Structures à déformation contrôlée dans des interconnexions de semi-conducteurs et des nanomembranes pour dispositifs électroniques étirables Download PDF

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Publication number
WO2008030960A2
WO2008030960A2 PCT/US2007/077759 US2007077759W WO2008030960A2 WO 2008030960 A2 WO2008030960 A2 WO 2008030960A2 US 2007077759 W US2007077759 W US 2007077759W WO 2008030960 A2 WO2008030960 A2 WO 2008030960A2
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WIPO (PCT)
Prior art keywords
substrate
component
stretchable
strain
semiconductor elements
Prior art date
Application number
PCT/US2007/077759
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English (en)
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WO2008030960A3 (fr
Inventor
John A. Rogers
Matthew Meitl
Yugang Sun
Heung Cho Ko
Andrew Carlson
Won Mook Choi
Mark Stoykovich
Hanqing Jiang
Yonggang Huang
Ralph G. Nuzzo
Keon Jae Lee
Seong Jun KANG
Zhengtao Zhu
Etienne Menard
Jong-Hyun Ahn
Hoon-Sik Kim
Dahl-Young Khang
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The Board Of Trustees Of The University Of Illinois
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by The Board Of Trustees Of The University Of Illinois filed Critical The Board Of Trustees Of The University Of Illinois
Priority to KR1020167032797A priority Critical patent/KR101814683B1/ko
Priority to KR1020147006478A priority patent/KR101612749B1/ko
Priority to KR1020177037238A priority patent/KR102087337B1/ko
Priority to KR1020147031584A priority patent/KR101689747B1/ko
Priority to KR20097007081A priority patent/KR101453419B1/ko
Priority to JP2009527564A priority patent/JP5578509B2/ja
Priority to EP07841968A priority patent/EP2064710A4/fr
Priority to CN2007800411276A priority patent/CN101681695B/zh
Publication of WO2008030960A2 publication Critical patent/WO2008030960A2/fr
Publication of WO2008030960A3 publication Critical patent/WO2008030960A3/fr

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0271—Mechanical force other than pressure, e.g. shearing or pulling
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/201—Integrated devices having a three-dimensional layout, e.g. 3D ICs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the stretchable component central portion is curved or arc- shaped.
  • the curve has an amplitude, such as an amplitude that is between about 100 nm and 1 mm.
  • the number of distinct component or interconnect bond regions may number more than two, such as three, four, or five, for example.
  • the central portion that is between the first and second component ends is actually subdivided into a number of bent configuration regions, so that a plurality of distinct curved portion regions not in physical contact with the substrate are formed.
  • the amplitude and/or periodicity may be constant or may vary over the entire longitudinal length of the component or interconnect.
  • the component itself may be of any shape, such as a membrane, wire, or a ribbon.
  • the ribbon may have a thickness that is between about 300 nm and 1 mm.
  • the stretchable component optionally comprises one or more materials that is a metal, a semiconductor, an insulator, a piezoelectric, a ferroelectric, a magnetosthctive material, an electrosthctive material, a superconductor, a ferromagnetic material, or a thermoelectric material.
  • the stretchable component comprises a component of a device selected from the group consisting of an electronic device, an optical device, an opto-electronic device, mechanical device and a thermal device.
  • the invention provides a stretchable component or interconnect for establishing electrical contact with device components.
  • the component or interconnect has a first end, a second end and a central portion disposed between the first and second ends.
  • the ends are bonded to a substrate, such as a flexible (e.g., stretchable) substrate, an elastomeric substrate, a rigid substrate, a substrate that is not elastomeric, or a substrate to which it is desired to print electronic devices, device components, or arrays thereof.
  • a substrate such as a flexible (e.g., stretchable) substrate, an elastomeric substrate, a rigid substrate, a substrate that is not elastomeric, or a substrate to which it is desired to print electronic devices, device components, or arrays thereof.
  • Each end of the component or interconnect may be attached to a different device component that is itself supported by the substrate.
  • the central portion of the component or interconnect is in a bent configuration and not in physical contact (e.g., not bonded) with
  • the stretchable component is an actuator of a mechanical device, wherein the central region is curved and has an amplitude that is capable of modulation by compressing or elongating said stretchable component or by applying an electric potential to said central region.
  • a useful application in this embodiment is a mechanical device that is selected from the group consisting of a microelectromechanical device, a nanoelectromechanical device, and a microfluidic device.
  • multi-axial stretching and bending is provided by incorporating any of the stretchable components disclosed herein into a device array having a plurality of components and more than two device components.
  • each component provides electrical contact between a pair of device components.
  • the device array may have a geometric configuration that is in a grid, floral, bridge or any combination thereof (e.g., one region that is in a grid, another region that is bridge).
  • further stretching and bendability control is provided by the ability to connect adjacent device components to more than one components (e.g., multiple interconnects), such as two, three, or four components.
  • a device component that is square or rectangular may be adjacent to four other device components. If each adjacent pair is connected by two interconnects, the device component will have eight interconnects extending therefrom.
  • a tuning method may comprise providing a device having a stretchable component, as disclosed herein, such as a component having a first end; a second end; and a central region disposed between the first and second ends, and that is supported by a substrate.
  • the first end and second end of the component are bonded to the substrate, and at least a portion of the central region of the component has a bent configuration and is under a level of strain.
  • the level of strain is modulated in the stretchable component by compressing, elongating and/or bending the stretchable component, thereby tuning the property of the stretchable component of the device.
  • Bonding of the device components to the substrate is by any suitable means.
  • the bonding step comprises generating a pattern of bonded and non- bonded regions of the stretchable component, wherein the bonded regions of the stretchable component are bonded to the elastomehc substrate and wherein the non- bonded regions of said stretchable component are not bonded to the elastomeric substrate.
  • non-bonded regions correspond to central regions of the stretchable components
  • the step of applying the force to the elastomeric substrate causes the central regions to bend such that at least a portion of the central region of each stretchable component is not in physical contact with the substrate.
  • the step of applying the force to the elastomeric substrate causes central regions to bend such that at least a portion of the central region of each stretchable component is not in physical contact with the substrate.
  • any of the methods or devices have an elastomeric substrate with a plurality of compliant regions and a plurality of rigid regions.
  • a substrate provides flexural rigidity of the compliant regions that is less than that of the rigid regions, and optionally have the first and second ends of each of the stretchable components bonded to at least one of the rigid regions and a central region of each of the stretchable components bonded to at least one of the compliant regions.
  • Use of this substrate type provides the capacity of achieving controllable buckling of the component based on the pattern of compliancy of the underlying substrate.
  • the step of bonding the one or more device components to said receiving surface of said elastomehc substrate is carried out before the step of applying a force to the elastomeric substrate that generates a change in the level of strain of the substrate from the first level to a second level of strain different than said first level.
  • the step of bonding is carried out after the step of applying a force to the elastomeric substrate that generates a change in the level of strain of the substrate from the first level to a second level of strain different than the first level.
  • any of the first level of strain or second level of strain is equal to 0.
  • any of the device components comprises an interconnect or an electrode.
  • the invention relates to various methods for making a buckled component or interconnect capable of establishing electrical contact with device components.
  • a pattern of bond sites is applied to an elastomeric substrate surface, the components or interconnects, or to both.
  • a force is exerted to strain the substrate and the components or interconnects contacted with the substrate.
  • the pattern of bond sites provides bonding between specific components or interconnect locations and the substrate.
  • buckled components or interconnects are generated. Varying one or more of the magnitude of prestrain, bond site patterning, geometry and spacing generates components or interconnects with different buckled or wavy geometry.
  • the component is an interconnect electrically connected to a device component.
  • a substrate that is capable of stretching up to about 100%, compressing up to about 50%, or bending with a radius of curvature as low as 5 mm, without component fracture.
  • the component is made from any suitable material, such as a metal, a semiconductor, including GaAs or Si, an insulator, a piezoelectric, a ferroelectric, a magnetosthctive material, an electrosthctive material, a superconductor, a ferromagnetic material, and a thermoelectric material.
  • the methods provide for transfer printing of the buckled components from an elastomeric substrate, such as a stamp, to a device substrate such as, for example, a curved device substrate.
  • a stretchable and bendable interconnect may be made by application of a component material to a receiving surface, such as a receiving surface having relief features, such as a wavy surface.
  • a substrate with wavy features on a surface is smoothed, such as spin-coating a polymer to partially fill the recess features.
  • the partial filling generates a smoothly-wavy substrate.
  • Components, including but not limited to metal features, are then deposited and patterned as desired onto the smoothly-wavy substrate.
  • the components on the receiving surface substrate are available for subsequent casting of a polymeric stamp against the substrate at least partially coated with the component.
  • the component is transferred to the polymeric susbstrate by removing the polymeric stamp from the substrate to make a stretchable and bendable component.
  • the interface between the component and substrate is Au/Su-8 epoxy photoresist.
  • the component may be a layered metal, for example, Au/AI.
  • the substrate may be similarly layered, for example a glass layer supporting the Su-8 layer, with the actual interface between the metal and the substrate being Au/Su-8.
  • An alternative method of making a pop-up component, such as a pop-up interconnect, on a stamp surface relies on flattening a curved substrate surface, contacting components to the flattened surface, and allowing the substrate surface to relax back to its curved geometry.
  • the method further provides spatial patterning of bond sites prior to contact, as disclosed herein.
  • the method is particularly suited for transferring interconnects and device components to a second corresponding curved substrate surface.
  • bonding means such as adhesive or adhesive precursor generates bonding between the second curved substrate and interconnect system on the first curved substrate, sufficient to permit transfer of interconnect system to the second substrate, even after the elastomehc stamp is removed.
  • any of the methods and devices of the present invention has a stamp or elastomehc substrate that is PDMS having a linear and elastic response for strains that are up to about 40%.
  • the interconnects of the present invention are optionally part of a stretchable electrode, stretchable passive matrix LED display, or a photodetector array.
  • the invention is a stretchable electronic device with any one or more interconnects made by the methods of the present invention, where the electronic device is a stretchable or bendable: electrode, passive matrix LED, solar cell, optical collector arrays, biosensor, chemical sensor, photodiode array, or semiconductor array.
  • the device component that is electrically connected to the buckled interconnect is a thin film, sensor, circuit element, control element, microprocessor, transducers, or combinations thereof.
  • interconnects are accessed by electrically connecting one end of the interconnect to a device component.
  • the invention relates to methods and structures having a wavy nanomembrane, such as a wavy semiconductor nanomembrane.
  • a wavy nanomembrane facilitates incorporation of flexibility in a device component itself (in contrast to flexibility of the interconnects that connect device components).
  • the invention is a method of making a biaxially stretchable semiconductor membrane transferring a semiconductor nanomembrane material from a first substrate to a second deformed substrate, wherein after transfer the deformed substrate is permitted to relax back to its resting configuration.
  • the thickness of the semiconductor material is between about 40 nm and 600 nm. Release of a two-dimensional deforming force generates a nanomembrane having a two-dimensional wavy structure.
  • the deforming force is generated by changing the temperature of the flexible substrate.
  • a method for making a stretchable and bendable device comprising providing a substrate having a receiving surface with relief features; smoothing the relief features by spin-coating a polymer to at least partially conformally coat the receiving surface; casting a polymeric stamp against the spin- coated substrate; removing the polymeric stamp from the substrate to expose a polymeric stamp having relief features; and depositing a device component onto the polymeric stamp surface having relief features; thereby making a stretchable and bendable component for use in a stretchable and bendable device.
  • the relief features are wavy.
  • the printable semiconductor elements each comprise a unitary inorganic semiconductor structure having a length selected from the range of about 100 nanometers to about 1000 microns, a width selected from the range of about 100 nanometers to about 1000 microns, and a thickness selected from the range of about 10 nanometers to about 1000 microns.
  • At least a portion of the printable semiconductor elements in the first device layer are spatially aligned, in electrical contact or both with at least a portion of the printable semiconductor elements in the second device layer.
  • a specific method of this aspect of the present invention further comprises the step of establishing electrical contact between at least a portion of the printable semiconductor elements in the first device layer and at least a portion of the printable semiconductor elements in the second device layer.
  • Contact printing methods of the present invention optionally provide high precision registered transfer and assembly of printable semiconductor elements in preselected positions and spatial orientations relative to one or more device components prepatterned on a device substrate.
  • Contact printing is also compatible with a wide range of substrate types, including conventional rigid or semi-rigid substrates such as glasses, ceramics and metals, and substrates having physical and mechanical properties attractive for specific applications, such as flexible substrates, bendable substrates, shapeable substrates, conformable substrates and/or stretchable substrates.
  • Contact printing assembly of printable semiconductor structures is compatible, for example, with low temperature processing (e.g., less than or equal to 298K). This attribute allows the present optical systems to be implemented using a range of substrate materials including those that decompose or degrade at high temperatures, such as polymer and plastic substrates.
  • Contact printing transfer, assembly and integration of device elements is also beneficial because it can be implemented via low cost and high-throughput printing techniques and systems, such as roll-to-roll printing and flexographic printing methods and systems.
  • the printable semiconductor elements comprise heterogeneous semiconductor elements.
  • a range of heterogeneous semiconductor elements are useful in the present invention.
  • the heterogeneous semiconductor elements comprise an inorganic semiconductor structure in combination with one or more structures comprising a material selected from the group consisting of: an inorganic semiconductor having a different composition than the inorganic semiconductor structure, an inorganic semiconductor having a different doping than the inorganic semiconductor structure, a carbon nanomaterial or film thereof, an organic semiconductor, a dielectric material, and a conductor.
  • the heterogeneous semiconductor elements comprise a combination of two different semiconductor materials selected from the group consisting of single crystal silicon, Si, Ge, SiC, AIP, AIAs, AISb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AIGaAs, AIInAs, AIInP, GaAsP, GaInAs, GaInP, AIGaAsSb, AIGaInP, SiGe and GaInAsP.
  • the heterogeneous semiconductor elements comprise the inorganic semiconductor structure in combination with a dielectric material, a conductor or both a dielectric material and a conductor.
  • a multilayer device structure fabricated by the present methods may comprise a plurality of device layers separated by one or more interlayers; wherien the device layers comprise printable semiconductor elements.
  • the device layers have thicknesses less than or equal to 1 micron and wherein the interlayers have thicknesses less than or equal to 1.5 microns.
  • methods of this aspect further comprise the step of establishing electrical contact between printable semiconductors provided in different device layers.
  • Methods of this aspect may optionally further comprise the steps of: (i) patterning one or more openings in the interlayer, thereby exposing regions of one or more of the printable semiconductor elements provided on the receiving surface of the substrate or the one or more structures provided thereon; and (ii) establishing electrical contact through the openings in the interlayer between printable semiconductor elements provided on the receiving surface of the substrate or the one or more structures provided thereon and the semiconductor elements provided on the receiving surface of the interlayer.
  • Methods of the present invention are applicable to a range of substrates including, but not limited to, flexible substrates; polymer substrates, plastic substrates, stretchable substrates; rigid substrates; semiconductor wafers and a contoured substrate.
  • the invention also includes devices and systems made using the present methods.
  • Devices and systems of the present invention include, but are not limited to, electronic devices, optical devices, electro-optical devices, microfluidic devices, microelectromechanical systems, nanoelectromechanical systems, sensors, integrated circuits, microprocessors, and memory devices.
  • the invention is a two-dimensional stretchable and bendable device.
  • the device comprises a substrate having a contact surface, where a component is bonded to at least a portion of the substrate contact surface, wherein the component has at least one relief feature region and at least one substantially flat region; wherein the relief feature region has a portion that is separated from the substrate, and the substantially flat region is at least partially bonded to the substrate.
  • the at least one relief feature region has a two-dimensional pattern of relief features on the substrate, such as a wavy pattern having a plurality of contact regions in contact with the substrate contact surface.
  • any one or both of the component or substrate receiving surface may have activated regions, such as a pattern of activated regions.
  • activate regions is used broadly to refer to means for bonding and/or means for providing buckling, such as by on or more of a pattern of adhesive sites on said substrate contact surface or said component; a selected pattern of substrate or component physical parameters, said parameter selected from one or more of: substrate or component thickness, modulus, temperature, composition, each having a spatial variation; chemical modification of the substrate surface; and regions adjacent to free edges of the component on the substrate contact surface.
  • the common theme for each of these parameters is that they either facilitate bonding between the component and substrate or provide a mechanism for generating spatially-controlled buckling of the component. For example, positioning the substantially flat region or a portion of the relief feature region to an active substrate region, the component may be controllably buckled to provide for stretchable components.
  • any of the two dimensional stretchable and bendable devices have a substantially flat region comprising an island for receiving a device component, such as an interconnect relief feature that electrically connects at least two islands.
  • any of the substrate contact or receiving surface is: flat, substantially flat, has a relief feature, has a curved portion, has a wavy portion, or is elastomeric, such as a PDMS substrate or substrate layer.
  • FIG. 2 is a photograph of a stretchable wavy/buckled electrical interconnect, formed by retrieval from a rigid substrate onto a pre-strained, stretchable PDMS rubber substrate followed by the release of the strain to induce buckling.
  • FIG. 5 provides an image of a smoothly wavy PDMS substrate generated by the methods outlined in Figs. 3-4.
  • the interconnect shown is capable of 22.6 % stretchability and has a metal interconnect that is about 900 nm thick (700 nm Al/ 200 nm Au), a wavelength of about 38 microns and an amplitude (distance from peak to valley) of about 15.6 microns.
  • B shows one end of the interconnect for establishing electrical contact with a device component.
  • the device component may be positioned in a flat portion of the substrate.
  • FIG. 8 is a schematic illustration of a process for the fabrication of a stretchable passive matrix LED display using stretchable electrodes.
  • FIG. 9 illustrates the mechanical stretchability of a passive matrix LED display with wavy electrodes.
  • FIG. 10 illustrates inorganic photodiode arrays distributed on a lens with spherical curvature. Shown: various lens shapes and angles
  • FIG. 11 illustrates the need for stretchability when a planar sheet is wrapped around a spherical surface.
  • FIG. 12 summarizes one scheme for fabricating stretchable buckled semiconductor arrays capable of conforming to spherically-curved surfaces.
  • FIG. 14 Electron microscopic images of buckled stretchable silicon arrays in a grid configuration capable of supporting device components and conforming to a curved surface.
  • the scale bar is 200 ⁇ m in A and 50 ⁇ m in B.
  • FIG. 16 Electron microscopic images of buckled stretchable silicon arrays in a floral configuration capable of supporting device components and conforming to a curved surface.
  • the scale bar is 200 ⁇ m in A and 50 ⁇ m in B.
  • FIG. 17 Electron microscopic images of buckled stretchable silicon arrays in a bridge configuration capable of supporting device components and conforming to a curved surface.
  • the scale bar is 200 ⁇ m in A and 50 ⁇ m in B.
  • FIG. 19 demonstrates the reversible behavior of the stretchable interconnects during stretching and relaxation.
  • the system is relaxed in panel 1.
  • the system is stretched as indicated by the stretching arrows in panels 2, 3 and 4.
  • the maximum stretch in panel 4 is about 10 % and results in a substantially flat interconnect for the interconnect aligned in the direction of the stretching force.
  • the system is released in panels 5-8, and panel 8 has a geometry and configuration equivalent to that shown in panel 1.
  • the scale bar is 0.2 mm.
  • FIG. 20 "Bubble stamp” or “Balloon stamp” device capable of conformal contact to curved substrates as well as flat substrates.
  • FIG. 21 Another device capable of conforming to both spherically curved and flat surfaces is a stretchable spherically-molded stamp.
  • the stamp is cast against a curved surface (in this example a concave lens) and removed.
  • the stamp is stretched to substantially flatten its surface and to which interconnects can be transferred.
  • FIG. 22 Stretchable buckled silicon arrays during a stretching cycle on a "bubble" or “balloon” stamp.
  • the interconnect between adjacent contact pads comprises two wavy interconnects (Si 290 nm in thickness).
  • the stretch test uses bubble expansion to provide multi-directional stretching. The right-most panel is under maximum stretch and the bottom two panels show that when the stretching force is removed, the interconnects relax back to their prestretched configuration shown in the top-left panel.
  • FIG. 23 Silicon printed via balloon stamps onto glass lenses coated with adhesives (PDMS or SU-8).
  • FIG. 24 summarizes processing steps for engineering 3D buckled shapes in semiconductor nanohbbons.
  • A Fabricating a UVO mask and using it to pattern the surface chemistry on a PDMS substrate.
  • B Forming buckled GaAs ribbons and embedding them in PDMS.
  • C Response of buckled GaAs ribbons to stretching and compressing.
  • FIG. 26 Side-view image of a buckled GaAs ribbon embedded in PDMS after microtoming. This image shows that the PDMS fully fills the gaps between the ribbons and the underlying substrate.
  • the PDMS prepolymer cast on the surface of these buckled ribbons is cured in an oven at 65 0 C for 4 hours.
  • FIG. 27 Optical micrographs of the side-view profiles of buckled (A and D) GaAs and (B, C) Si ribbons.
  • B Si ribbon structures formed on a PDMS substrate prestrained to 50% and patterned with W act 15 ⁇ m and W 1n : 350, 300, 250, 250, 300, and 350 ⁇ m (from left to right).
  • FIG. 28 Stretching and compressing of buckled GaAs ribbons embedded in PDMS.
  • A Images of a single buckled ribbon stretched to different levels of tensile strain (positive %). Fracture occurs near 50%.
  • B Images of a single buckled ribbon compressed to different levels of compressive strain (negative %). Small, short period wavy geometries appear at the peaks of the buckles for compressive strains larger than ⁇ -15%.
  • the red lines and arrows in each panel indicate the same positions on the same ribbons to highlight the mechanical deformations.
  • the insets provide magnified images of the sections marked with the white boxes, clearly showing the formation of cracks at high compressive strains.
  • FIG. 29 Photograph of a sample with two layer of buckled GaAs ribbons arrays.
  • the structure is fabricated in a layer by layer scheme.
  • FIG. 30 Bending of buckled ribbons on surfaces and in matrixes of PDMS.
  • A- C Optical microscopic images with low magnification (top left frames) and high magnification (right frames) and schematic illustrations (bottom left frames) of buckled GaAs ribbons on PDMS with (A) concave, (B) flat, and (C) convex surfaces.
  • the scale bars in c apply to a and b.
  • d Images of buckled ribbons embedded in PDMS (left) before and (right) after bending.
  • the top and bottom frames show the curvatures of the top and bottom surfaces, respectively.
  • the scale bars in the right images apply also to the left images.
  • FIG. 31 Characterization of stretchable metal-semiconductor-metal photodetectors (MSM PDs). A Schematic illustrations of the geometry (top), an equivalent circuit (middle), and optical images of a buckled PD before and during stretching (bottom). B Current (I) - voltage (V) curves recorded from a buckled PD that was irradiated by an IR lamp with different output intensities. I-V characteristics of PDs illuminated with constant luminance and (C) stretched or (D) compressed by different degrees.
  • MSM PDs stretchable metal-semiconductor-metal photodetectors
  • FIG. 32 A hemispherical elastomeric transfer 'stamp' can liftoff interconnected Si CMOS 'chiplets' from a conventional wafer and then transform their geometry into a hemispherical shape. The 'pop-up' interconnects between the chiplets accommodates the strains associated with this planar to curved surface transformation.
  • FIG. 33 Transfer of interconnected CMOS chiplets from a hemispherical stamp to a matched hemispherical device substrate.
  • the photocurable adhesive layer bonds to the CMOS to the device substrate and also planarizes the surface.
  • FIG. 34 Printer apparatus with fixtuhng, actuators and vision systems compatible with hemispherical stamps.
  • FIG. 35 Compressible array of single crystal silicon islands electrically connected by 'pop up' ribbon interconnects, on a hemispherical stamp.
  • FIG. 36 Optical images of an array of interconnected single crystal silicon islands 'inked' onto the surface of a hemispherical stamp with radius of curvature ⁇ 2 cm.
  • FIG. 37 Stress/strain curves for various silicone elastomers that can be used for the hemispherical stamps. Linear, purely elastic responses for strains less than 20% are important.
  • FIG. 38 Finite element modeling of the spherical to planar transformation in a hemispherical stamp with an initially uniform thickness of 0.57 mm.
  • FIG. 39 Schematic illustration of steps for fabricating two-dimensional, "wavy" semiconductor nanomembranes on elastomeric supports.
  • FIG. 40 (a-f) Optical micrographs of 2D wavy structures in silicon nanomembranes at various stages during their formation.
  • the insets show two- dimensional power spectra,
  • the thickness of the silicon is 100 nm with the lateral dimension of ca. 4 X 4 mm 2
  • the substrate is PDMS
  • the thermally induced prestrain is 3.8%.
  • FIG. 41 (a) AFM and (b-d) SEM images (tilt angle ) 60°) of a 2D wavy Si nanomembrane on PDMS.
  • the thickness of the silicon is 100 nm, and the thermal prestrain is 3.8%.
  • FIG. 43 (a) Optical micrographs of 2D wavy Si nanomembranes under different uniaxial strains, applied at three different orientations. These samples consist of Si membranes with thicknesses of 100 nm on PDMS, formed with a thermal prestrain of 3.8%. The images were collected in the relaxed state before stretching (top frames), the relaxed state after stretching (bottom frames), and at uniaxial applied tensile strains of 1.8% (top middle frames) and 3.8% (bottom middle frames), (b) Dependence of the short wavelength on applied strain in the three different directions.
  • FIG. 47 Optical micrographs of wavy structures of Si nanomembranes with shapes designed to exploit edge effects to provide 2D stretchability in interconnected arrays of flat islands.
  • the Si is 100 nm thick
  • the squares are 100 x 100 ⁇ m
  • the ribbon connections are 30 x 150 ⁇ m lines.
  • the prestrain is (a, e) 2.3% and (c, g) 15%.
  • SEM images tilt angle of 75°) of selected regions that show ribbons and squares of (a, c, e, g) are shown in (b, d, f, h), respectively.
  • the insets of high-magnification SEM images show the raised region of waves in b and d.
  • FIG. 48 is photograph of the sample of 2D wavy Si nanomembrane (100 nm thick, 4* 5 mm 2 , and 3.8 % thermal prestrain) on PDMS substrate wave (top frame), and (i) the 1 D waves at the edge, (ii) the herringbone waves at the inner region, and (iii) disordered herringbone waves at the center.
  • the scale bar is 50 ⁇ m.
  • FIG. 49 Schematic illustration of the characteristic lengths in the herringbone wave structures.
  • FIG. 52 Schematic illustration of the 'unfolding' of herringbone waves with application of uniaxial tensile strain.
  • the compressive strain ⁇ cp is due to the Poisson effect with tensile strain ⁇ st .
  • FIG. 53 Optical microscope images of the morphology change of herringbone waves during heating and cooling process as a biaxial stretching test. The test sample was prepared with 100 nm thick Si membrane and 2.9 % biaxial thermal prestrain.
  • FIG. 54 summarizes one method of fabrication of wavy stretchable electrodes by deposition on a structured wavy master, followed by casting a stamp on that master, curing the stamp, and thereby transferring the electrodes to the master upon release.
  • FIG. 55 proivdes an image of stretchable metal electrodes (Au, 300 nm thick) on wavy PDMS prepared by the methods in FIG. 4 combined with those in FIG. 54.
  • the bottom panel is a graph of measured electrical resistance data of the stretchable wavy metal electrodes as a function of applied tensile strain (up to 30%).
  • FIG. 56 is an example of an application of the present method for making flexible, stretchable iLED strip-lights.
  • A is a photomicrograph illustrating the device is capable of large bending, and in this example the bending radius is 0.85 cm.
  • B provides a cross-section (top panel, scale bar 40 ⁇ m) and a top-view (bottom panel, scale bar 3 mm) of stretchable metal on a wavy PDMS substrate. The metal is capable of stretching about 30% without significant degradation of physical properties.
  • C is a plot of the effects of local strain on the wavelength (squares, left axis) and amplitude (circles, right axis) of sinusoidally-wavy metal interconnects on PDMS (shown in B). As the strain increases, there is a corresponding increase in the wavelength and decrease in the amplitude of the metal.
  • the layers are colorized (gold: top layer; red: middle layer; blue: bottom layer; silicon: grey) for ease of viewing.
  • the channel lengths and widths are 19 and 200 ⁇ m, respectively.
  • FIG. 60 (A) Image of a printed array of 3D silicon NMOS inverters on a polyimide substrate.
  • the inverters consist of MOSFETs (channel lengths of 4 ⁇ m, load- to-driver width ratio of 6.7, and a driver width of 200 ⁇ m) on two different levels, interconnected by electrical via structures.
  • the image on the top right provides a magnified view of the region indicated by the red box in the left frame.
  • the graph on the bottom right shows transfer characteristics of a typical inverter.
  • FIG. 63 (A) Optical micrographs of three dimensional, heterogeneously integrated arrays of Si MOSFETs and SWNT TFTs on a polyimide substrate. The right inset shows a cross sectional schematic view. The electrodes (gold), epoxy (cyan), SiO2 (PEO; purple), Si (light blue: undoped; dark blue: doped), SWNTs (grey), polyimide (Pl; brown) and cured polyimide (tan) are all shown.
  • FIG. 65 (A) Schematic structure of the cross section of SWNT-Si CMOS inverter built on a silicon wafer substrate. (B) Transfer and I-V characteristics of n- channel Si MOSFET and p-channel SWNT TFT forming CMOS inverter. (C) Calculated transfer characteristics of inverter and I-V characteristics of Si and SWNT transistors.
  • FIG. 67 schematically illustrates an optical device (waveguide array) produced via the controlled buckling of an optical microstructure partially adhered to a deformable substrate.
  • FIG. 68 schematically illustrates a mechanical device (e.g., accelerometer/pressure sensor) produced via the controlled buckling of a conductive microstructure partially adhered to a deformable substrate.
  • a mechanical device e.g., accelerometer/pressure sensor
  • FIG. 69 schematically illustrates a thermal device (microbolometer) produced via the controlled buckling of a thermoresistive microstructure partially adhered to a deformable substrate.
  • Stretchable refers to the ability of a material, structure, device or device component to be strained without undergoing fracture.
  • a stretchable material, structure, device or device component may undergo strain larger than about 0.5% without fracturing, preferably for some applications strain larger than about 1 % without fracturing and more preferably for some applications strain larger than about 3% without fracturing.
  • a “component” is used broadly to refer to a material or individual component used in a device.
  • An “interconnect” is one example of a component and refers to an electrically conducting material capable of establishing an electrical connection with a component or between components. In particular, the interconnect may establish electrical contact between components that are separate and/or can move with respect to each other.
  • the interconnect is made from a suitable material. For applications where a high conductivity is required, typical interconnect metals may be used, including but not limited to copper, silver, gold, aluminum and the like, alloys. Suitable conductive materials may include a semiconductor like silicon, indium tin oxide, or GaAs.
  • Semiconductors useful in the present invention may comprise element semiconductors, such as silicon, germanium and diamond, and compound semiconductors, such as group IV compound semiconductors such as SiC and SiGe, group IM-V semiconductors such as AISb, AIAs, AIn, AIP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP, group Ml-V ternary semiconductors alloys such as Al x Gai -x As, group H-Vl semiconductors such as CsSe, CdS, CdTe, ZnO, ZnSe, ZnS, and ZnTe, group I-VII semiconductors CuCI, group IV - VI semiconductors such as PbS, PbTe and SnS, layer semiconductors such as PbI 2 , MoS 2 and GaSe, oxide semiconductors such as CuO and Cu 2 O.
  • group IV compound semiconductors such as SiC and SiGe
  • group IM-V semiconductors such
  • Specific semiconductor materials useful for in some applications of the present invention include, but are not limited to, Si, Ge, SiC, AIP, AIAs, AISb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AIGaAs, AIInAs, AIInP, GaAsP, GaInAs, GaInP, AIGaAsSb, AIGaInP, and GaInAsP.
  • Porous silicon semiconductor materials are useful for applications of the present invention in the field of sensors and light emitting materials, such as light emitting diodes (LEDs) and solid state lasers.
  • Impurities of semiconductor materials are atoms, elements, ions and/or molecules other than the semiconductor matehal(s) themselves or any dopants provided to the semiconductor material. Impurities are undesirable materials present in semiconductor materials which may negatively impact the electronic properties of semiconductor materials, and include but are not limited to oxygen, carbon, and metals including heavy metals. Heavy metal impurities include, but are not limited to, the group of elements between copper and lead on the periodic table, calcium, sodium, and all ions, compounds and/or complexes thereof.
  • an interconnect that is "stretchable” is used herein to broadly refer to an interconnect capable of undergoing a variety of forces and strains such as stretching, bending and/or compression in one or more directions without adversely impacting electrical connection to, or electrical conduction from, a device component.
  • a stretchable interconnect may be formed of a relatively brittle material, such as GaAs, yet remain capable of continued function even when exposed to a significant deformatory force (e.g., stretching, bending, compression) due to the interconnect's geometrical configuration.
  • a stretchable interconnect may undergo strain larger than about 1 %, 10% or about 30% without fracturing.
  • the strain is generated by stretching an underlying elastomehc substrate to which at least a portion of the interconnect is bonded.
  • a “device component” is used to broadly refer to an individual component within an electrical, optical, mechanical or thermal device.
  • Component can be one or more of a photodiode, LED, TFT, electrode, semiconductor, other light- collecting/detecting components, transistor, integrated circuit, contact pad capable of receiving a device component, thin film devices, circuit elements, control elements, microprocessors, transducers and combinations thereof.
  • a device component can be connected to one or more contact pads as known in the art, such as metal evaporation, wire bonding, application of solids or conductive pastes, for example.
  • Electrical device generally refers to a device incorporating a plurality of device components, and includes large area electronics, printed wire boards, integrated circuits, device components arrays, biological and/or chemical sensors, physical sensors (e.g., temperature, light, radiation, etc.), solar cell or photovoltaic arrays, display arrays, optical collectors, systems and displays.
  • Substrate refers to a material having a surface that is capable of supporting a component, including a device component or an interconnect.
  • An interconnect that is "bonded” to the substrate refers to a portion of the interconnect in physical contact with the substrate and unable to substantially move relative to the substrate surface to which it is bonded. Unbonded portions, in contrast, are capable of substantial movement relative to the substrate.
  • the unbonded portion of the interconnect generally corresponds to that portion having a "bent configuration," such as by strain-induced interconnect bending.
  • a component in "conformal contact" with a substrate refers to a component that covers a substrate and retains a three-dimensional relief feature whose pattern is governed by the pattern of relief features on the substrate.
  • Bent configuration refers to a structure having a curved conformation resulting from the application of a force.
  • Bent structures in the present invention may have one or more folded regions, convex regions, concave regions, and any combinations thereof.
  • Bent structures useful in the present invention may be provided in a coiled conformation, a wrinkled conformation, a buckled conformation and/or a wavy (i.e., wave-shaped) configuration.
  • Bent structures such as stretchable bent interconnects, may be bonded to a flexible substrate, such as a polymer and/or elastic substrate, in a conformation wherein the bent structure is under strain.
  • the bent structure such as a bent ribbon structure, is under a strain equal to or less than about 30%, a strain equal to or less than about 10%, a strain equal to or less than about 5% and a strain equal to or less than about 1 % in embodiments preferred for some applications.
  • Thermal contact refers to the ability of two materials that are capable of substantial heat transfer from the higher temperature material to the lower temperature material, such as by conduction. Bent structures resting on a substrate are of particular use in providing regions that are in thermal contact (e.g., bond regions) with the substrate and other regions that are not in thermal contact (e.g., regions that are insulated and/or physically separated from the substrate).
  • Interconnects can have any number of geometries or shape, so long as the geometry or shape facilitates interconnect bending or stretching without breakage.
  • a general interconnect geometry can be described as “buckled” or “wavy.”
  • that geometry can be obtained by exerting a force (e.g., a strain) on the interconnect by exerting a force on an underlying deformable substrate, such that a change in a dimension of the underlying substrate generates buckles or waves in the interconnect because portions of the interconnect are bonded to the substrate, and regions between the bound portions are not bonded.
  • a force e.g., a strain
  • an individual interconnect may be defined by ends that are bonded to a substrate, and a curved central portion between the ends that is not substrate-bonded.
  • the interconnect can have any cross-sectional shape.
  • One shape interconnect is a ribbon-shaped interconnect.
  • Ribbon refers to a substantially rectangular-shaped cross-section having a thickness and a width. Specific dimensions depend on the desired conductivity through the interconnect, the composition of the interconnect and the number of interconnects electrically connecting adjacent device components. For example, an interconnect in a bridge configuration connecting adjacent components may have different dimensions than a single interconnect connecting adjacent components.
  • the dimensions may be of any suitable values, so long as a suitable electrical conductivity is generated, such as widths that are between about 10 ⁇ m and 1 cm and thickness between about 50 nm to 1 , or a width to thickness ratio ranging from between about 0.001 and 0.1 , or a ratio that is about 0.01.
  • Elastomeric refers to a polymeric material which can be stretched or deformed and return, at least partially, to its original shape without substantial permanent deformation. Elastomeric substrates commonly undergo substantially elastic deformations. Exemplary elastomeric substrates useful in the present include, but are not limited to, elastomers and composite materials or mixtures of elastomers, and polymers and copolymers exhibiting elasticity.
  • the elastomeric substrate is prestrained via a mechanism providing for expansion of the elastic substrate along one or more principle axes. For example, prestraining may be provided by expanding the elastic substrate along a first axes, including expansion in a radial direction to transform a hemispherical surface to a flat surface.
  • the elastic substrate may be expanded along a plurality of axes, for example via expansion along first and second axis orthogonally positioned relative to each other.
  • Means of prestraining elastic substrates via mechanisms providing expansion of the elastic substrate include bending, rolling, flexing, flattening, expanding or otherwise deforming the elastic substrate.
  • the prestraining means also includes prestraining provided by raising the temperature of the elastic substrate, thereby providing for thermal expansion of the elastic substrate.
  • Axial strain refers to a force applied to an axis of the substrate to generate the displacement ⁇ L. Strain is also generated by forces applied in other directions, such as a bending force, a compressive force, a shearing force, and any combination thereof. Strain or compression may also be generated by stretching a curved surface to a flat surface, or vice versa.
  • Level of strain refers to the magnitude of the strain and can range from negative (corresponding to compression) to zero (relaxed state) to positive (corresponding to elongation or stretching). .
  • Young's modulus is a mechanical property of a material, device or layer which refers to the ratio of stress to strain for a given substance. Young's modulus may be provided by the expression;
  • Frracturing or “fracture” refers to a physical break in the interconnect, such that the interconnect is not capable of substantial electrical conductivity.
  • bond sites can be patterned by a variety of techniques, and may be described in terms of surface-activated (W act ) areas capable of providing strong adhesive forces between substrate and feature (e.g., interconnect) and surface-inactive (W 1n ) where the adhesive forces are relatively weak.
  • W act surface-activated
  • W 1n surface-inactive
  • a substrate that is adhesively patterned in lines may be described in terms of W act and W 1n dimensions.
  • spatial variation refers to a parameter that has magnitude that varies over a surface, and is particularly useful for providing two-dimensional control of component relief features, thereby providing spatial control over the bendability of a device or device component.
  • Heterogeneous semiconductor elements are multicomponent structures comprising a semiconductor in combination with one or more other materials or structures.
  • Other materials and structures in the context of this description may comprise elements, molecules and complexes, aggregates and particles thereof, that are different from the semiconductor in which they are combined, such as materials and/or structures having a different chemical compositions and/or physical states (e.g. crystalline, semicrystalline or amorphous states).
  • Useful heterogeneous semiconductor elements in this aspect of the invention include an inorganic semiconductor structure in combination with other semiconductor materials, including doped semiconductors (e.g., N-type and P-type dopants) and carbon nanomaterials or films thereof, dielectric materials and/or structures, and conducting materials and/or structures.
  • Heterogeneous semiconductor elements of the present invention include structures having spatial homogeneous compositions, such as uniformly doped semiconductor structures, and include structures having spatial inhomogeneous compositions, such as semiconductor structures having dopants with concentrations that vary spatially in one, two or three dimensions (i.e. a spatially inhomogeneous dopant distribution in the semiconductor element).
  • FIG. 2 is a photograph of a stretchable wavy/buckled electrical interconnect 40, formed by retrieval from a rigid substrate onto a pre-strained, stretchable PDMS rubber substrate 30, followed by release of the strain, thereby inducing buckling.
  • FIG. 3A A method for generating wavy stretchable electrodes and/or interconnects is provided in FIG. 3.
  • wavy features 22 are prepared on a substrate 20, such as by micromachining processes, for example.
  • the substrate 20 with a surface having wavy features 22 serves as a master for molding elastomer stamps 30 with a corresponding wavy surface 32.
  • Metal features 10 are deposited on the wavy surface 32, such as by evaporation through a shadow mask and/or electrodeposition.
  • Fig. 4 provides one method for fabricating a smooth wavy elastomer substrate.
  • Anisotropic Si (1 0 0) etching provides a substrate 20 having sharp-edges 24 (FIG. 4B - top panel).
  • Spin PR smooths the sharp-edged valleys by depositing PR 26 in the sharp-edged valleys 24 of substrate 20.
  • An elastomehc stamp 34 is cast against substrate 20.
  • Stamp 34 has sharp-edged recess features.
  • a second elastomehc stamp 36 is cast on stamp 34 to generate a stamp having sharp-edged peaks.
  • Stamp 36 is embossed with Su-8 50 and cured as appropriate.
  • Spin PR 26 smooths the sharp- edged valleys of 50.
  • Elastomeric substrate 30 is cast against the 50 having smooth valleys. Substrate 30 is removed to reveal a wavy and smooth surface 32.
  • FIG. 7 are photographs of a stretchable electrode.
  • FIG. 7A is a photograph of a cross-section of an elastomer substrate 30 having a wavy surface 32.
  • FIG. 7B is a top view micrograph of an electrode made by evaporating metal 10 on the wavy elastomer substrate surface 32. The image's focal plane is on the peaks of the wavy relief. In FIG. 7C, the focal plane is on the valleys of the wavy relief and the metal interconnect 10 is in electrical contact with the electrode 250.
  • the stretchable electrode is deposited by evaporation through a shadowmask onto a smoothly wavy elastomer substrate. In this example, the electrode 250 maintains conductivity and connectivity via interconnects 10 during stretching up to about 10% in tension.
  • FIG. 10 One such example of a curved electronic device is provided in FIG. 10.
  • FIG. 10 One such example of a curved electronic device is provided in FIG. 10.
  • Prestrain is provided in two directions, as illustrated.
  • the bonding is by any means known in the art such as an adhesive, for example, applied to the Si elements, the substrate, or both.
  • the bonding means is applied in a selected pattern so that the Si has bonded regions that will remain in physical contact with the substrate (after deformation) and other regions in a bent configuration that are not in physical contact with the substrate (e.g., regions that are not bonded or are weakly bonded relative to the adhesive force in the bond regions).
  • the prestrained substrate is removed from the wafer substrate to reveal a flat grid of semiconductor arrays (panel (iii)).
  • buckled interconnects 10 impart stretchability to the entire array, and specifically the capability for motion of component 60 relative to other components 60.without breaking electrical contact between components 60, thereby providing conformal capability to a curved surface or a bendable surface.
  • FIG. 13 provides an optical microscopic image of a buckled strectchable silicon array in a single grid configuration 140 (top two panels), grid configuration having a plurality of connected interconnects 160 (bottom left panel), and a floral configuration 150 (bottom right panel).
  • interconnect 10 is buckled in a central portion, with interconnect ends attached to a contact pad 70.
  • the interconnects and contact pad 70 are supported on a PDMS substrate 30.
  • Close-up views of a number of different interconnect geometries are further provided in FIGs 14-17.
  • FIG. 14 provides electron microscopic images to show a basic buckled or wavy interconnect 10 having a central portion 90 with a first end 100 and second end 110. The central portion is in a bent configuration. Ends 100 and 110 are connected to a device component, in this case a contact pad 70 capable of establishing electrical contact with a device component.
  • the interconnect 10 and contact pad 70 are supported on a substrate 30, such as an elastomehc PDMS substrate.
  • FIG. 15 is an electron microscopic image of adjacent device components (e.g., contact pad 70) connected to each other by a plurality (two) of interconnects 160. Comparing FIG. 15 to FIG. 14 demonstrates that adjacent device components 70 can be connected to one another by one or more interconnects 10 to provide additional flexibility to the electronic device. For example, a device component or contact pad 70 having a relatively large footprint is optionally connected to another device component by multiple interconnects.
  • FIG. 16 is an electron microscopic image of interconnects in a floral configuration 150.
  • a floral configuration in contrast to a grid configuration, has interconnects oriented in more than two longitudinal directions. In this example, there are four distinct orientations, so that a device component such as contact pad 70 is capable of contacting diagonally-adjacent device components.
  • the interconnect 10 has an optional bond region 102 in between interconnect ends 100 and 110 that are electrically connected to a device component (not shown), thereby dividing central portion 90 into two non-bonded regions 92, each having a bent configuration.
  • FIG. 19 depicts one-dimensional stretching behavior of a buckled silicon array.
  • Panel (i) is a picture of a buckled silicon array without any straining force applied.
  • a stretching force is applied (as indicated by the arrows above panel (i)) to stretch the array in one direction.
  • panels (2)-(4) the buckled interconnect flattens.
  • the stretching force is released in panel (5), the array reverses to its buckled configuration (see panels (6)-(8)).
  • a comparison between panels (1 ) and (8) shows that the buckle configuration pre and post-stretch are identical, indicating the process is reversible.
  • Buckled arrays of device components may be readily transferred to curved surfaces, including rigid or inelastic curved surfaces.
  • An example of one device and process for facilitating conformal contact to curved surfaces is provided by the bubble or balloon stamp 400 of FIG. 20.
  • An elastomehc substrate 30, in this example an about 20 ⁇ m thick PDMS membrane is fixed in a housing chamber 300 to provide a chamber volume 310 defined by the interior-facing substrate wall and housing chamber.
  • Applying a positive pressure e.g., pressure in chamber 300 greater than exterior pressure
  • a convex 200 substrate surface capable of conformal contact with a concave- shaped receiving substrate.
  • FIG. 21 Another means for generating buckled or pop-up interconnects on a curved surface is summarized in FIG. 21.
  • a thin elastomeric film is cast against a shaped surface to generate an elastomeric substrate having at least a portion that is curved.
  • the substrate is capable of being stretched to flatten the surface so that the substrate is capable of conforming to both curved and flat surfaces.
  • An interconnect is applied to the flat stamp, and upon release of the stretching force, the substrate surface relaxes back to a curved geometry, generating a strain in the interconnect that is accommodated by a pop-up of the interconnect central portion.
  • FIG. 22 An example of "two-dimensional" stretching of a buckled silicon array by the device shown in FIG. 20, is provided in FIG. 22.
  • the interconnect comprises a plurality of buckled interconnect connections in a grid configuration, with the interconnects made of 290 nm thick Si.
  • the initially flat buckled silicon array (top left image) is placed into the housing, and a positive pressure exerted to expand the array into a bubble or balloon configuration (e.g., a curved surface). Maximum expansion is shown in the right-most image, and subsequently the positive pressure removed. Similar to the results for uniaxial stretching of a flat substrate, this "bending" stretching is reversible.
  • the array may be transferred to the curved surface by any means known in the art.
  • An example of silicon printing by balloon stamps onto glass lenses coated with adhesives (elastomehc substrate or SU-8) is shown in FIG. 23.
  • Example 1 Controlled Buckling Structures in Semiconductor Nanohbbons With Application Examples in Stretchable Electronics
  • Control over the compositions, shapes, spatial locations and/or geometrical configurations of semiconductor nanostructures is important for nearly all applications of these materials.
  • methods exist for defining the material compositions, diameters, lengths, and positions of nanowires and nanoribbons there are relatively few approaches for controlling their two- and three-dimensional (2D and 3D) configurations.
  • 2D and 3D two- and three-dimensional
  • Provided herein is a mechanical strategy for creating certain classes of 3D shapes in nanoribbons that are otherwise difficult to generate. This example involves the combined use of lithographically patterned surface chemistry to provide spatial control over adhesion sites and elastic deformations of a supporting substrate to induce well- controlled local displacements.
  • Precisely engineered buckling geometries are created in nanoribbons of GaAs and Si in this manner and these configurations can be described quantitatively with analytical models of the mechanics.
  • particular structures provide a route to electronics (and optoelectronics) with extremely high levels of stretchability (up to -100%), compressibility (up to -25%) and bendability (with curvature radius down to -5 mm).
  • nanoribbons and wires are controlled during their growth to yield certain geometries, such as coils, rings, and branched layouts, or after their growth to produce, as examples, sinusoidal wave-like structures by coupling these elements to strained elastomeric supports or tube-like (or helical) structures by using built-in residual stresses in layered systems.
  • Semiconductor nanoribbons with wavy geometries are of interest in part because they enable high performance, stretchable electronic systems for potential applications such as spherically curved focal plane arrays, intelligent rubber surgical gloves and conformable structural health monitors.
  • FIG. 24 shows the steps in this procedure.
  • the fabrication starts with the preparation of a mask for patterning surface chemical adhesion sites on an elastomeric substrate of poly(dimethylsiloxane) (PDMS).
  • PDMS poly(dimethylsiloxane)
  • This process involves passing deep ultraviolet (UV) light (240-260 nm) through an unusual type of amplitude photomask (fabricated via step i), referred to as a UVO mask, while it is in conformal contact with the PDMS.
  • the UVO mask possesses recessed features of relief in the transparent regions, such that exposure to UV creates patterned areas of ozone in proximity to the surface of the PDMS.
  • the ozone converts the unmodified hydrophobic surface, dominated by -CH 3 and -H terminal groups, to a highly polar and reactive surface (i.e. activated surface), terminated with -OH and -O-Si-O- functionalities.
  • the unexposed areas retain the unmodified surface chemistry (i.e. inactivated surface).
  • ⁇ pre ⁇ L/L for lengths changed from L to L+ ⁇ L
  • nanoribbons consisted of both single crystal Si and GaAs.
  • the silicon ribbons are prepared from silicon-on-insulator (SOI) wafers using procedures described previously (see Khang et al. Science 311 , 208-212 (2006)).
  • the GaAs ribbons involved multilayers of Si-doped n-type GaAs (120 nm; carrier concentration of 4x10 17 cm 3 ), semi-insulating GaAs (SI-GaAs; 150 nm) and AIAs (200 nm) formed on a (100) Sl- GaAs wafer by molecular-beam epitaxy (MBE).
  • MBE molecular-beam epitaxy
  • a thin layer of SiO 2 (-30 nm) is deposited to provide the necessary -Si-OH surface chemistry for bonding to the activated regions of the PDMS.
  • step iv Laminating the processed SOI or GaAs wafers against a UVO treated, pre- stretched PDMS substrate (ribbons oriented parallel to the direction of prestrain), baking in an oven at 90° C for minutes, and removing the wafer transferred all of the ribbons to the surface of the PDMS (step iv). Heating facilitates conformal contact and the formation of strong siloxane bonds (i.e., -O-Si-O-) between the native SiO 2 layer on the Si ribbons or the deposited SiO 2 layer on the GaAs ribbons and the activated areas of the PDMS. Relatively weak van der Waals forces bond the ribbons to the inactivated surface regions of the PDMS.
  • strong siloxane bonds i.e., -O-Si-O-
  • the 3D ribbon structures can be encapsulated in PDMS by casting and curing a liquid prepolymer (see FIG. 24 step vi). Due to its low viscosity and low surface energy, the liquid flows and fills the gaps formed between the ribbons and the substrate (see FIG. 26).
  • the image reveals uniform, periodic buckles with common geometries and spatially coherent phases for all ribbons in the array.
  • the anchoring points are well registered to the lithographically defined adhesion sites.
  • the inset shows an SEM image of a bonded region; the width is -10 ⁇ m, consistent with W act -
  • the images also reveal that the surface of the PDMS is flat, even at the bonding sites.
  • the PDMS represents a soft, nondestructive tool for manipulating the ribbons through forces applied at the adhesion sites.
  • the heights of the buckles e.g., "amplitude"
  • the ribbons (thickness h) separate from the PDMS to form buckles with vertical displacement profiles characterized by:
  • the width of the buckles is 2L 1 and the periodicity is 2L 2 . Because h 2 ⁇ 2 /(12Li 2 ) is much smaller than ⁇ pre (i.e., >10% in the report) for h ⁇ 1 ⁇ m, the amplitude is independent of the mechanical properties of ribbons (e.g., thickness, chemical composition, Young's modulus, etc.) and is mainly determined by the layout of adhesion sites and the prestrain. This conclusion suggests a general applicability of this approach: ribbons made of any material will form into similar buckled geometries. This prediction is consistent with the results obtained with Si and GaAs ribbons used here. The calculated profiles, plotted as dotted lines in FIG.
  • the lithographically defined adhesion sites can have more complex geometries than the simple grating or grid patterns associated with the structures in FIG. 24.
  • buckles with different widths and amplitudes can be formed in individual ribbons.
  • the image clearly shows the variation of widths and amplitudes of adjacent buckles in each of the ribbons.
  • Buckled ribbons can also be formed with different phases for different ribbons.
  • FIG. 27C presents an example of a Si system designed with phases in the buckles that vary linearly with distance perpendicular to the lengths of the ribbons.
  • the UVO mask used for this sample has W act and W 1n of 15 and 250 ⁇ m, respectively.
  • the angle between the activated stripes on PDMS stamp and Si ribbons is 30°. Many other possibilities can easily be achieved, due to the simple lithographic control of the adhesion sites, and some are shown in FIGs. 13-17, for example.
  • J_ J ⁇ projecte d d represents the maximum/minimum length before fracture
  • FIG. 30A-C present optical micrographs of bent configurations that illustrate this feature.
  • the PDMS substrate thickness -4 mm
  • the images illustrate how the profiles changed to accommodate the bending induced surface strains (-20-25% for these cases).
  • the shapes are similar, in fact, to those obtained in compression (by -20%) and tension (by -20%).
  • the embedded systems exhibit even higher levels of bendability due to neutral mechanical plane effects.
  • FIG. 31 A shows the geometry and equivalent circuit, and top-view optical micrographs of an MSM PD before and after stretching by -50%. In the absence of light, little current flowed through the PD; the current increased with increasing illumination with an infrared beam (wavelength -850 nm) (FIG. 31 B). The asymmetry in the current/voltage (I-V) characteristics can be attributed to differences in the electrical properties of the contacts.
  • I-V current/voltage
  • this example indicates that soft elastomers with lithographically defined adhesion sites are useful as tools for creating certain classes of 3D configurations in semiconductor nanoribbons.
  • Stretchable electronics provide one example of the many possible application areas for these types of structures.
  • Simple PD devices demonstrate some capabilities. The high level of control over the structures and the ability to separate high temperature processing steps (e.g. formation of ohmic contacts) from the buckling process and the PDMS indicate that more complex devices (e.g. transistors, and small circuit sheets) are possible. The well controlled phases of buckles in adjacent ribbons provide an opportunity for electrically interconnecting multiple elements. Also, although the experiments reported here used GaAs and Si nanoribbons, other materials (e.g. GaN, InP, and other semiconductors) and other structures (e.g. nanowires, nanomembranes) are compatible with this approach.
  • GaAs wafers with customer-designed epitaxial layers were purchased from IQE Inc., Bethlehem, PA. Photolithography and wet chemical etching generated the GaAs ribbons.
  • AZ photoresist e.g., AZ 5214
  • the GaAs wafers were then anisotropically etched for 1 minute in the etchant (4 ml_ H 3 PO 4 (85 wt%), 52 ml_ H 2 O 2 (30 wt%), and 48 m L deionized water), cooled in the ice-water bath.
  • the AIAs layers were dissolved with an HF solution (Fisher ® Chemicals) diluted in ethanol (1 :2 in volume).
  • the samples with released ribbons on mother wafers were dried in a fume hood. The dried samples were coated with 30 nm SiO2 deposited by electron beam evaporation.
  • FABRICATION OF Si RIBBONS The silicon ribbons are fabricated from an silicon-on-insulator (SOI) wafer (Soitect, Inc., top silicon 290nm, buried oxide 400nm, p- type). The wafer is patterned by conventional photolithography using AZ 5214 photoresist and etched with SF6 plasma (PlasmaTherm RIE, SF6 40sccm, 50mTorr, 100W). After the photoresist is washed away with acetone, the buried oxide layer is then etched in HF (49%).
  • SOI silicon-on-insulator
  • FABRICATION OF UVO MASKS Fused quartz slides are cleaned in piranha solution (at 60 0 C) for 15 minutes and thoroughly rinsed with plenty of water. The cleaned slides are dried with nitrogen blowing and placed in the chamber of electron- beam evaporator to be coated with sequential layers of 5-nm Ti (as adhesive layer) and 100-nm Au (mask layer for UV light). Negative photoresist, i.e., SU8 5, is spin cast on the slides at speed of 3000 rpm for 30 seconds to yield ⁇ 5 ⁇ m thick films. Soft baking, exposing to UV light, post baking, and developing generated patterns in the photoresist. Mild O2 plasma (i.e., descum process) removes the residual photoresist. The photoresist serves as mask to etch Au and Ti using gold etchant (i.e., aqueous solution of 12 and Kl) and titanium etchant (i.e., diluted solution of HCI), respectively.
  • gold etchant i.
  • FORMATION AND EMBEDMENT OF BUCKLED GaAs RIBBONS GaAs wafers with released ribbons coated with Si ⁇ 2 were laminated against the stretched PDMS with patterned surface chemistry. Baking in an oven at 90 0 C for 5 minutes, cooling to room temperature in air, and then slowly relaxing the strain in the PDMS generated buckles along each ribbon. Embedding the buckled ribbons, involved flood exposing to UV light for 5 minutes and then casting of liquid PDMS prepolymers to a thickness of ⁇ 4 mm. Curing the sample either in an oven at 65°C for 4 hours or at room temperature for 36 hours cured the prepolymer, to leave the buckled ribbons embedded in a solid matrix of PDMS.
  • CHARACTERIZATION OF BUCKLED RIBBONS The ribbons were imaged with an optical microscope by tilting the sample by -90° (for nonembedded samples) or -30° (for embedded samples). The SEM images were recorded on a Philips XL30 field- emission scanning electron microscope after the sample was coated with a thin layer of gold ( ⁇ 5 nm in thickness). The same stage used for pre-stretching the PDMS stamps was used to stretch and compress the resulting samples.
  • Liquid PDMS prepolymer was cast onto the regions of the ribbons without electrodes and then cured in an oven.
  • the gold electrodes extended beyond the top PDMS to enable probing with a semiconductor parameter analyzer. (Agilent 4155C).
  • the PDs were manipulated using a mechanical stage for stretching and compressing.
  • An IR LED source (with wavelength of 850 nm) provided the illumination.
  • the 'inked' hemispherical stamp is used to transfer print these elements onto the final device substrate having a matching shaped cavity (e.g., in this example a glass substrate with a matching hemispherically- shaped cavity).
  • This transfer process uses an ultraviolet (UV) curable photopolymer, such as photocurable BCB (Dow Chemical) or polyurethane (Norland Optical Adhesive) as an adhesive.
  • UV curable photopolymer such as photocurable BCB (Dow Chemical) or polyurethane (Norland Optical Adhesive) as an adhesive.
  • FIGs. 32 and 33 The approach of FIGs. 32 and 33 has several notable features. First, it exploits state-of-the-art planar electronics technology to enable reliable, cost-effective and high performance operation on the hemispherical substrates. In particular, the chiplets consist of collections of silicon transistors processed at the 0.13 ⁇ m design rule to yield the local, pixel-level processing capabilities for the HARDI system.
  • the buried oxide provides the sacrificial layer (undercut etching with HF) to prepare the chiplets for printing.
  • the interconnects consist of narrow and thin (-100 nm) metal lines.
  • a second feature is that the approach uses elastomehc elements and mechanical designs to enable a well-controlled planar to hemispherical transformation. Reversible, linear mechanics in the transfer stamps and comprehensive mechanical modeling accomplishes this control, as outlined subsequently.
  • a third attractive aspect is that certain basic components of the transfer processes and strategies to control adhesion have been demonstrated in planar applications. In fact, the stages that have been engineered for those planar printing applications can be adapted for the process of FIGs. 32 and 33.
  • FIG. 34 shows a home-built printer with integrated vision systems and air pressure actuators suitable for use in this process.
  • FIG. 35 shows scanning electron micrograph images of the surface of a hemispherical stamp that is 'inked' with an array of single crystal silicon islands interconnected in a square array with heavily doped silicon ribbons.
  • FIG. 36 shows optical images. During the planar to spherical transformation, these ribbon interconnects pop up in the manner depicted in FIG. 32.
  • a key aspect of these types of interconnects is that, when combined with the transfer of fully formed chiplets, they reduce the need for high resolution, curved surface lithography or other forms of processing directly on the hemisphere.
  • the second approach is a unit-cell model for devices (chiplets) that analyzes their mechanical performance upon loading. Each device is represented by a unit cell, and its response upon mechanical loading (e.g., bending and tension) is studied thoroughly via the finite element method. Each device is then replaced by the unit cell linked by interconnects. This unit-cell model is then incorporated into the finite element analysis to replace the detailed modeling of devices and interconnects. Furthermore, away from the edge of the sphere, the strains are relatively uniform such that the many unit-cells can be integrated and their performance can be represented by a coarse-level model. Near the sphere edge the strains are highly non-uniform such that the detailed modeling of devices are still necessary. The advantage of such an approach is that it significantly reduces the computational effort.
  • the full-scale finite element analysis in the first approach is used to validate this unit-cell model. Once validated, the unit-cell model provides a powerful design tool since it is suitable for the quick exploration of different designs of devices, interconnects, and their spacing.
  • FIG. 38 presents preliminary FEM results for stretching a hemispherical stamp into a planar geometry (and relaxing it back to its hemispherical shape), as outlined in FIG. 32.
  • the top frame shows a cross sectional view of a hemispherical stamp with a geometry like the one schematically illustrated in FIG. 32.
  • These results show slight spatial non-uniformities in the strains of the stretched membrane, as evidenced by its non-uniform thickness.
  • Engineering the thickness profiles of the stamps through proper selection of the structures against which they are formed by casting and curing, can eliminate these non-uniformities.
  • the modeling can also determine the levels of strain in the Si CMOS chiplets.
  • the systems should be designed to keep these chiplet strains below -0.1 -0.2% to avoid changes in the electrical properties and, possibly, mechanical failures due to fracture or delamination. This modeling facilitates the design of stamps and processing conditions to avoid exposure of the chiplets to strains above this range.
  • This example introduces a biaxially stretchable form of single crystalline silicon that consists of two dimensionally buckled, or "wavy", silicon nanomembranes on elastomeric supports. Fabrication procedures for these structures are described, and various aspects of their geometries and responses to uniaxial and biaxial strains along various directions are presented. Analytical models of the mechanics of these systems provide a framework for quantitatively understanding their behavior. These classes of materials provides a route to high-performance electronics with full, two-dimensional stretchability.
  • Recent demonstrations involved the use of buckled, one-dimensional "wavy" geometries in nanoribbons (thicknesses between tens and hundreds of nanometers and widths in the micrometer range) of silicon and gallium arsenide to achieve uniaxial stretchability in metal oxide semiconductor field effect transistors (MOSFETs), metal semiconductor field effect transistors (MESFETs), pn junction diodes, and Schottky diodes.
  • MOSFETs metal oxide semiconductor field effect transistors
  • MESFETs metal semiconductor field effect transistors
  • pn junction diodes pn junction diodes
  • Schottky diodes Schottky diodes.
  • FIG. 39 schematically illustrates the steps for forming two-dimensionally stretchable Si nanomembranes on elastomehc supports.
  • these membranes are fabricated from silicon-on-insulator (SOI) wafers (Soitec, Inc., p-type) starting with the formation of a square array of holes in the top silicon (-2.5 ⁇ m diameter, and -25 ⁇ m pitch), by defining suitable patterns of photoresist by photolithography and then removing the exposed silicon by reactive ion etching (PlasmaTherm RIE, SF 6 40 seem, 50 mTorr, 100 W).
  • SOI silicon-on-insulator
  • This same step defines the overall lateral dimensions of the membranes which, for the samples reported here, are in the range of 3-5 mm square. The thicknesses are between 55 and 320 nm. Immersing the etched samples in concentrated hydrofluoric acid (HF 49%) removes the buried SiO2 layer (145-1000 nm thick); washing in acetone removed the photoresist. Casting and curing prepolymers of poly(dimethylsiloxane) (PDMS) against polished silicon wafers generated flat, elastomeric substrates (-4 mm thick).
  • PDMS poly(dimethylsiloxane)
  • the herringbone region is characterized by the distance between adjacent peaks in the waves, which we refer to as the short wavelength ⁇ , the amplitude of wave Ai (not shown in Figure 1 ), and a longer distance 2 ⁇ /k 2 (along the x2 direction), associated with the separation between adjacent "jogs" in the herringbone structure, which we refer to as the long wavelength.
  • Other characteristic length are the 'jogs' wavelength 2 ⁇ /ki (along the xi direction, normal to the long wavelength direction X 2 ), the amplitude A 2 of the jogs, the jog angle ⁇ .
  • the bottom frames of FIG. 39 illustrate these features schematically.
  • Parts a-f of FIG. 40 show optical micrographs collected at different stages during the formation of herringbone waves, for the case of a nanomembrane with 100 nm thickness (lateral dimension of ca. 4 x 4 mm 2 ) and thermal prestrain (defined by heating to 150 0 C) of -3.8%. These images indicate structure formation in two stages, the first of which involves predominantly one-dimensional waves over large areas followed by bending of these wave structures to form, ultimately, compact herringbone layouts at full cooling (FIG. 40 d-f).
  • FIG. 40h shows the time evolution of both characteristic wavelengths. The short wavelength tends to decrease as the cooling leads to progressively larger compressive strain on the silicon due to the relatively larger thermal contraction of the PDMS.
  • the stress, strain, and displacement fields in the Si film can be obtained in terms of A-i, k-i, A 2 , and k 2 from the Von Karman plate theory.
  • the fields in the PDMS substrate are obtained from 3D elasticity theory. Minimizing the total energy, which consists of the membrane energy and bending energy in the Si film and the elastic energy in the PDMS substrate gives A 1 , k-i, A 2 , and k 2 .
  • FIG. 41 presents atomic force microscope (AFM) and scanning electron microscope (SEM) images of structures similar to those illustrated in the fully cooled state of FIG. 40. These images clearly show that the herringbone patterns are characterized by zigzag structures that define two characteristic directions, even though the compressive strain is completely isotropic.
  • the herringbone structures represent a minimum elastic energy configuration that reduces the overall in-plane stress in the system and relieves biaxial compression in both directions. This geometry is, therefore, preferred over large areas, compared to the "checkerboard" and 1 D wave layouts because the herringbone mode is the only one of these three modes that relaxes the in- plane stress in all directions without incurring significant stretch energy. Only in the immediate vicinity of the jogs is significant stretch induced.
  • the 1 D mode lowers the prestress only in one direction.
  • the checkerboard mode lowers the stress in all directions, but it produces significant stretch energy accompanying the bending.
  • the two linecuts extracted from the AFM images indicate periodic, although only approximately sinusoidal, relief profiles along the jogs direction (profile i) and perpendicular to waves (profile ii).
  • the ⁇ and A 1 of waves, determined from profile ii, are 12.8 and 0.66 ⁇ m, respectively.
  • the ⁇ given by theoretical analysis, 12.4 ⁇ m, is similar with the experimental data; however, the Ai from theoretical analysis is 0.90 ⁇ m, somewhat higher value than the experimental results.
  • the SEM images show clearly the intimate bonding between the membrane and the PDMS, as evidenced by the behavior of the sample near the small holes in the silicon in both the raised and recessed regions of the waves.
  • the 2D herringbone waves Compared to the 1 D waves at the edges, the 2D herringbone waves have smaller ⁇ and A 1 , suggesting that the inner area of Si is affected more strongly by the compressive strain than the edges.
  • the stress state near the edge is approximately uniaxial compression within some distance range because of the traction-free edge of the membrane. This uniaxial compression is parallel to this free edge and therefore leads to 1 D waves along the edge.
  • the stress state becomes equi-biaxial compressive in the central region where herringbone structures result.
  • the unbalanced biaxial compression causes a "semi"- herringbone wave with the large jog angle.
  • Our model yields ⁇ and A 1 of 16.9 and 0.83 ⁇ m, respectively, for the 1 D waves and 12.4 and 0.90 ⁇ m for the herringbone structure.
  • FIG. 45 shows optical micrographs of these structures, for two different levels of thermal prestrain.
  • the 100 and 200 ⁇ m wide membranes exhibit perfect 1 D waves from one side to the other, with flat, undeformed regions at the ends.
  • the 500 ⁇ m wide membrane shows similar 1 D waves and flat regions, but the waves have slightly bent geometries in the middle of the structures, with overall ordering and uniformity in orientation that are substantially less than the 100 and 200 ⁇ m cases.
  • the characteristic length scales that define the spatial extent of the flat regions which we refer to as the edge effect length, Ledge, can be evaluated as a function of membrane size and prestrain.
  • FIG. 45C shows results that indicate a linear scaling of this length with prestrain, in a manner that is independent of the size of the membrane, for the cases investigated here. As the prestrain becomes higher, the length of uniaxial strain region becomes smaller. Therefore, shorter range 1 D waves form and similar behavior can be observed in the stress-free regions near the two free edges.
  • FIG. 46 shows optical micrographs of wavy structures that form in other membrane geometries, including circles, ovals, hexagons, and triangles.
  • the results are qualitatively consistent with observations in the ribbons and squares of FIG. 45.
  • the edge regions show 1 D waves oriented parallel to the edges. Waves with the orthogonal orientation only appear at distances larger than the L edge from the edge.
  • 1 D waves appear near the edges, with an overall radial orientation due to the shape of the membrane.
  • Herringbone waves appear in the center.
  • the ovals exhibit similar behavior, although with flat regions at the edges of the major axis, due to the small radius of curvature in these regions.
  • nanomembranes of silicon can be integrated with prestrained elastomeric substrates to create 2D "wavy" structures with a range of geometries. Many aspects of the mechanical behavior of these systems are in good agreement to theoretically predicted behaviors. These results are useful for applications of electronics in systems where full stretchability is required during use or during installation.
  • Example 4 Heterogeneously Integrated, Three Dimensional Electronics by Use of Printed Semiconductor Nanomaterials
  • HGI heterogeneously integrated
  • 3D three dimensional
  • HGI monolithic, heterogeneous integration
  • examples include multifunctional radio frequency communication devices, infrared (IR) imaging cameras, addressable sensor arrays and hybrid CMOS/nanowire/nanodevice circuits (3-7).
  • compound semiconductors or other materials provide high speed operation, efficient photodetection or sensing capabilities while silicon CMOS provides digital readout and signal processing, in circuits that often involve stacked 3D configurations.
  • Wafer bonding (8) and epitaxial growth (9,10) represent the two most widely used methods for achieving these types of 3D-HGI systems.
  • the former process involves physical bonding, by use of adhesives or thermally initiated interface chemistries, of integrated circuits, photodiodes or sensors formed separately on different semiconductor wafers.
  • This approach works well in many cases, but it has important drawbacks, including (i) limited ability to scale to large areas or to more than a few layers in the third (i.e. stacking) dimension, (ii) incompatibility with unusual (e.g. nanostructured materials) or low temperature materials and substrates, (iii) challenging fabrication and alignment for the through-wafer electrical interconnects, (iv) demanding requirements for flat, planar bonding surfaces and (v) bowing and cracking that can occur from mechanical strains generated by differential thermal expansion/contraction of disparate materials.
  • Epitaxial growth provides a different approach that involves the direct formation, by molecular beam epitaxy or other means, of thin layers of semiconductor materials on the surfaces of wafers of other materials. Although this method avoids some of the aforementioned problems, the requirements for epitaxy place severe restrictions on the quality and type of materials that can be grown, even when buffer layers and other advanced techniques are used.
  • emerging classes of semiconductor nanomaterials such as nanoscale wires, ribbons, membranes or particles of inorganic materials, or carbon based systems such as single walled carbon nanotubes (SWNTs) or graphene sheets (11 -14), can be grown and then suspended in solvents or transferred onto substrates in a manner that bypasses the need for epitaxial growth or wafer bonding.
  • SWNTs single walled carbon nanotubes
  • 11 -14 graphene sheets
  • Recent work shows, for example, the integration, in 2D layouts, of crossed nanowire diodes formed by solution casting (15).
  • the results presented here illustrate how dissimilar single crystal inorganic semiconductors (e.g., nanowires/ribbons of GaN, Si and GaAs) can be combined with one another and also with other classes of nanomatehals (e.g. SWNTs) using a scalable and deterministic printing method to yield complex, HGI electronic systems in 2D or 3D layouts.
  • ultrathin multilayer stacks of high performance metal-oxide- semiconductor field-effect transistors MOSFETs
  • metal-semiconductor field-effect transistors MOSFETs
  • MESFETs metal-semiconductor field-effect transistors
  • TFTs thin film transistors
  • photodiodes and other components integrated into device arrays, logic gates and actively addressable photodetectors on rigid inorganic and flexible plastic substrates demonstrate some of the capabilities.
  • Figure 57 illustrates representative steps for producing these 3D-HGI systems.
  • the process begins with synthesis of the semiconductor nanomaterials, each on their own source substrate.
  • the devices presented here integrate nanowires and nanoribbons of single crystal Si, GaN and GaAs, formed using wafer based source materials and lithographic etching procedures (16-21 ), and networks of SWNTs grown by chemical vapor deposition (13,21 ). Scanning electron micrographs at the top of
  • Figure 57 show these semiconductor nanomaterials, after their removal from the source substrates.
  • these elements remain in the configurations defined on the wafers during the fabrication or growth stage: aligned arrays in the case of the Si, GaN and GaAs nanowires/ribbons and sub-monolayer random networks for the SWNTs.
  • High temperature doping and annealing procedures for ohmic contacts to the Si, GaN and GaAs can be performed on the source substrates.
  • the next step involves transferring these processed elements, using an elastomehc stamp-based printing technique described previously, from the source substrates to a device substrate, such as a sheet of polyimide (Pl) as illustrated in Fig. 57.
  • a device substrate such as a sheet of polyimide (Pl) as illustrated in Fig. 57.
  • a stamp of polydimethysiloxane (PDMS) against the source substrate establishes soft, van der Waals adhesion contacts to the semiconductor nanomatehal elements.
  • a device substrate e.g. Pl sheet
  • a thin, spin-cast layer of a liquid prepolymer e.g. polyamic acid
  • curing the polymer leaves these semiconductor materials embedded on and well adhered to this layer (16-20) when the stamp is removed.
  • Similar procedures work well with a range of substrates (i.e. rigid or flexible; organic or inorganic) and semiconductor nanomatehals [A slightly modified version of this process is used for the SWNTs (21 ).].
  • the thickness of the interlayer can be as small as 500 nm and is typically 1 -1.5 ⁇ m, for the systems described here.
  • the transfer printing and device fabrication steps can be repeated, beginning with spin-coating a new prepolymer interlayer on top of the previously completed circuit level.
  • Automated stages specially designed for transfer printing or conventional mask aligners enable overlay registration accuracy of ⁇ 1 ⁇ m over several square centimeters. (22) (Fig 61).
  • Layer to layer interconnects (23) are formed simply by evaporating metal lines over and into openings in the interlayers defined by photopatterning and/or dry etching. This unusual approach to 3D-HGI electronics has several important features.
  • Figure 58 presents a three layer, 3D stack arrayed Si MOSFETs fabricated using the general process flow illustrated in Fig. 57, using single crystal silicon nanoribbons, with doped contacts (formed on the source wafer), plasma enhanced chemical vapor deposited SiO2 dielectrics, and Cr/Au metallization for source, drain and gate (24). Each device uses three aligned nanoribbons, with widths, thicknesses and lengths of 87 ⁇ m, 290 nm and 250 ⁇ m, respectively.
  • Figure 2A shows a top view optical micrograph of an edge of the system with a layout designed to reveal separately the parts of the substrate that support one, two and three layers of MOSFETs.
  • FIG. 58B Schematic cross-sectional and angled views of the stacked structure appear in Fig. 58B.
  • the sample can be viewed in 3D using confocal optical microscopy.
  • Figure 58C shows top and angled views of such images, colorized for ease of viewing. (The image quality degrades somewhat with depth, due to scattering and absorption from the upper layers).
  • Figure 58D presents electrical measurements of representative devices [top gate MOSFETs with channel lengths (L c ) of 19 ⁇ m, channel overlap distances (Lo), defined by distance that the gate electrode extends over the doped source/drain regions, of 5.5 ⁇ m, and channel widths (W) of 200 ⁇ m] in each layer.
  • Devices on each of the three layers, which are formed on a Pl substrate, show excellent properties (linear mobilities of 470 ⁇ 30 cm 2 A/s, on/off ratios >104 and threshold voltages of -0.1 ⁇ 0.2V) and no systematic differences between devices in different layers. Additional layers can be added to this system, by repeating the same procedures.
  • 3D circuits with a single semiconductor as illustrated in Fig.
  • MESFETS high electron mobility transistors
  • MOSFETs MOSFETs
  • TFTs thin film transistors
  • Figure 59A and 59B show high magnification optical and confocal images, respectively, of the resulting devices.
  • the GaN HEMTs on the first layer use ohmic contacts (Ti/AI/Mo/Au, annealed on the source wafer) for source and drain, and a Schottky (Ni/Au) contacts for the gates.
  • the channel lengths and widths, and the gate widths are 20, 170, and 5 ⁇ m respectively.
  • Each device uses GaN ribbons (composed of multilayer stacks of AIGaN/GaN/AIN) with thicknesses, widths and lengths of 1.2, 10 and 150 ⁇ m, respectively, interconnected electrically by processing on the device substrate.
  • the SWNT TFTs on the second layer use SiO2/Epoxy for the gate dielectric and Cr/Au for source, drain and gate, with channel lengths and widths of 50 and 200 ⁇ m, respectively.
  • the Si MOSFETs use the same design as those shown in Fig. 58.
  • Various other 3D- HGI devices can be constructed using different combinations of Si, SWNT and GaN (Figs. 61 and 62).
  • Figure 59C presents the current-voltage characteristics of typical devices in the systems of Fig. 59A and 59B.
  • this double-layer inverter exhibits well-defined transfer characteristics with gains of ⁇ 2, comparable to the performance of conventional planar inverters that use the similar transistors (25).
  • Figure 6OB shows an inverter with a complementary design (CMOS) by use of integrated n-channel Si MOSFETs and p-channel SWNT TFTs, designed in order to equalize the current-driving capability in both pull-up and pull-down directions (Fig. 65).
  • CMOS complementary design
  • Transfer curves collected with a 5 V bias to the VDD terminal and gate voltage (input) swept from 0 V to 5 V appear in Fig. 6OA.
  • the curve shapes and gains are qualitatively consistent with numerical circuit simulations (Fig. 65).
  • MSM metal-semiconductor-metal
  • IR detectors infrared detectors
  • Electrodes (Ti/Au 5/70nm) deposited on the ends of these GaAs nanoribbons form back-to-back Schottky diodes with separations of 10 ⁇ m.
  • the resulting detector cells exhibit current enhancement as the intensity of IR illumination increases (Fig. 60C), consistent with circuit simulation (Fig. 66).
  • a responsivity of about 0.30 A/W at the 850 nm wavelength is observed from 1 to 5 V, without taking into account the light reflected from the surface of the semiconductor.
  • the system also exhibits bendability with radii of curvature below 1 cm, which could be useful for advanced systems such as curved focal plane arrays for wide angle IR night vision imagers.
  • Printed semiconductor nanomaterials provide new approaches to 3D-HGI systems and could have important applications in various fields of application, not only those suggested by the systems reported here, but also others including microfluidic devices with integrated readout and sensing electronics, chem/bio sensor systems that incorporate unusual sensing materials with conventional silicon based electronics and photonic/optoelectronic systems that combine light emitters of compound semiconductor with silicon drive electronics or microelectromechanical structures. Further, the compatibility of this approach with thin, lightweight plastic substrates may create additional opportunities for devices that have unusual form factors or mechanical flexibility as key features.
  • the first step involved phosphorous doping, using a solid source and spin-on-dopant (Filmtronic, P509), and a photolithographically defined layer of plasma enhanced chemical vapor (PECVD) deposited SiO2 (Plasmatherm, 300nm, 900mTorr, 350sccm, 2% SiH 4 /He, 795sccm NO 2 , 250 0 C) as a mask to control where dopant diffuses into the silicon.
  • PECVD plasma enhanced chemical vapor
  • the stamp thus 'inked' with Ds- Si ribbons from wafer was laminated against a polyimide (Pl) sheet of 25 ⁇ m (Dupont, Kapton100E) spincoated with a thin layer ( ⁇ 1.5 ⁇ m) of liquid Pl precursor, polyamic acid (Sigma_Aldhch Inc.). Curing the precursor, peeling off the PDMS stamp, and stripping the photoresist left the ribbons embedded on and well adhered to the surface of the Pl substrate.
  • the gate dielectric layer consisted of a layer of SiO 2 (thickness -100 nm) deposited by PECVD at relatively low temperature, 250 0 C. Photolithography and CF 4 plasma etching defined openings to the doped source/drain regions of the silicon.
  • Source, drain and gate electrodes of Cr/Au (5/100 nm, from bottom to top by electron beam evaporation, Temescal FC-1800) were defined in a single step by photolithography and wet etching.
  • GaN devices GaN microstructures were fabricated on a bulk wafer of GaN with heteorostructure [ AIGaN(18 nm)/ GaN(0.6 ⁇ m)/ AIN(0.6 ⁇ m)/ Si]. An ohmic contact area defined by AZ 5214 photoresist and then cleaned with SiCI 4 plasma in a RIE system. A Ti/AI/Mo/Au (15/60/35/50 nm) metal layer was then deposited by e-beam evaporation (Ti/AI/Mo) and thermal evaporation (Au). Washing away the resist completed left metal contacts on the GaN.
  • ICP dry etching (3.2 mTorr, 15 seem CI2, 5 seem Ar, -100V Bias, 14 min) was used to remove the exposed GaN and to etch slightly into the Si ( ⁇ 1.5 ⁇ m) to facilitate the subsequent anisotropic etching.
  • the Si was then etched away from underneath the GaN using a tetramethyl ammonium hydroxide (Aldrich, 150 0 C for 4 min 30 sec).
  • the sample was dipped in BOE (6:1 , NH 4 F: HF) for 30 sec to remove the
  • SWNT devices Chemical vapor deposition (CVD) was used to grow random networks of individual single walled carbon nanotubes on SiO2/Si wafers.
  • CVD Chemical vapor deposition
  • the feeding gas was methane (1900 seem CH 4 with a 300 seem H 2 ).
  • the quartz tube in the furnace was flushed with a high flow of Ar gas for cleaning before growth. During the growth, the temperature was held at 900°C for 20 minutes.
  • the transfer involved either procedures similar to the printing like processes described previously, or a slightly different method in which a thick Au layer and a Pl precursor were coated on the SiO 2 /Si substrate with the tubes. After curing the Pl, the Au/PI was peeled back.
  • 3D Circuit 3D Si NMOS inverter: Multilayer devices were constructed by repetitively applying the same fabrication procedures. In particular, to the Pl precursor was spin-cast on the top of an existing layer of devices, and silicon ribbons were transfer-printed on top. The same processes were then used to fabricate devices. For vertical metal interconnects, an electrode area was defined by photo-patterning openings in a layer of AZ4620 photoresist, and then etching away the SiO2 and Pl in this exposed area using CF 4 and O2 plasma in a RIE system. Depositing 300 nm Al into this area established contacts at the bottom, and provided an electrically continuous connection over the step edge formed by the etched SiO 2 and Pl.
  • SWNT and Si CMOS inverter The SWNT devices consisted of source/drain contacts of Au (20 nm) defined by photolithography on the tube networks.
  • the SiO 2 (100nm)/Si wafer substrate provided the gate dielectric and gate.
  • Epoxy (SU8, 500 nm) was then spin-coated onto this substrate after the SWNT transistors were selectively coated with photoresist (AZ5214). After UV exposure for curing of epoxy, a PDMS slab 'inked' with undoped Si ribbons was laminated against the substrate and subsequently removed by slow manual peeling to complete the transfer-printing process.
  • Cr/Au (5/100 nm) were used as Schottky contacts for source and drain electrodes in the silicon devices.
  • Al (100 nm) was used to connect the SWNT and Si transistor.
  • GaAs wafers with photoresist mask patterns were anisotropically etched in the etchant (4ml_ H3PO4 (85 wt%), 52 ml_ H2O2 (30 wt%), and 48 ml_ deionized water).
  • the AIAs layers were etched away with a diluted HF solution in ethanol (1 :2 in volume). Layers of 2nm Ti and 28nm SiO2 were the deposited by e-beam evaporator.
  • a PDMS stamp inked with the GaAs ribbons was then contacted to a layer of Si transistors coated with Pl (thickness 1.5 ⁇ m).
  • the pop up architecture is one that enables a range of device architectures and structures integrating structures that embed useful but difficult to achieve features. It is an architecture enabling important competencies devices that express electronic, optical, mechanical, and thermal forms of functionality. In many cases, the system designs exploit a hierarchy of such effects to enable explicit device level performance outcomes, although for simplicity we discuss specific embodiments below in terms of a dominant mode of functioning.
  • the examples show a specific architecture for the simplest system elements, the interconnects, that can be used to withstand formal system high level strains (> 30% in the form factor appropriate for the construction of bus lines and interconnects in a display) as well as providing for other more demanding forms of mechanical compliance (stretchability).
  • formal system high level strains > 30% in the form factor appropriate for the construction of bus lines and interconnects in a display
  • mechanical compliance stress
  • These benefits can be extended as well to more complex device level components as illustrated by the form factor of the exemplary devices shown in Figure 31 , a GaAs MSM IR photodetector as described.
  • every functional component of a complex electronic system can be integrated in a design-specific, mechanically compliant form using the methods taught herein.
  • Optical components e.g., a waveguide can respond with extreme sensitivity to flexure.
  • the methods and systems provide new architectures for such devices that can both tolerate and, more importantly, exploit mechanical flexure to benefit functional performance.
  • Examples of technologies that can directly exploit the methods disclosed herein include advanced forms of photonic components including, but not limited to, waveguide optical couplers and related forms of optical switches and limiters.
  • Mechanical flexure at the system level of the integrated structure via compression or extension) provides a direct means to effect these functionalities. The loss in a channel as well directly relates to the flexure of the waveguide — high bending radii promoting leakage in a controllable way from core to sheath modes.
  • FIG. 67 schematically illustrates a waveguide array produced via the controlled buckling of an optical microstructure partially adhered to a deformable substrate.
  • FIG. 67A shows the optical device is produced by attaching a component 330 (e.g., waveguide such as an optical fiber or other elongated microstructure) to a substrate 30 by contact printing, for example.
  • the attachment includes strongly bound contacting regions 310 and weakly bound regions corresponding to raised regions 320.
  • the second electrode buckles and the weakly-bound region of the waveguide separates physically from the substrate, thereby producing the raised region.
  • the device may operate simply as a waveguide capable of significant (5 to 50%) stretchability (see FIG. 67B).
  • the indices of refraction of the waveguide and substrate as well as the buckling geometry may be chosen such that the device operates as an optical switch, allowing light to pass in the elongated state (FIG. 67B) but not in the shortened state (FIG. 67A), due to the high curvature in the buckled waveguides.
  • FIG. 68 is a representative example of a mechanical system, specifically an entwined multilayer architecture for capacitively coupled sensing. This exemplary architecture directly enables important forms of force related sensing — inertial and pressure measurements most notably.
  • the methods and systems disclosed herein provide a relatively direct means to control many systems level aspects of the performance of these devices — dynamic range and region of optimum sensitivity most notably — while enabling their integration into compact, novel form-factor systems (e.g.
  • a mechanical device 400 e.g., accelerometer/pressure sensor
  • This device architecture operates by monitoring changes in the capacitance between the bottom electrode 450 and the other electrode 440 that occur when the raised region 320 of the electrode 440 is displaced relative to the substrate via acceleration or pressure in the z-direction.
  • the device 400 is produced by preparing an electrode (bottom electrode 450) on the substrate 30, then by attaching another electrode 440 by contact printing.
  • the attachment includes strongly bound contacting regions 310 and weakly bound regions (e.g., in the region below 320).
  • the second electrode 440 buckles and the weakly-bound region separates physically from the substrate, thereby producing the raised region 320.
  • Thermally Functional Devices The pop up structures afforded by the present invention engender new capacities to provide for the thermal isolation of complex electronic components.
  • An explicit device class provides a general design for the pixel elements of a long wavelength imaging system that requires the integration of high performance electronic components that provide control, read out, data handling and other capabilities for the system while providing direct integration and precise thermal isolation of thermally responsive (and for this example) two terminal devices. This demanding architecture is readily accessed using the methods taught by the current invention.
  • FIG. 69 shows a thermal device 500 (microbolometer) produced via the controlled buckling of a thermoresistive microstructure partially adhered to a deformable substrate.
  • the device 500 is produced by attaching to the substrate 30 an electrode 550 that contains a thermoresistive material 560 by contact printing.
  • the attachment includes strongly bound contacting regions 310 and weakly bound regions corresponding to raised regions 320.
  • the electrode 550 buckles and the weakly-bound region separates physically from the substrate, thereby producing the raised region 320 that is to a large extent thermally isolated from the substrate, thereby providing accurate and localized temperature sensing.

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Abstract

Dans un aspect, la présente invention concerne des composants étirables et éventuellement imprimables, tels que des semi-conducteurs et des circuits électriques, qui présentent une efficacité satisfaisante lorsqu'ils sont étirés, comprimés, pliés ou déformés d'une autre façon. L'invention a également trait à des procédés de fabrication ou de réglage de tels composants étirables. Les semi-conducteurs et circuits électroniques étirables préférés pour certaines applications sont souples en plus d'être étirables, et peuvent ainsi considérablement s'allonger, se plier, se couder ou se déformer d'une autre manière le long d'un ou plusieurs axes. En outre, les semi-conducteurs et circuits électroniques étirables selon l'invention sont adaptés à une large gamme de configurations de dispositifs, ce qui permet d'obtenir des dispositifs électroniques et optoélectroniques totalement souples.
PCT/US2007/077759 2006-09-06 2007-09-06 Structures à déformation contrôlée dans des interconnexions de semi-conducteurs et des nanomembranes pour dispositifs électroniques étirables WO2008030960A2 (fr)

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KR1020167032797A KR101814683B1 (ko) 2006-09-06 2007-09-06 2차원 인장 가능하고 구부릴 수 있는 장치
KR1020147006478A KR101612749B1 (ko) 2006-09-06 2007-09-06 2차원 인장 가능하고 구부릴 수 있는 장치
KR1020177037238A KR102087337B1 (ko) 2006-09-06 2007-09-06 인장 가능한 가요성 장치의 제조 방법
KR1020147031584A KR101689747B1 (ko) 2006-09-06 2007-09-06 2차원 인장 가능하고 구부릴 수 있는 장치
KR20097007081A KR101453419B1 (ko) 2006-09-06 2007-09-06 2차원 인장 가능하고 구부릴 수 있는 장치
JP2009527564A JP5578509B2 (ja) 2006-09-06 2007-09-06 エラストマ基板に伸縮性コンポーネントを接着する方法
EP07841968A EP2064710A4 (fr) 2006-09-06 2007-09-06 Structures à déformation contrôlée dans des interconnexions de semi-conducteurs et des nanomembranes pour dispositifs électroniques étirables
CN2007800411276A CN101681695B (zh) 2006-09-06 2007-09-06 在用于可拉伸电子元件的半导体互连和纳米膜中的受控弯曲结构

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