Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
  • H03K2005/00019—Variable delay
  • H03K2005/00058—Variable delay controlled by a digital setting

Definitions

• the present invention relates to a variable delay device for adjusting the timing of an input signal by changing the delay time and outputting the result.
• variable delay device As a conventional variable delay device, there has been a variable delay device in which a plurality of delay elements are connected in series and an output of the delay elements is selected (for example, refer to Patent Document 1).
• variable delay device that is configured by combining delay elements with a delay amount of 2 to the Nth power X t (t is the minimum delay time, N is an integer) (for example, (See Patent Document 2).
• FIG. 10 shows a configuration of a conventional variable delay device described in Patent Document 1.
• Delay elements 1002a to 1002 ⁇ are connected in series, and each output of input signal 1001 and delay elements 1002a to 1002 ⁇ is connected to selector 1004, and output signal 1005 is selected by selection signal 1003.
• a variable delay device that can be changed is configured.
• FIG. 11 shows the configuration of a conventional variable delay device described in Patent Document 2.
• Delay element 1103, 1105, 1107 and manoplexer 1104, 1106, 1108 force N delay stages (stages) are connected in series, and the signal path inside each delay stage is selected by the N-bit delay selection signal 1102, thereby configuring a variable delay device that can vary the delay amount of the input signal 1101. To do.
• Patent Document 1 Japanese Patent Laid-Open No. 8-56143
• Patent Document 2 JP-A-6-196958
• variable delay device configured as in Patent Document 1
• the variable delay device When a variable time range is required, and the variable time range is wide or the variable time resolution is small, many delay elements are required, and the scale of the device will increase. I got it.
• FIG. 12 (a) is a block diagram when N is 3 in the variable delay device configured as in Patent Document 2
• FIG. 12 (b) is a diagram showing an example of operation timing.
• Fig. 12 (b) when the 3-bit delay selection signal 1202 changes from the set value 4 to the set value 3, the input signal and output are output during the 3t time immediately after setting the delay amount 3.
• the time difference of the signal is other than 3t (delay time not corresponding to the delay amount setting of 3) and is different from the delay time of 4t corresponding to the previous set value 4, and a signal with a timing different from the set value is output.
• the present invention solves the above-described conventional problem, and even immediately after changing the delay amount of the variable delay device, a signal having a timing different from the set delay amount is not output.
• An object is to provide a delay device.
• the variable delay device of the present invention is a variable delay device that outputs an input signal with a delay amount corresponding to the delay selection signal, and sets the input signal according to the delay selection signal.
• 1st to Ith variable delay blocks that are output after being delayed by the first to Ith delays (I is a natural number), and output selections corresponding to the first to Ith delay amounts
• First selection means for switching and outputting the output signals of the first to I-th variable delay blocks according to the signal.
• variable delay device of the present invention there is provided a variable delay device in which a signal having a timing different from the set delay amount is not output even immediately after the delay amount of the variable delay device is changed. can do.
• FIG. 1 is a block diagram of a variable delay device in Embodiment 1 of the present invention.
• FIG. 2 is a timing chart showing an operation example when N is 3 in the first embodiment of the present invention.
• FIG. 3 is a block diagram of a variable delay device in Embodiment 2 of the present invention.
• FIG. 4 is a timing diagram showing that output signal jitter occurs in the second embodiment of the present invention.
• FIG. 5 is a timing chart showing an operation example when N is 3 in the second embodiment of the present invention (1)
• FIG. 6 is a timing chart showing an operation example when N is 3 in the second embodiment of the present invention (2)
• FIG. 7 is a timing chart showing an operation example when N is 3 in the second embodiment of the present invention (3)
• FIG. 8 is a diagram showing how a signal with a timing different from the set delay amount is output when the delay amount setting is changed from 8 to 7 in Embodiment 2 of the present invention.
• FIG. 9 is a block diagram of a variable delay device in Embodiment 3 of the present invention.
• FIG. 10 is a diagram showing a configuration of a conventional variable delay device described in Patent Document 1.
• FIG. 11 is a diagram showing a configuration of a conventional variable delay device described in Patent Document 2.
• FIG. 12 is a block diagram and an example of operation timing when N is 3 in the variable delay device described in Patent Document 2.
• FIG. 13 is a diagram showing an example of the circuit configuration and operation timing of the selector in the first embodiment of the present invention.
• variable delay device in which variable delay blocks are parallelized and one of the outputs is used as the delay output.
• adoption is basically performed alternately.
• switching of which variable delay block output is to be used is performed after the delay time setting has been changed and after a predetermined time has elapsed to reflect the changed delay amount. It is.
• FIG. 1 is a block diagram of a variable delay device according to Embodiment 1 of the present invention.
• the variable delay device shown in FIG. 1 delays an input signal by a delay amount corresponding to the delay selection signal, and outputs the first delay set by the N-bit delay selection signal 105.
• Variable delay block 108 that delays the output by an amount
• variable delay block 109 that outputs input signal 111 by delaying the second delay amount set by N-bit delay selection signal 106, and first and second outputs According to the output selection signal 110 generated corresponding to the delay amount
• the selector 107 outputs the output signal 112 by switching the output signals of the variable delay block 108 and the variable delay block 109.
• FIG. 1 is a block diagram of a variable delay device according to Embodiment 1 of the present invention.
• the variable delay device shown in FIG. 1 delays an input signal by a delay amount corresponding to the delay selection signal, and outputs the first delay set by the N-bit delay selection signal 105.
• an input signal 111 is input to the delay element 101 ⁇ of the variable delay block 108, 103 ⁇ of the variable delay block 109, the selector 102 ⁇ of the variable delay block 108, and the selector 104 ⁇ of the variable delay block 109.
• the selector 102 ⁇ outputs the signal output from the delay element 101 ⁇ when the first selection signal 105 ⁇ is “;!”, And outputs the input signal 111 when it is “0”.
• the selector 102b outputs the signal output from the delay element 101b when the second selection signal 105b is ";!, And outputs the signal input to the delay element 101b when it is "0".
• the selector 102a outputs the signal output from the delay element 101a when the first selection signal 105a is “1", and outputs the signal input to the delay element 101a when it is “0".
• the selector 104 ⁇ outputs the signal output from the delay element 103 ⁇ when the Nth selection signal 106 ⁇ is “;!”, And outputs the input signal 111 when it is “0”.
• the selector 104b outputs the signal output from the delay element 103b when the second selection signal 106b is ";!, And outputs the signal input to the delay element 103b when it is "0". To do.
• the selector 104a outputs the signal output from the delay element 103a when the first selection signal 106a is ";!, And outputs the signal input to the delay element 103a when it is "0".
• the selector 107 sets the signal output from the variable delay block 108 as the output signal 112 when the output selection signal 110 is “0”, and sets the signal output from the variable delay block 109 as “1”.
• variable delay device of the present embodiment for example, when changing the delay amount of the input signal 111 to the delay amount 4 and the delay amount 3 as well, the variable delay block 108 is delayed by 4 and the variable delay block 109 is delayed.
• Set amount 3 and switch selector 107 from 0 to 1.
• FIG. 2 is a timing diagram showing an operation example when N is 3 in Embodiment 1 of the present invention.
• Delay length 4 (first selection signal 105a is "0", second selection signal 105b is “0", third selection signal 105 ⁇ is ";!) Is set in variable delay block 108 as 3-bit delay selection signal 105
• a signal with a timing different from the delay amount 3 set as shown in FIG. 12 may be output as an output signal.
• variable delay block 109 has a delay amount 3 as the 3-bit delay selection signal 106 (the first selection signal 106a is “;!”, The second selection signal 106b is “;!”, The third selection signal 106 ⁇ Is set to “0”), the output selection signal 110 is changed after the time when the signal with the timing different from the set delay amount is output as the output signal, and the selector 107 outputs the output signal 112.
• the signal to be changed is changed from the output of the variable delay block 108 to the output of the variable delay block 109.
• the selector 107 is switched by the output selection signal 110 after the time for which a signal with a timing different from the set delay amount is output, and the output signal 112 is changed from the delay amount 4 to the delay amount 3. Switch to.
• switching of a plurality of variable delay blocks has been described as being performed after a predetermined time has elapsed after changing the delay amount setting, but this is compared with the set value and the output value. It is also possible to carry out switching after confirming that it is within a predetermined error range. Note that the function of confirming that the error range is within a predetermined range can be realized using, for example, a phase comparator.
• FIG. 13 is a diagram showing an example of the circuit configuration and operation timing of the selector.
• the input signal is an S clock signal (0 and 1 alternate periodically)
• the circuit shown in Fig. 13 is applied to the selector 107 in Fig. 1 and the select operation is performed in synchronization with the clock.
• Clock It is possible to change the delay amount without causing a glitch.
• the output clock is selected so that the period is always longer. For this reason, when the delay amount setting is changed, the circuit using the output clock that does not exceed the maximum operating frequency of the circuit using the output clock can always be operated normally. Become
• variable delay device of the first embodiment is further provided with a delay output selecting means, and a plurality of variable delay blocks are referred to while referring to the set delay amount and the correlation table until the setting is completed.
• a variable delay device that performs switching will be described.
• FIG. 3 is a block diagram of the variable delay device according to Embodiment 2 of the present invention. 3 differs from the variable delay device shown in FIG. 1 in that an N-bit delay selection signal 301, which is a signal for selecting a delay amount with respect to the input signal 111, is supplied and the delay amount is changed to the variable delay block 108. , 109 is provided with a selection signal control unit 302 that performs control to output a selection signal to be set to either or both. In addition, the selection signal control unit 302 supplies the selector 107 with the output selection signal 110 and controls to output one of the variable delay blocks 108 and 109 as the output signal 112.
• an N-bit delay selection signal 301 which is a signal for selecting a delay amount with respect to the input signal 111
• FIG. 4 is a timing diagram showing that jitter of the output signal occurs in the second embodiment of the present invention.
• Fig. 4 when both N-bit delay selection signals 105 and 106 have a delay amount of 1, it is extremely difficult to make the delay times of the variable delay block 108 and the variable delay block 109 exactly the same in an actual device.
• the signal output as the output signal 112 is switched between the output from the variable delay block 108 and the output from the variable delay block 109, whereby the change interval force of the input signal 111 is reduced. Even so, there are three types of change intervals of the output signal 112: t ⁇ A t, t, and t + At, and jitter occurs in the output signal.
• FIG. 5 is a timing diagram showing an operation example when N is 3 in the second embodiment of the present invention.
• the 3-bit delay selection signal 301 is changed in order of delay amount 2, delay amount 4, and delay amount 3, delay amount 2 is set to variable delay block 108, and then delay amount 4 is set.
• the timing is as shown in Fig. 6.
• the selection signal control unit 302 performs control so that the delay amount 4 is also set to the variable delay block 108. To do.
• the selection signal control unit 302 sets the delay amount 3 for the variable delay block 109.
• variable delay block 109 After setting the delay amount 3 in the variable delay block 109, a signal different from the set value is output from the variable delay block 109.
• the signal output from the variable delay block 108 is output by the force selector 107. Since it is output as the signal 112, the output signal 112 is not affected by the output from the variable delay block 109.
• the selection signal control unit 302 After the signal corresponding to the delay set in the 3-bit delay selection signal 106 is output as the output signal of the variable delay block 109, the selection signal control unit 302 outputs the signal to the selector 107. By changing the output selection signal 110 and outputting the output signal of the variable delay block 109 as the output signal 112, it is possible to avoid outputting a signal different from the set delay amount.
• the delay amount is set for the variable delay block used at that time.
• the jitter of the output signal 112 can be reduced.
• Fig. 8 is a diagram showing how a signal with a timing different from the set delay amount is output when the delay amount setting is changed from 8 to 7.
• variable delay device in which a part of parallel variable delay blocks is shared to reduce the circuit scale will be described.
• FIG. 9 is a block diagram of a variable delay device according to Embodiment 3 of the present invention.
• the variable delay device of the present embodiment is intended to reduce the circuit scale by sharing a part of the variable delay blocks 108 and 109 in the variable delay devices of the first and second embodiments.
• the variable delay device shown in FIG. 9 is a variable delay device that outputs an input signal by delaying it by a delay amount corresponding to the delay selection signal, and delays the input signal 907 according to the N-bit delay selection signal.
• the selection signal control unit 906 is supplied with an N-bit delay selection signal 908 that is a signal for selecting a delay amount with respect to the input signal 907, and either of the variable delay blocks 904b and 904c, Alternatively, control is performed to output selection signals to be set for both and the variable delay block 904a. Further, the selection signal control unit 906 controls the selector 905 to supply the block selection signal 909 and output one of the variable delay blocks 904b and 904c as an output signal.
• variable delay block 904a The signal output from selector 905 is further output as output signal 9 10 via variable delay block 904a.
• the variable delay device according to the present embodiment is the same as the first implementation shown in FIG. In the variable delay device of the present embodiment, the delay elements lower than the variable delay blocks 108 and 109 and the selector are made common to form the variable delay block 904a, and the selector 107 is arranged in the middle stage to form the selector 905. is there.
• the usage method in which the delay selection signal is changed only by ⁇ 1 is to change the N-bit delay selection signal 908 from, for example, delay amount 3 to delay amount 4 and delay amount 4 to delay amount 3
• the configuration in which the delay element having the delay amount 1 is connected after the selector 905 is the case where the variable delay block 904a is set to the delay amount 1.
• the selector 902a has only one delay element (delay element 901a) with a delay amount 1. This is because, when switching between delay and non-delay, there is no other delay amount of only delay amount 0 or delay amount 1.
• variable delay device (Fig. 1) of the first embodiment is duplicated.
• the circuit scale is reduced when viewed as a whole variable delay device.
• one delay element is disposed in each of the variable delay blocks 904b and 904c, and two delay elements are disposed in the variable delay block 904a, thereby delaying the delay. It can be configured with 4 elements and 5 selectors, and further reduces the circuit scale with power S.
• the outputs of the variable delay block 904b and the variable delay block 904c Although the delay delay is added to the variable delay block 904a and the delay is added, the delay setting is reflected by parallelizing the variable delay block 904a by parallelizing the variable delay block 904a. You may comprise so that a delay may not arise.
• the first delay signal is used as the output of the variable delay block 904b or 904c, and the output of the variable delay block 904a obtained by parallelizing the second delay signal. It is good.
• variable delay device is a variable delay device that outputs an input signal with a delay amount corresponding to the delay selection signal, and outputs the input signal to the delay selection signal.
• a first variable delay block that delays and outputs the first delay amount set by the second delay amount, and a second delay block that outputs the input signal by delaying the second delay amount set by the delay selection signal.
• a variable delay block and a first output signal that switches between the output signals of the first and second variable delay blocks according to an output selection signal generated corresponding to the first and second delay amounts. 1 selection means.
• the output signals of the first and second variable delay blocks are switched and output according to the output selection signal generated corresponding to the first and second delay amounts. Even immediately after changing the delay amount of the variable delay device, it is possible to avoid outputting a signal having a timing different from the set delay amount.
• the first and second variable delay blocks include any one of a delay element, a signal input to the delay element, and a signal output from the delay element. And N sets (N is a natural number) of second selection means for selecting and outputting these according to the delay selection signal.
• the output selection signal is generated according to the magnitude relationship between the first and second delay amounts.
• the output selection signal is generated according to the magnitude relationship between the first and second delay amounts, the first selection is performed so that a signal having a timing different from the set delay amount is not output.
• the selection means can be switched.
• variable delay device of the present invention when the output selection signal changes the first delay amount, a signal with a delay amount different from a set value is output from the first variable delay block.
• the first selection means is switched so as to select the output signal of the second variable delay block.
• the first variable delay block if the first variable delay block outputs a signal having a delay amount different from the set value when the first delay amount is changed, the output signal of the second variable delay block is output.
• the variable delay device By selecting a signal, it is possible to provide a variable delay device that does not output a signal having a timing different from the set delay amount.
• variable delay device is such that the output selection signal is output after the second variable delay block has output a signal having a delay amount different from the set value.
• the selection means 1 is switched.
• variable delay device of the present invention includes a timing table that stores a correspondence relationship between the first and second delay amounts and the output selection signal.
• variable delay device of the present invention receives the supply of the delay selection signal, outputs the first delay selection signal to the first variable delay block, and outputs the first delay selection signal to the second variable delay block.
• a selection signal control unit configured to output a second delay selection signal and output the output selection signal to the first selection unit;
• variable delay device of the present invention when the selection signal control unit changes the first delay amount, a signal having a delay amount different from a set value is output from the first variable delay block. When there is no output, the first delay amount is changed.
• variable delay device of the present invention when the selection signal control unit changes the first delay amount, a signal having a delay amount different from a set value is output from the first variable delay block. When outputting, the second delay amount is changed.
• the selection signal control unit may be configured to perform the above-described processing after a time during which a signal with a delay amount different from the set value is output from the second variable delay block.
• the first selection means is switched.
• variable delay device of the present invention is configured such that the input signal is a delay amount corresponding to the delay selection signal.
• a variable delay device that outputs a delayed signal, the first and second variable delay blocks that delay the input signal according to the delay selection signal, and the first and second variable delay blocks, respectively.
• the first selection is performed by switching the output signal of the first and second variable delay blocks according to the block selection signal generated corresponding to the first and second delay amounts set
• a third variable delay block for delaying the output signal of the first selection means in accordance with the delay selection signal.
• the first selection unit can be switched so that a signal with a delay amount different from that of the setting is not output. Also, the first variable delay block outputs the input signal after delaying the first delay amount, and the second variable delay block outputs the input signal after delaying the second delay amount. Compared with the configuration in which the output of the output is selected by the selection means, part of the variable delay blocks that are duplicated (parallelized) are combined into one, so the circuit scale of the entire variable delay device is reduced be able to.
• the first and second variable delay blocks include any one of a delay element, a signal input to the delay element, and a signal output from the delay element. And (N ⁇ M) pairs, M is a natural number, and N> M), and the third variable delay block includes a delay element and second selection means for selecting and outputting the signal according to the delay selection signal. And M sets of second selection means for selecting and outputting either the signal input to the delay element or the signal output from the delay element in accordance with the delay selection signal.
• variable delay device of the present invention receives the supply of the delay selection signal, outputs the first delay selection signal to the first variable delay block, and outputs the first delay selection signal to the second variable delay block.
• Selection signal control for outputting a second delay selection signal, outputting a third delay selection signal to the third variable delay block, and outputting the block selection signal to the first selection means A part.
• variable delay device can provide a variable delay device in which a signal having a timing different from the set delay amount is not output even immediately after the delay amount of the variable delay device is changed. It has an effect and is useful as a variable delay device or the like for adjusting and outputting the timing of an input signal by varying the delay time.

Landscapes

• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Pulse Circuits (AREA)

Priority Applications (1)

Applications Claiming Priority (4)

Publications (1)

Family

ID=39032986

Family Applications (1)

Country Status (3)

Families Citing this family (3)

Citations (2)

Family Cites Families (6)

• 2007
  • 2007-06-21 JP JP2007163978A patent/JP5088941B2/ja not_active Expired - Fee Related
  • 2007-08-07 WO PCT/JP2007/065442 patent/WO2008018456A1/ja not_active Ceased
  • 2007-08-07 US US12/376,024 patent/US7898312B2/en not_active Expired - Fee Related

Patent Citations (2)

Also Published As

Similar Documents

Legal Events