JP2008067352A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2008067352A5 JP2008067352A5 JP2007163978A JP2007163978A JP2008067352A5 JP 2008067352 A5 JP2008067352 A5 JP 2008067352A5 JP 2007163978 A JP2007163978 A JP 2007163978A JP 2007163978 A JP2007163978 A JP 2007163978A JP 2008067352 A5 JP2008067352 A5 JP 2008067352A5
- Authority
- JP
- Japan
- Prior art keywords
- variable delay
- delay
- signal
- output
- selection signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007163978A JP5088941B2 (ja) | 2006-08-10 | 2007-06-21 | 可変遅延装置 |
| US12/376,024 US7898312B2 (en) | 2006-08-10 | 2007-08-07 | Variable delay apparatus |
| PCT/JP2007/065442 WO2008018456A1 (en) | 2006-08-10 | 2007-08-07 | Variable delay apparatus |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006217909 | 2006-08-10 | ||
| JP2006217909 | 2006-08-10 | ||
| JP2007163978A JP5088941B2 (ja) | 2006-08-10 | 2007-06-21 | 可変遅延装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008067352A JP2008067352A (ja) | 2008-03-21 |
| JP2008067352A5 true JP2008067352A5 (enExample) | 2010-05-06 |
| JP5088941B2 JP5088941B2 (ja) | 2012-12-05 |
Family
ID=39032986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007163978A Expired - Fee Related JP5088941B2 (ja) | 2006-08-10 | 2007-06-21 | 可変遅延装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7898312B2 (enExample) |
| JP (1) | JP5088941B2 (enExample) |
| WO (1) | WO2008018456A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6395647B2 (ja) * | 2015-03-18 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US11835580B2 (en) | 2020-12-01 | 2023-12-05 | Mediatek Singapore Pte. Ltd. | Circuit and method to measure simulation to silicon timing correlation |
| CN116633326A (zh) * | 2023-04-19 | 2023-08-22 | 深圳市紫光同创电子有限公司 | 一种延迟链电路及电子设备 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5389843A (en) * | 1992-08-28 | 1995-02-14 | Tektronix, Inc. | Simplified structure for programmable delays |
| SE501190C2 (sv) * | 1993-04-28 | 1994-12-05 | Ellemtel Utvecklings Ab | Digitalt styrd kristalloscillator |
| JP3378667B2 (ja) * | 1994-08-10 | 2003-02-17 | 株式会社アドバンテスト | 周期クロックの可変遅延回路 |
| US5646564A (en) * | 1994-09-02 | 1997-07-08 | Xilinx, Inc. | Phase-locked delay loop for clock correction |
| JPH0993082A (ja) | 1995-09-27 | 1997-04-04 | Ando Electric Co Ltd | 可変遅延回路 |
| JP3355894B2 (ja) * | 1995-09-27 | 2002-12-09 | 安藤電気株式会社 | 可変遅延回路 |
| US6008680A (en) | 1997-08-27 | 1999-12-28 | Lsi Logic Corporation | Continuously adjustable delay-locked loop |
| JP2001075671A (ja) * | 1999-09-08 | 2001-03-23 | Nec Corp | 位相補償回路 |
-
2007
- 2007-06-21 JP JP2007163978A patent/JP5088941B2/ja not_active Expired - Fee Related
- 2007-08-07 US US12/376,024 patent/US7898312B2/en not_active Expired - Fee Related
- 2007-08-07 WO PCT/JP2007/065442 patent/WO2008018456A1/ja not_active Ceased
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5955764B2 (ja) | 半導体装置のデータ出力タイミング制御回路 | |
| KR100855980B1 (ko) | 쉬프터와 가산기를 이용하여 지연 시간을 조절하는 지연고정 루프 및 클럭 지연 방법 | |
| JP2012504263A5 (enExample) | ||
| JP4718576B2 (ja) | Ddrメモリデバイスのデータ出力のデューティサイクル制御及び正確な調整のための複数の電圧制御された遅延ラインの利用 | |
| JP2010088108A5 (enExample) | ||
| JP2008199573A5 (enExample) | ||
| JP2008157971A5 (enExample) | ||
| JP2007536831A (ja) | クロック同期回路におけるクロック捕捉 | |
| JP2009278528A5 (enExample) | ||
| JP2010507342A5 (enExample) | ||
| TW200636754A (en) | Clock generator and clock duty cycle correction method | |
| TWI745493B (zh) | 半導體裝置及半導體系統 | |
| WO2005109647A3 (en) | Adjustable frequency delay-locked loop | |
| KR101163048B1 (ko) | 출력 타이밍 제어회로 및 그를 이용하는 반도체 장치 | |
| JP2006041818A5 (enExample) | ||
| KR20150007522A (ko) | 클럭 지연 검출회로 및 이를 이용하는 반도체 장치 | |
| WO2008024659A3 (en) | Circuits to delay a signal from a memory device | |
| JP2008067352A5 (enExample) | ||
| US7292080B2 (en) | Delay locked loop using a FIFO circuit to synchronize between blender and coarse delay control signals | |
| JP2009250774A5 (enExample) | ||
| US7886176B1 (en) | DDR memory system for measuring a clock signal by identifying a delay value corresponding to a changed logic state during clock signal transitions | |
| KR100857449B1 (ko) | 반도체 메모리 장치의 dll 회로 | |
| JP2009077042A5 (enExample) | ||
| TWI568189B (zh) | 數位控制延遲鎖定迴路參考產生器 | |
| JP5088941B2 (ja) | 可変遅延装置 |