JP5088941B2 - 可変遅延装置 - Google Patents

可変遅延装置 Download PDF

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Publication number
JP5088941B2
JP5088941B2 JP2007163978A JP2007163978A JP5088941B2 JP 5088941 B2 JP5088941 B2 JP 5088941B2 JP 2007163978 A JP2007163978 A JP 2007163978A JP 2007163978 A JP2007163978 A JP 2007163978A JP 5088941 B2 JP5088941 B2 JP 5088941B2
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JP
Japan
Prior art keywords
variable delay
delay
output
signal
selection signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007163978A
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English (en)
Japanese (ja)
Other versions
JP2008067352A5 (enExample
JP2008067352A (ja
Inventor
英毅 青柳
仁 浅野
和哉 鴇
道明 松尾
卓 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2007163978A priority Critical patent/JP5088941B2/ja
Priority to US12/376,024 priority patent/US7898312B2/en
Priority to PCT/JP2007/065442 priority patent/WO2008018456A1/ja
Publication of JP2008067352A publication Critical patent/JP2008067352A/ja
Publication of JP2008067352A5 publication Critical patent/JP2008067352A5/ja
Application granted granted Critical
Publication of JP5088941B2 publication Critical patent/JP5088941B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
JP2007163978A 2006-08-10 2007-06-21 可変遅延装置 Expired - Fee Related JP5088941B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007163978A JP5088941B2 (ja) 2006-08-10 2007-06-21 可変遅延装置
US12/376,024 US7898312B2 (en) 2006-08-10 2007-08-07 Variable delay apparatus
PCT/JP2007/065442 WO2008018456A1 (en) 2006-08-10 2007-08-07 Variable delay apparatus

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006217909 2006-08-10
JP2006217909 2006-08-10
JP2007163978A JP5088941B2 (ja) 2006-08-10 2007-06-21 可変遅延装置

Publications (3)

Publication Number Publication Date
JP2008067352A JP2008067352A (ja) 2008-03-21
JP2008067352A5 JP2008067352A5 (enExample) 2010-05-06
JP5088941B2 true JP5088941B2 (ja) 2012-12-05

Family

ID=39032986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007163978A Expired - Fee Related JP5088941B2 (ja) 2006-08-10 2007-06-21 可変遅延装置

Country Status (3)

Country Link
US (1) US7898312B2 (enExample)
JP (1) JP5088941B2 (enExample)
WO (1) WO2008018456A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6395647B2 (ja) * 2015-03-18 2018-09-26 ルネサスエレクトロニクス株式会社 半導体装置
US11835580B2 (en) 2020-12-01 2023-12-05 Mediatek Singapore Pte. Ltd. Circuit and method to measure simulation to silicon timing correlation
CN116633326A (zh) * 2023-04-19 2023-08-22 深圳市紫光同创电子有限公司 一种延迟链电路及电子设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5389843A (en) * 1992-08-28 1995-02-14 Tektronix, Inc. Simplified structure for programmable delays
SE501190C2 (sv) * 1993-04-28 1994-12-05 Ellemtel Utvecklings Ab Digitalt styrd kristalloscillator
JP3378667B2 (ja) * 1994-08-10 2003-02-17 株式会社アドバンテスト 周期クロックの可変遅延回路
US5646564A (en) * 1994-09-02 1997-07-08 Xilinx, Inc. Phase-locked delay loop for clock correction
JPH0993082A (ja) 1995-09-27 1997-04-04 Ando Electric Co Ltd 可変遅延回路
JP3355894B2 (ja) * 1995-09-27 2002-12-09 安藤電気株式会社 可変遅延回路
US6008680A (en) 1997-08-27 1999-12-28 Lsi Logic Corporation Continuously adjustable delay-locked loop
JP2001075671A (ja) * 1999-09-08 2001-03-23 Nec Corp 位相補償回路

Also Published As

Publication number Publication date
WO2008018456A1 (en) 2008-02-14
US7898312B2 (en) 2011-03-01
US20090315605A1 (en) 2009-12-24
JP2008067352A (ja) 2008-03-21

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