WO2007118026A2 - Procédé pour améliorer la couverture de niveaux et de chargement de motifs pour films diélectriques - Google Patents

Procédé pour améliorer la couverture de niveaux et de chargement de motifs pour films diélectriques Download PDF

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Publication number
WO2007118026A2
WO2007118026A2 PCT/US2007/065592 US2007065592W WO2007118026A2 WO 2007118026 A2 WO2007118026 A2 WO 2007118026A2 US 2007065592 W US2007065592 W US 2007065592W WO 2007118026 A2 WO2007118026 A2 WO 2007118026A2
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WIPO (PCT)
Prior art keywords
layer
plasma
dielectric layer
silicon
chamber
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PCT/US2007/065592
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English (en)
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WO2007118026A3 (fr
Inventor
Mihaela Balseanu
Li-Qun Xia
Mei-Yee Shek
Hichem M'saad
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Applied Materials, Inc.
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Priority claimed from US11/668,911 external-priority patent/US7601651B2/en
Priority claimed from US11/693,005 external-priority patent/US7780865B2/en
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to CN2007800121574A priority Critical patent/CN101416293B/zh
Publication of WO2007118026A2 publication Critical patent/WO2007118026A2/fr
Publication of WO2007118026A3 publication Critical patent/WO2007118026A3/fr

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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Definitions

  • Embodiments of the present invention generally relate to a method and apparatus for semiconductor processing. Specifically, embodiments of the present invention relate to a method and apparatus for depositing a conformal dielectric film.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • CVD and PECVD dielectric layers can be used as different layers in semiconductor devices.
  • the dielectric layers may be used as intermetal dielectric layers between conductive lines or interconnects in a device.
  • the dielectric layers may be used as barrier layers, etch stops, or spacers, as well as other layers.
  • Dielectric layers that are used for applications such as barrier layers and spacers are typically deposited over features, e.g., horizontal interconnects for subsequently formed lines, vertical interconnects (vias), gate stacks, etc., in a patterned substrate.
  • the deposition provides a conformal layer.
  • the barrier layer material may overloaf, that is, deposit excess material on the shoulders of a via and deposit too little material in the base of the via, forming a shape that looks like the side of a loaf of bread.
  • the phenomena is also known as footing because the base of the via has a profile that looks like a foot.
  • the shoulders of a via may merge to form a joined, sealed surface across the top of the via.
  • the film thickness non-uniformity across the wafer can negatively impact the drive current improvement from one device to another. Modulating the process parameters alone does not significantly improve the step coverage and pattern loading problems.
  • Embodiments of the present invention provide a method for forming a dielectric film on a substrate comprising placing a substrate with at least one formed feature across a surface of the substrate into a chamber, depositing a dielectric layer, treating the dielectric layer with plasma, determining the thickness of the dielectric layer, and repeating the depositing a dielectric layer, treating the dielectric layer with a plasma, and determining the thickness of the dielectric layer.
  • a method of forming a layer on a patterned substrate in a chamber comprises exposing the patterned substrate to a silicon-containing precursor, such as octamethylcyclotetrasiloxane, in the presence of a plasma to deposit a layer on the patterned substrate and treating the layer after it is deposited with a plasma from an oxygen-containing gas, such as oxygen gas.
  • the exposing and treating are repeated until a desired thickness of the layer is obtained.
  • the layer may be a silicon oxide or carbon-doped silicon oxide layer.
  • a method of forming a layer on a patterned substrate in a chamber comprises exposing the patterned substrate to a silicon- containing precursor in the presence of a plasma to deposit a layer on the patterned substrate, treating the layer after it is deposited with a plasma from an nitrogen- containing gas, and repeating the exposing and treating until a desired thickness of the layer is obtained.
  • Embodiments of the present invention also provide a method of controlling the step coverage and pattern loading of a layer on a substrate.
  • the method comprises placing a substrate with at least one formed feature across a surface of the substrate into a chamber.
  • a dielectric layer is deposited on the substrate, and the dielectric layer is etched with a plasma from oxygen or a halogen-containing gas selected from the group consisting of fluorine, chlorine, bromine, and combinations thereof to provide a desired profile of the dielectric layer on the at least one formed feature.
  • the method comprises placing a substrate with at least one formed feature across a surface of the substrate into a chamber and depositing a dielectric layer on the substrate.
  • the feature comprises a top surface, a sidewall surface, and a bottom surface.
  • the dielectric layer is deposited to a greater thickness on the top surface than on the bottom surface and sidewall surface.
  • the dielectric layer is then etched with a plasma from oxygen or a halogen- containing gas selected from the group consisting of fluorine, chlorine, bromine, and combinations thereof.
  • the dielectric layer is etched at a higher rate on the top surface than on the sidewall surface and bottom surface.
  • the depositing and etching of the dielectric layer is repeated for one or more times to provide a desired profile of the dielectric layer on the at least one formed feature.
  • the method comprises placing a substrate with at least one formed feature across a surface of the substrate into a chamber and depositing a silicon nitride dielectric layer on the substrate.
  • the feature comprises a top surface, a sidewall surface, and a bottom surface.
  • the silicon nitride dielectric layer is deposited to a greater thickness on the top surface than on the bottom surface and sidewall surface.
  • the silicon nitride dielectric layer is then etched with a NF 3 plasma at a higher etch rate on the top surface than on the sidewall surface and bottom surface to provide a desired profile of the silicon nitride dielectric layer on the at least one formed feature.
  • the depositing and etching of the silicon nitride dielectric layer may be repeated for one or more times to provide the desired profile.
  • Figure 1 is a flow chart of an embodiment of a deposition process.
  • Figure 2 is a flow chart of an additional embodiment of a deposition process.
  • Figure 3A is a sketch of a dielectric layer profile on a feature of a substrate according to the prior art.
  • Figure 3B is a sketch of a dielectric layer profile on a feature of a substrate according to an embodiment of the invention.
  • Figure 4 is a graph showing the resulting bottom thickness for features in dense and isolated regions of a substrate for different etched film thicknesses according to an embodiment of the invention.
  • Figure 5 is a graph showing the resulting bottom pattern loading effect for different etched film thicknesses according to an embodiment of the invention.
  • Figure 6 is a flow chart of an embodiment of a deposition process.
  • Figure 7 is a graph showing the thickness of a layer during a deposition process performed according to an embodiment of the invention.
  • Figure 8 is a graph showing the thickness of a layer deposited on a substrate according to an embodiment of the invention relative to the amount of time the substrate is exposed to a precursor.
  • Figure 9 is a schematic diagram of the deposition of a layer on a substrate according to an embodiment of the invention.
  • Figure 10 is a flow chart of an additional embodiment of a deposition process.
  • Figure 11 is a flow chart of an additional embodiment of a deposition process.
  • the present invention provides a method and apparatus for depositing a conformal dielectric layer over a formed feature.
  • Films that can benefit from this process include dielectric materials such as silicon oxide, silicon oxynitride, or silicon nitride films that may be used as spacers or etch stop layers, for example.
  • the films may be carbon doped, hydrogen doped, or contain some other chemical or element to tailor the dielectric properties.
  • the film may be carbon doped or nitrogen doped.
  • the films may be SiCN, SiOC, SiOCN, SiBN, SiBCN, SiC, BN, or BCN films.
  • a combination of thin layers that have been individually deposited and plasma treated provide a more conformal dielectric layer than a single thick dielectric layer.
  • the chambers that may be used for the processes described herein include the PRODUCER ® P3 chamber, PRODUCER ® APFTM PECVD chamber, PRODUCER ® BLACK DIAMOND ® PECVD chamber, PRODUCER ® BLOK ® PECVD chamber, PRODUCER ® DARC PECVD chamber, PRODUCER HARP chamber, PRODUCER ® PECVD chamber, PRODUCER SACVD chamber, PRODUCER ® SE STRESS NITRIDE PECVD chamber, and PRODUCER ® TEOS FSG PECVD chamber, each of which are commercially available from Applied
  • the chambers may be configured individually, but are most likely part of an integrated tool.
  • the processes may be performed on any substrate, such as a 200 mm or 300 mm substrate or other medium suitable for semiconductor or flat panel display processing.
  • the processing conditions described below are provided with respect to a PRODUCER ® SE STRESS NITRIDE PECVD chamber, which has two isolated processing regions. Thus, the flow rates experienced per each substrate processing region are half of the flow rates into the chamber.
  • FIG. 1 is a flow chart of an embodiment of a deposition process 100. All of the process steps of deposition process 100 may be performed in the same chamber.
  • the process 100 begins with start step 110 that includes placing a substrate with at least one formed feature across its surface into a chamber.
  • the formed feature may be any type of formed feature such as a via, interconnect, or gate stack.
  • a dielectric layer is deposited by CVD or PECVD during thin dielectric layer deposition step 120.
  • the thin dielectric layer may be silicon oxide, silicon oxynitride, or silicon nitride layer, for example.
  • the layer may be carbon doped or nitrogen doped.
  • the thin dielectric layer may have a thickness of about 1 A to about 8 A.
  • the pressure of the chamber is about 100 mTorr to about 8 Torr, and 2 to 8 Torr is preferred.
  • the thin dielectric layer is deposited during deposition step 120 for about 2 to about 5 seconds and then the thin dielectric layer is plasma treated during step 130.
  • the plasma treatment step 130 may include using an inert gas or a reactive gas.
  • the thickness of the deposited layers is next analyzed or estimated during thickness determination step 140. If the thickness of the deposited layer or layers is equal to or greater than a given desired thickness, the process 100 is completed during step 160. During end step 160 the substrate undergoes additional processing and is removed from the chamber. If the thickness is not equal to or greater than a given desired thickness, then the deposition step 120 and plasma treatment step 130 are repeated during repeat process 150.
  • FIG. 1 is a generalization to provide a framework for the individual processes illustrated by Figures 2, 6, and 10-1 1.
  • the process steps that are similar to Figure 1 have identical reference numerals in Figures 2, 6, and 10-1 1. However, slight process modifications may be appropriate.
  • FIG. 2 is a flow chart of an embodiment of a deposition process 200.
  • a substrate having at least one formed feature across its surface is placed into a chamber, as shown in step 202.
  • the feature has a top surface, a sidewall surface, and a bottom surface.
  • a dielectric layer is deposited on the substrate, as shown in step 204.
  • the dielectric layer may be deposited by CVD or PECVD.
  • the dielectric layer may be a silicon nitride, silicon oxide, or silicon oxynitride layer, for example.
  • the layer may be any of the carbon or nitrogen-doped films described above.
  • the deposition of the dielectric layer provides a greater thickness of the dielectric layer on the top surface than on the bottom surface and the sidewall surface.
  • the dielectric layer is etched with a plasma from oxygen or a halogen-containing gas, as shown in step 206.
  • the halogen-containing gas is selected from the group consisting of fluorine, chlorine, bromine, and combinations thereof.
  • An oxygen plasma may be provided by oxygen gas (O 2 ) or other oxygen- containing gases.
  • the thickness of the dielectric layer may be then analyzed or estimated during a thickness determination step as described above with respect to Figure 1. If the etching of the dielectric layer in step 206 provides a desired profile of the dielectric layer on the at least one formed feature, the process is ended in step 208.
  • the desired profile may be a conformal or substantially conformal profile which has less thickness variation among the sidewall, top, and bottom surfaces of the feature than after the deposition of the dielectric layer and prior to the etching. In other words, the desired profile has an improved step coverage, i.e., a lower percentage of film thickness difference between different surfaces of a feature.
  • a repeat step 210 may be performed.
  • the repeat step 210 includes deposition of an additional amount of the dielectric layer and then etching the dielectric layer.
  • the repeat step 210 may be performed several times, such as between one and 100 times, e.g., between one and six times, to obtain a desired profile of the dielectric layer on the at least one formed feature.
  • the dielectric layer may be etched in the same chamber in which the dielectric layer is deposited or in a different chamber that is part of the same integrated tool as the deposition chamber and is connected to the deposition chamber by a transfer chamber of the integrated tool.
  • the oxygen or halogen-containing gas may be introduced into the chamber individually or in combination with an inert gas, such as argon or helium.
  • the etch step 206 is performed using a plasma that is generated remotely or in situ.
  • the length of the etch step 206 may be at least 0.1 seconds, such as between about 0.1 seconds and about 45 seconds, e.g., between about 15 seconds and about 45 seconds.
  • the etch profile can be configured to match the deposition profile by adjusting the halogen-containing gas flow rate and length of exposure.
  • the etch rate may be higher on the top surface of the feature than on the sidewall surface or bottom surface of the feature.
  • the etch rate on the top surface is about 10% higher than the etch rate on the sidewall surface or the bottom surface.
  • an etch rate of about 50 percent may be desirable.
  • an etch rate of about 50 percent corresponds to an etch process that removes about 50 percent of the thickness of the dielectric layer that is deposited.
  • deposition step 204 may alternatively be a two part deposition process, such as two seconds of plasma at a first power and precursor partial pressure and two additional seconds at a second power and second precursor partial pressure.
  • the plasma may be produced by exposing oxygen or a halogen-containing gas selected from the group consisting of fluorine, chlorine, bromine, and combinations thereof to microwave energy in a remote plasma source that is connected to the chamber in which the dielectric layer is deposited.
  • the plasma may be generated from NF 3 , which provides reactive fluorine species.
  • the NF 3 may be introduced into the chamber at a flow rate between about 10 seem and about 20 slm.
  • the NF 3 may be introduced into the chamber with argon or helium as a dilution gas. The argon and helium may also help sustain the plasma in the chamber.
  • the argon or helium may be introduced into the chamber at a flow rate between about 100 seem and about 20 slm.
  • the pressure in the chamber during the etch may be between about 10 mTorr and about 760 Torr, and the temperature of a substrate support in the chamber may be set to between about 100 0 C and about 650 0 C.
  • the plasma may be generated by RF power.
  • the RF power may be provided at a high frequency, such as between about 1 MHz and about 13.56 MHz, e.g., about 2 MHz to about 13.56 MHz, a low frequency between about 100 kHz and about 1 MHz, e.g., between about 100 kHz and about 400 kHz, or a mixed frequency comprising a frequency between about 1 MHz and about 13.56 MHz, e.g., about 2 MHz to about 13.56 MHz, a low frequency between about 100 kHz and about 1 MHz, e.g., between about 100 kHz and about 400 kHz.
  • the halogen-containing gas that is selected from the group consisting of fluorine, chlorine, bromine, and combinations thereof and is used as an etching gas may be NF 3 , or a carbon and fluorine-containing gas, such as CF 4 or C 4 F 8 .
  • the oxygen or halogen-containing gas may be introduced into the chamber at a flow rate between about 10 seem and about 20 slm.
  • the oxygen or halogen-containing gas may be introduced into the chamber with argon or helium as a dilution gas.
  • the argon and helium may also help sustain the plasma in the chamber.
  • the argon or helium may be introduced into the chamber at a flow rate between about 100 seem and about 20 slm.
  • the pressure in the chamber during the etch may be between about 10 mTorr and about 760 Torr, and the temperature of a substrate support in the chamber may be set to between about 100 0 C and about 650 0 C.
  • the spacing between a showerhead electrode and a substrate support electrode in the chamber may be between about 100 mils and about 3000 mils. The spacing may be adjusted to control the stability of the plasma.
  • Embodiments of the invention include process sequences in which a single deposition step 204 and a single etching step 206 are performed and process sequences that include a repeat step 210 with multiple deposition and etching steps.
  • a process sequence comprising a single deposition step and a single etching step may be performed for a dielectric layer that has a high etch rate on a sidewall surface of a feature of the dielectric layer relative to the etch rate on a top surface of a feature of the dielectric layer.
  • the etch rate on the sidewall surface may be at least about 10% of the rate at which the dielectric layer is etched from the top surface.
  • Dielectric deposition processes that provide a lower ion bombardment on the sidewalls of features than on the top or bottom of features can result in higher etch rates of the dielectric on the sidewall rather than on the bottom or top of features.
  • a process sequence comprising multiple deposition and etching steps may be performed for a dielectric layer that has a low etch rate on a sidewall surface of a feature of the dielectric layer relative to the etch rate on a top surface of a feature of the dielectric layer.
  • the etch rate on the sidewall surface may be less than about 10% of the rate at which the dielectric layer is etched from the top surface.
  • the etch rates may be determined by measuring the thickness of the dielectric layer at the bottom, sidewall, and top of a feature using SEM or TEM cross-sections before and after the dielectric layer is etched and calculating the thickness etched per the time period of the etch. Increasing the number of deposition and etching cycles may improve the pattern loading effect.
  • a process sequence comprising two or three deposition and etching cycles may be performed for dielectric layers for use as etch stop liners for features sites of 90 nm and below.
  • the dielectric layer may be deposited to a thickness of between about 300 A and about 400 A in each cycle, and a thickness of between about 100 A and about 200 A of the dielectric layer may be etched in each cycle.
  • Experimental testing of embodiments of the invention shows that the etch profile can be controlled to match the deposition profile, that is, to provide a higher etch rate across the top surface of formed features than at the bottom or along the sidewalls of the formed feature.
  • Figure 3A is a sketch of a SEM of a dielectric layer 302 formed on a feature 304 of a substrate 306 according to the prior art.
  • the dielectric layer has a non-uniform profile with a greater thickness of the top 308 of the feature than on the sidewall 310 and bottom 312 of the feature.
  • Figure 3B is a sketch of a SEM of a dielectric layer 320 formed on a feature 304 according to an embodiment of the invention.
  • the dielectric layer 320 has a more uniform profile on the feature 304 than the dielectric layer 302.
  • a lower pattern loading effect percentage reflects a higher film thickness uniformity across a substrate.
  • Figures 4 and 5 show the effect of the length of the etch period, as reflected by the film thickness etched, on the bottom dielectric layer thickness for substrates with isolated (iso) and dense feature spacings and the pattern loading effect respectively for NF 3 etches using 50 seem of NF 3 , 3 L of argon, 100 W of low frequency RF power at 350 kHz, a chamber pressure of 1.5 Torr, and a spacing of 1000 mils.
  • Etch periods of 15-45 seconds were used, which corresponded to 100 A to 300 A of etched film thickness.
  • the bottom pattern loading effect improved significantly, i.e., about 30%, with the longer etch period.
  • a comparison of pattern loading and bottom thickness as a function of the type of etch was performed using NF 3 as the fluorine-containing etching gas on a silicon nitride dielectric layer.
  • No etch, a low frequency RF plasma etch at 100 W, a high frequency RF plasma etch at 50 W, and a remote plasma source etch were compared for a process sequence comprising depositing 400 A of a silicon nitride dielectric layer, etching 200 A of the silicon nitride dielectric layer, and then depositing 450 A of the silicon nitride dielectric layer.
  • the low frequency RF plasma etch and the high frequency RF plasma etch provided similar pattern loading effect results, while the remote plasma source etch resulted in a greater pattern loading effect and an etch rate uniformity of more than 20 percent. It is believed that the RF plasma in situ etching methods are more efficient in providing an etch profile that is similar to the deposition profile, i.e., higher etch rates on the top surface of features and slower etch rates on the sidewall surface of features, than remote plasma etching methods as the etching species are accelerated toward the substrate surface directionally by the sheath voltage in in situ RF methods while the etching profile is more isotropic in remote plasma etching methods.
  • the embodiment of Figure 2 has been described primarily with respect to SiN layers, the embodiment of Figure 2 may also be used for other dielectric layers, such as SiO, SiN, SiCN, SiOC, SiOCN, SiBN, SiBCN, SiC, BN, or BCN layers.
  • the etch step 206 includes an oxygen- containing gas that provides reactive oxygen species that etch carbon-containing layers and a halogen-containing gas.
  • the halogen-containing gas and the oxygen- containing gas may be used simultaneously or sequentially.
  • the layer may be exposed to a plasma of an oxygen-containing gas and then a plasma of a halogen-containing gas.
  • Figure 6 is a flow chart of an embodiment of a deposition process 600. All of the process steps of deposition process 600 may be performed in the same chamber.
  • the process 600 begins with start step 610 that includes placing a substrate with at least one formed feature across its surface, i.e., a patterned substrate, into a chamber.
  • the formed feature may be any type of formed feature such as a via, interconnect, or gate stack, for example.
  • Deposition of a dielectric layer is performed by exposing the substrate to a silicon-containing precursor simultaneously with plasma present in the chamber during precursor and plasma step 620.
  • the silicon-containing precursor can include octamethylcyclotetrasiloxane (OMCTS), methyldiethoxysilane (MDEOS), bis(tertiary- butylamino)silane (BTBAS), tridimethylaminosilane (TriDMAS), trisdimethylaminosilane (TrisDMAS), silane, disilane, dichlorosilane, trichlorosilane, dibromosilane, silicon tetrachloride, silicon tetrabromide, or combinations thereof.
  • OCTS octamethylcyclotetrasiloxane
  • MDEOS methyldiethoxysilane
  • BBAS bis(tertiary- butylamino)silane
  • TriDMAS tridimethylaminosilane
  • TrisDMAS tris
  • OMCTS and silane are preferred silicon-containing precursors.
  • the plasma is provided at about 50 W to about 3000 W of RF power at a frequency of 13.56 MHz and / or 350KHz.
  • Gases that are optionally introduced into the chamber at the same time as the silicon-containing precursor include helium, nitrogen, oxygen, nitrous oxide, and argon.
  • Oxygen and/or helium are the preferred additional gases for introduction to the chamber if an additional gas is used.
  • Helium or other inert gases may be used as a carrier gas.
  • the plasma, precursor, and optional additional gases introduced during step 620 are followed by the introduction of an oxygen-containing gas, such as oxygen gas or nitrous oxide, to the chamber during oxygen purge step 630.
  • the oxygen purge step 630 is performed by introducing the oxygen-containing gas into the chamber at a time period and partial pressure that are selected to purge the residual silicon-containing precursor and optional additional gases.
  • an oxygen-containing gas such as oxygen or nitrous oxide, is introduced into the chamber.
  • the plasma is provided at about 50 W to about 3000 W for about 0.1 seconds to about 600 seconds.
  • the silicon-containing precursor may be introduced into the chamber at a flow rate of between about 5 seem and about 1000 seem.
  • An optional carrier gas e.g., helium
  • the ratio of the flow rate of the silicon-containing precursor, e.g., octamethytcyclotetrasiloxane, to the flow rate of the carrier gas, e.g., helium, into the chamber is about 1 :1 or greater, such as between about 1 :1 and about 1 :100.
  • the chamber pressure may be greater than about 5 mTorr, such as between about 1.8 Torr and about 10 Torr, and the temperature of a substrate support in the chamber may be between about 125°C and about 580 0 C while the silicon-containing precursor is flowed into the chamber to deposit the layer.
  • the temperature is below about 500 0 C.
  • the silicon- containing precursor may be flowed into the chamber for a period of time sufficient to deposit a layer having a thickness of between about 5 A and about 2000 A.
  • the silicon-containing precursor may be flowed into the chamber for between about 0.1 seconds and about 120 seconds.
  • the plasma during step 620 may be provided by RF power at between about 50 W and about 3000 W at a frequency of 13.56 MHz or 350 KHz.
  • the RF power may be provided to a showerhead, i.e., a gas distribution assembly, and/or a substrate support of the chamber.
  • the spacing between the showerhead and the substrate support is greater than about 230 mils, such as between about 350 mils and about 800 mils.
  • the flow of the silicon-containing precursor into the chamber and the RF power are then stopped, and any remaining silicon-containing precursor is purged from the chamber by introducing an oxygen-containing gas, such as oxygen gas, nitrous oxide, or a combination thereof into the chamber in step 630.
  • the oxygen- containing gas may be introduced into the chamber at a flow rate of between about 100 and about 20000 seem.
  • the oxygen-containing gas may be flowed into the chamber for a period of time such as between about 0.1 seconds and about 60 seconds.
  • the chamber pressure may be between about 5 mTorr and about 10 Torr, and the temperature of a substrate support in the chamber may be between about 125°C and about 580 0 C while the oxygen-containing gas is flowed into the chamber.
  • an oxygen plasma treatment is performed in the chamber to treat the layer that is deposited on the substrate from the silicon- containing precursor, as described in step 640.
  • the oxygen-containing gas may be introduced into the chamber at a flow rate of between about 100 and about 20000 seem.
  • the oxygen-containing gas may be flowed into the chamber for a period of time such as between about 0.1 seconds and about 120 seconds.
  • the oxygen plasma may be provided by applying a RF power of between about 50 W and about 3000 W in the chamber at a frequency of 13.56 MHz and/ or 350KHz.
  • the chamber pressure may be between about 5 mTorr and about 10 Torr, and the temperature of a substrate support in the chamber may be between about 125°C and about 580 0 C while the oxygen-containing gas is flowed into the chamber.
  • the oxygen plasma treatment may be terminated by interrupting the RF power and the flow of the oxygen-containing gas into the chamber.
  • the thickness of the deposited dielectric layer is then analyzed or estimated during thickness determination step 650. If the thickness of the deposited layer or layers is equal to or greater than a given desired thickness, the process 600 is completed during end step 660. During end step 660, the substrate undergoes additional processing and is removed from the chamber. If the thickness is not equal to or greater than a given desired thickness, then the deposition step 620 and plasma treatment step 630 are repeated during repeat process 655.
  • the thickness determination step 650 and repeat process 655 may be repeated multiple times until the desired film thickness is obtained, for example, about 1 to about 6 repetitions may be performed.
  • the flow of the silicon-containing precursor into the chamber is then resumed to deposit an additional amount of the dielectric layer.
  • the chamber is purged and then an oxygen plasma treatment as described above is performed. Multiple cycles of deposition, purging, and plasma treatment may be performed until the desired thickness of dielectric layer is obtained.
  • Nitrous oxide and oxygen were compared for use in the oxygen plasma treatment step 640. Scanning electron micrographs of a film deposited using a nitrous oxide plasma and a film deposited using an oxygen plasma indicate that the film deposited using an oxygen plasma had the better pattern loading effect and step coverage of the two films.
  • the embodiment described with respect to Figure 6 is a pulsed layer deposition (PLD), as pulses of the silicon-containing precursor separated by oxygen plasma treatments provide sequentially deposited thin layers that form a complete layer.
  • Figure 7 is a graph showing the thickness of a layer during a dielectric deposition performed using the cycles of deposition and plasma treatment described above relative to the deposition time or cycle number. The points at which the plasma treatments are performed are indicated on the graph. Figure 7 shows that in a similar process that did not include the plasma treatments, there were periods in which the deposition rate was noticeably decreased, while the process provided herein did not exhibit such periods.
  • Figure 8 shows that the thickness deposited per period of time of flowing the silicon-containing precursor (OMCTS) into the chamber in the presence of a plasma (plasma soak time in Figure 8) in a similar process that did not include the plasma treatments (dep only in Figure 8) was less than the thickness deposited per period of time of flowing the silicon- containing precursor into the chamber in the presence of a plasma in a process that includes the plasma treatments according to an embodiment of the invention.
  • deposition rates approximately 10-fold higher than deposition rates for atomic layer deposition (ALD) processes have been obtained using processes according to embodiments of the invention.
  • the processes described herein can be performed in conventional chemical vapor deposition chambers, such as PRODUCER PECVDTM chambers.
  • the oxygen plasma treatment enhances the deposition rate by removing methyl groups (-CH 3 ) that are retained in the deposited layer, as it has been observed that the presence of methyl groups in the deposited layer can hinder further deposition.
  • the oxygen plasma treatment replaces at least some if not many of the methyl groups in the deposited layer with hydroxyl groups (-OH) that can serve as nucleation sites for the attachment of another layer of the silicon- containing precursor.
  • Figure 9 shows an example of the effect of an oxygen plasma treatment on a layer that is deposited from octamethylcyclotetrasiloxane (OMCTS). For simplicity, only one OMCTS molecule of the layer is shown.
  • OMCTS octamethylcyclotetrasiloxane
  • step 902 of Figure 9 OMCTS is reacted in the presence of a plasma and a substrate containing a Si-OH bond.
  • the plasma forms an OMCTS radical.
  • the OMCTS radical then attaches to the hydroxyl group of the substrate, as shown in step 904.
  • an oxygen plasma treatment with oxygen gas replaces at least some of the methyl groups in the deposited OMCTS layer with hydroxyl groups.
  • a thin, uniform dielectric layer having a thickness of only between about 3 A and about 25 A can be reliably deposited when a self- saturating precursor is used as a precursor to deposit the layer.
  • a 1 A thickness range of the layer within a single 300 mm substrate has been obtained using the conditions provided herein.
  • a self-saturating precursor is a precursor that deposits one thin layer, e.g., one molecular layer of the precursor, on a substrate. The presence of the thin dielectric layer hinders the further deposition of additional layers of the dielectric material from the precursor under the processing conditions used to deposit the thin layer.
  • OMCTS is a preferred self-saturating precursor as it contains a large number of methyl groups that result in a self- saturating deposition of layer.
  • a conformal first layer may be deposited from OMCTS because as soon as the surface of the underlying substrate is covered with OMCTS molecules, the presence of the Si-CH 3 bonds at the surface of the deposited layer substantially hinders further deposition until some of the methyl groups are removed by the oxygen plasma treatment described above.
  • the deposition of each molecular layer of OMCTS can be well controlled, which enhances the step coverage of the final layer.
  • an oxide layer deposited according to an embodiment of the invention was measured on the side, bottom, and top of features in patterned substrates having regions with a high density of features (dense areas) and low density of features (isolated areas).
  • a sidewall/top coverage of 75% was achieved in dense areas, and a sidewall/top coverage of 80% was achieved in isolated areas.
  • a bottom/top coverage of 85% was achieved in dense areas, and a bottom/top coverage of 95% was achieved in isolated areas.
  • 0% pattern loading effect (PLE) was observed for the top of features, and only 10% PLE was observed was for the sidewall and bottom of features.
  • an oxide layer was deposited to a top thickness of 420 A in a feature having an aspect ratio of 3.5.
  • the thickness of the layer on the sidewall was 275 A, and the thickness on the bottom was 345 A. Thus, the sidewall/top step coverage was 66%, the bottom/top step coverage was 83%, and the sidewall/bottom step coverage was 80%.
  • a low dielectric constant carbon-doped oxide film was deposited to a top thickness of 340 A in a feature having an aspect ratio of 3.5.
  • the thickness of the layer on the sidewall was 125 A, and the thickness on the bottom was 210 A.
  • the sidewall/top step coverage was 35%
  • the bottom/top step coverage was 60%
  • the sidewall/bottom step coverage was 58%.
  • silicon-containing precursors may be used.
  • Other silicon-containing precursors that include a Si-O or Si-N backbone and one or more alkyl groups attached to the silicon atoms may also be used.
  • other plasma treatments may be used to form other films.
  • a silicon-containing precursor may be used to deposit a layer that is nitrogen plasma treated to provide a conformal SiN layer, as described below with respect to Figures 10 and 1 1.
  • Figure 10 is a flow chart of an embodiment of a deposition process 1000.
  • the start step 610, the thickness determination step 650, the repeat step 655, and the end step 660 are described above with respect to Figure 6.
  • a silicon-containing precursor is introduced into the chamber.
  • the silicon-containing precursor can include octamethylcyclotetrasiloxane (OMCTS), methyldiethoxysilane (MDEOS), bis(tertiary-butylamino)silane (BTBAS), tridimethylaminosilane (TriDMAS), trisdimethylaminosilane (TrisDMAS), silane, disilane, dichlorosilane, trichlorosilane, dibromos ⁇ lane, silicon tetrachloride, silicon tetrabromide, or combinations thereof.
  • Silane is a preferred precursor for deposition process 1000.
  • the deposition step 1010 may be performed for about 2 to about 5 seconds.
  • nitrogen is introduced into the chamber to purge the chamber.
  • step 1030 ammonia is used to provide plasma to the chamber.
  • step 1040 another nitrogen purge is performed.
  • the time for one cycle of steps 1010 to 650 is about 60 seconds per cycle and the deposition rate is about 2 A per cycle.
  • the process 1000 provides conformal coverage that is controlled by the purge efficiency, that is, how effectively the purge removes the silicon-containing precursor before the ammonia plasma.
  • FIG 11 is a flow chart of an additional embodiment of a deposition process 1 100.
  • the start step 610, the thickness determination step 650, the repeat step 655, and the end step 660 are described above.
  • a silicon-containing precursor is introduced into the chamber.
  • an optional nitrogen purge step (not shown) may be performed.
  • plasma of a nitrogen-containing precursor is introduced to the chamber.
  • the nitrogen containing precursor may include nitrogen, ammonia, or nitrous oxide. Ammonia is a preferred nitrogen- containing precursor.
  • the time for one cycle of steps 1 1 10 to 650 is about 30 seconds for deposition process 1 100.
  • the deposition rate is about 3.5 A per cycle.
  • the conformal layers provided according to embodiments of the invention may be used as different layers in semiconductor devices. For example, they may be used as layers that are deposited and then subsequently etched to form spacers around a gate stack of a transistor, or they may be used as barrier layers.
  • An advantage of the processes described above is that they result in films with improved step coverage and a reduced pattern loading effect.
  • the process cycles can be performed in the same chamber and thus require less processing time than processes requiring multiple chambers.
  • the overall thermal budget and individual substrate process temperatures are lower than in processes that do not use plasma.

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Abstract

La présente invention concerne des procédés de contrôle de la couverture de niveaux et de chargement de motifs d'une couche sur un substrat. Dans un aspect, un procédé comprend l'exposition du substrat à un précurseur contenant du silicium en présence d'un plasma pour déposer une couche, le traitement de la couche déposée avec un plasma, et la répétition de l'exposition et du traitement jusqu'à l'obtention d'une épaisseur de la couche souhaitée. Le plasma peut être généré à partir d'un gaz contenant de l'oxygène. Dans un autre aspect, un procédé comprend le dépôt d'une couche diélectrique sur un substrat comprenant au moins une élément formé sur toute la surface du substrat et la gravure de la couche diélectrique avec un plasma dérivé d'un gaz contenant de l'oxygène ou de l'halogène pour procurer un profil souhaité de la couche diélectrique sur l'élément. Le dépôt et la gravure peuvent être répétés en plusieurs cycles pour obtenir le profil souhaité.
PCT/US2007/065592 2006-03-31 2007-03-30 Procédé pour améliorer la couverture de niveaux et de chargement de motifs pour films diélectriques WO2007118026A2 (fr)

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US11/668,911 US7601651B2 (en) 2006-03-31 2007-01-30 Method to improve the step coverage and pattern loading for dielectric films
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