Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
  • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
  • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/62—Fin field-effect transistors [FinFET]

Definitions

• the present invention relates generally to semiconductor devices, and more specifically, to method and apparatus for forming a semiconductor-on-insulator (SOI) body- contacted device.
• SOI semiconductor-on-insulator
• Body-contacted SOI transistors are typically built with a polysilicon gate separating the source/drain regions from the body contact region.
• the additional circuit loading capacitance due to this body-tie is substantial.
• body-contacted SOI transistors of greater widths are needed.
• the gate width increases, the resistance along the body of the transistor to the body contact also increases. This resistance may result in portions of the body not being properly tied via the body-contact, as needed for proper operation. Therefore, there is a need for an improved body-contacted SOI transistor.
• FIGs. 1-5, 10-12, and 15 illustrate cross-sectional views of various steps used in forming a body-contacted SOI transistor in accordance with one embodiment of the present invention
• FIGs. 6-9, 13, 14, and 16 illustrate top-down views of various steps used in forming the body-contacted SOI transistor illustrated in the cross-sectional views of FIGs. 1-5, 10-12, and 15, in accordance with one embodiment of the various embodiment; and
• FIG. 17 illustrates a three-dimensional view of a portion of the body-contacted SOI transistor of FIG. 16, in accordance with one embodiment of the various embodiment.
• a body-contacted semiconductor-on-insulator is formed having first and second active regions having different heights. Also, in at least a channel region, the first and second active regions are of different conductivity types. The use of these active regions of different heights and different conductivity types may allow for improved electrical contact to the body of the SOI transistor.
• FIG. 1 illustrates a cross-sectional view of semiconductor structure 10 in accordance with one embodiment of the present invention.
• Semiconductor structure 10 includes a semiconductor substrate 16 and a patterned masking layer 18 formed over semiconductor substrate 16.
• Semiconductor substrate 16 is a semiconductor-on-insulator (SOI) substrate including a semiconductor layer 14 overlying an insulating layer 12.
• SOI semiconductor-on-insulator
• Semiconductor layer 14 may include any type of semiconductor material such as, for example, silicon, silicon- germanium, gallium-arsenide, gallium-nitride, or combinations thereof.
• semiconductor layer 14 includes silicon, in which case substrate 16 may specifically be referred to as a silicon-on-insulator substrate. In the illustrated embodiment, formation of an n-type device will be described.
• semiconductor layer 14 is lightly doped with p-type dopants, such as, for example, boron or BF 2 , as indicated by the label "P-" in FIG. 1.
• p-type dopants such as, for example, boron or BF 2 , as indicated by the label "P-" in FIG. 1.
• this is achieved by performing a p-type implant using a dopant dosage in a range of approximately Iel5 to Iel8/cm 3 . Afterwards, an anneal can be performed to more evenly distribute the dopant.
• semiconductor structure 10 may also be referred to as semiconductor device 10 since eventually, it will become a device in subsequent figures.
• Insulating layer 12 may include any type of insulating materials.
• insulating layer 12 includes an oxide and may be referred to as a buried oxide.
• patterned masking layer 18 is a hardmask layer, and may be formed using known semiconductor processing techniques. Patterned masking layer 18, as will be seen further below, is used to define active areas of different heights.
• FIG. 2 illustrates semiconductor structure 10 after portions of semiconductor layer 14, exposed by patterned masking layer 18, are removed.
• an anisotropic etch may be used to remove portions of semiconductor layer 14, where the etch extends into semiconductor layer 14 but does not extend completely through semiconductor layer 14. Therefore, the etch of FIG. 2 results in semiconductor layer 14 having higher portions 28 and lower portions 30.
• FIG. 3 illustrates performing an implant 20 into semiconductor layer 14.
• implant 20 is a p-type implant using, for example, boron or BF 2 as the dopant with a dopant concentration in a range of approximately IeI 8 to le20/cm 3 .
• FIG. 4 illustrates semiconductor structure 10 after formation of isolation regions 22 to isolate semiconductor layer 14 from other surrounding devices and after removal of patterned masking layer 18.
• Known patterning and etching techniques may be used to form isolation regions 22.
• isolation region 22 surrounds semiconductor layer 14, where semiconductor layer 14 provides the active area (i.e. active region) for the SOI device being formed.
• Patterned masking layer 18 may also be removed using conventional processing techniques.
• FIG. 5 illustrates semiconductor structure 10 after formation of a gate dielectric 24 over semiconductor layer 14 and a gate 26 over gate dielectric layer 24.
• a gate dielectric layer and a gate electrode layer are blanket deposited over substrate 16 and are then patterned to form gate dielectric 24 and gate 26 (where gate 26 may also be referred to as a gate electrode).
• gate 26 and gate dielectric 24 together may be referred to as a gate structure.
• gate 26 is a polysilicon gate, however, in alternate embodiments, other materials or different combinations of materials may be used for gate 26.
• gate dielectric 24 includes an insulator such as oxide or nitride. In alternate embodiments, other materials or different combinations of materials may be used for gate dielectric 24.
• Semiconductor layer 14 which provides the active area for the device (and may therefore also be referred to as the active area or active region), includes a channel region 27 formed along gate dielectric 24 in higher portions 28 which are lightly doped (e.g. P-). Also, semiconductor layer 14 includes a body region 29 located in inner portions of higher portions 28, outside channel region 27. The lower portions 30 under gate 26 (e.g. the P+ portions) provide body ties or contacts between the different portions of body region 29 located in each higher portion 28. Therefore, note that higher portions 28 may be referred to as a first active region, and lower portions 30 may be referred to as a second active region, where the first and second active regions have different heights and different conductivity types (e.g. P- vs.
• Channel region 27 and body region 29 are illustrated in FIG. 5 with dotted lines and indicate the general location of these regions since the boundaries of these regions are not clearly defined.
• the body region usually refers to the region of the active area located below the channel region, where the channel region is a region below the gate where the channel forms during operation of the device.
• FIG. 6 illustrates a top-down view of semiconductor structure 10, where FIG. 5 corresponds to a cross-sectional view taken through a middle of gate 26, as illustrated in FIG. 6.
• semiconductor layer 14 extends out from under both sides of gate 26, forming active region 36.
• the upper portion of active region 36, above gate 26 as illustrated in FIG. 6, corresponds to a drain region 38
• the lower portion of active region 36, below gate 26 as illustrated in FIG. 6, corresponds to a source region 40.
• lower portions 30 extend out further from gate 26 than higher portions 28. Therefore, patterned masking layer 18, described above, is formed such that lower portions 30 extend further than higher portions 28, where the illustrated portions of patterned masking layer 18 above in FIG.
• FIG. 6 also illustrates a contact region 34 of gate 26 where a gate contact may be formed.
• FIG. 7 illustrates a top-down view of semiconductor structure 10 after formation of a patterned masking layer 44 which covers source region 40.
• Patterned masking layer 44 may be formed using known semiconductor processing techniques. As illustrated in FIG. 8, patterned masking layer 44 is used to protect source region 40 while removing lower portions 30 from drain region 38. For example, in one embodiment, an anisotropic etch may be performed to expose underlying insulating layer 12 between and around higher portions 28 in drain region 38, not covered by gate 26.
• FIG. 9 illustrates semiconductor structure 10 after removal of patterned masking layer
• Gate spacer 46 may be formed by blanket depositing one or more insulating layers, and then performing an anisotropic etch to result in gate spacer 46 surrounding gate 26.
• gate 26 is thicker than semiconductor layer 14 such that an overetch may be performed in forming gate spacer 46. This overetch confines gate spacer 46 to the sidewalls of gate 26 while removing the spacer material from any of the sidewalls of semiconductor layer 14 (e.g. of higher and lower portions 28 and 30). In this manner, gate spacer 46 only surrounds gate 26, as illustrated in FIG. 9.
• the formation of gate spacer 46 may be performed such that spacers are also formed on the sidewalls of semiconductor layer 14 (such as on the sidewalls of higher and lower portions 28 and 30).
• FIG. 10 illustrates a cross-sectional view of semiconductor structure 10 taken through drain region 38, as illustrated by the cross-section indicator in FIG. 9. Therefore, note that insulator layer 12 is exposed between higher portions 28, as was described above in reference to FIG. 8.
• FIG. 11 illustrates a cross-sectional view of semiconductor structure 10 taken through source region 40, as illustrated by another cross-section indicator in FIG. 9. Therefore, note that in source region 40, both higher portions 28 and lower portions 30 remain.
• FIG. 12 illustrates performing a source/drain implant 48 into semiconductor layer 14.
• Source/drain implant 48 is performed into both source region 40 and drain region 38 of semiconductor structure 10.
• source/drain implant 48 is performed using an n-type dopant such as, for example, phosphorous or arsenic.
• a dopant concentration in a range of approximately Iel9 to Ie21/cm 3 is used.
• FIG. 13 illustrates a top-down view of semiconductor structure 10 after source/drain implant 48 of FIG. 12. Therefore, note that semiconductor layer 14 not covered by gate 26 in source region 40 and drain region 38 receive n-type dopants, such that higher portions 28 exposed by gate 26 in source region 40 and drain region 38 are heavily doped with n-type dopants (as indicated by the N+). Lower portions 30 in source region 40 also include n-type dopants but may also still include the p-type dopants (as indicated by the N+ in addition to the P+). That is, the n-type dopants of source/drain implant 48 may not fully counter the high concentration of p-type dopants in lower portions 30.
• higher portions 28 underlying gate 26 have a different conductivity type from lower portions 30 of source region 40 (not underlying gate 26). In the illustrated embodiment, they have opposite conductivity types (e.g. P- and P+N+, respectively, where the N+ of lower portions 30 of source region 40 is of opposite conductivity type to the P- in higher portions 28 underlying gate 26). Also, note that in at least channel region 27, under gate 26, lower portions 30 and higher portions 28 have different conductivity types (remaining P- and P+, respectively).
• FIG. 14 illustrates semiconductor structure 10 after suiciding semiconductor layer 14 to form a suicide region 50 (which may also be referred to as a suicide layer). Suiciding may be performed to improve contact efficiency and reduce resistance.
• FIG. 15 illustrates a cross- sectional view of semiconductor structure 10 after suiciding taken through source region 40, as indicated by the cross-section indicator of FIG. 14. Note that in the illustrated embodiment, suiciding is performed such that suicide region 50 extends completely through lower portions 30 of semiconductor layer 14, reaching insulating layer 12. That is, the suiciding completely consumes semiconductor layer 14 in these lower portions. Note that suicide region connects higher portions 28 and lower portions 30 in source region 40, thus connecting the body of structure 10 and source of structure 10 to form a body-tied structure or device. Therefore, the existence of lower portions 30 allows for the ability to easily connect the body and source of structure 10 through silicidation.
• FIG. 16 illustrates a top-down view of semiconductor structure 10 after formation of contacts 51-57 to contact the source, drain, gate, and body of semiconductor structure 10.
• Contacts 51-53 may be formed to overlap a portion of higher portions 28 in drain region 38 (which forms the drain or drain structure of structure 10) or may be formed completely over a drain portion (such as contact 53).
• Contacts 54-56 to source region 40 (which forms the source or source structure of structure 10) provides body contacts along gate 26.
• Each of contacts 51-57 may include any conductive or metal-containing material.
• gate 26 e.g. contacts 54-56 which tie (i.e. electrically connect) the source and body of structure 10 (i.e. device 10).
• tie i.e. electrically connect
• This may provide for an improved body tie having lower resistance and capacitance, rather than the body tie having to extend all along a length of the gate from a body contact located further to the left or right of gate 26, such as beyond gate contact region 34, as would typically be done today.
• the junction formed between higher portions 28 under gate 26 and higher portions 28 in source region 40 due to the different conductivity types (P- vs. N+ in the current embodiment) provides isolation between source region 40 and body region 29.
• FIG. 17 illustrates a three-dimensional view of a portion of semiconductor structure 10 as taken through one of higher portions 28 (indicated by a cross-section indicator in FIG. 5 16). Note that one side of the illustrated active region includes two levels of active region, each at different heights, with the lower one extending further out than the higher one. The lower one provides a contact region for the body of the device while the higher one provides a contact region for the source of the device. As described above, due to the silicidation and conductivity types of lower portions 30 and higher portions 28, a body-tied device is formed
• L 5 an n-type device

Landscapes

• Thin Film Transistor (AREA)
• Electrodes Of Semiconductors (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (2)

Family

ID=38333175

Family Applications (1)

Country Status (5)

Families Citing this family (9)

Family Cites Families (22)

• 2006
  • 2006-02-08 US US11/349,875 patent/US7446001B2/en active Active
• 2007
  • 2007-01-08 TW TW096100710A patent/TWI414023B/zh active
  • 2007-01-22 WO PCT/US2007/060843 patent/WO2007098305A2/en not_active Ceased
  • 2007-01-22 JP JP2008554454A patent/JP5535486B2/ja active Active
  • 2007-01-22 CN CN2007800050278A patent/CN101379614B/zh active Active

Also Published As

Similar Documents

Legal Events