WO2007055071A1 - Procédé de production d'un dispositif mémoire semi-conducteur non volatil comprenant des éléments résistifs variables - Google Patents

Procédé de production d'un dispositif mémoire semi-conducteur non volatil comprenant des éléments résistifs variables Download PDF

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Publication number
WO2007055071A1
WO2007055071A1 PCT/JP2006/319131 JP2006319131W WO2007055071A1 WO 2007055071 A1 WO2007055071 A1 WO 2007055071A1 JP 2006319131 W JP2006319131 W JP 2006319131W WO 2007055071 A1 WO2007055071 A1 WO 2007055071A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory device
semiconductor memory
manufacturing
nonvolatile semiconductor
film
Prior art date
Application number
PCT/JP2006/319131
Other languages
English (en)
Japanese (ja)
Inventor
Shinobu Yamazaki
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2007055071A1 publication Critical patent/WO2007055071A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

Definitions

  • the present invention relates to a method for manufacturing a nonvolatile semiconductor memory device in which a variable resistor for storing data is formed between an upper electrode and a lower electrode.
  • a transistor circuit or the like is formed.
  • the surface is flattened by a so-called CMP method (Chemical Mechanical Polishing Method).
  • Patent Document 2 Japanese Patent Laid-Open No. 2003-68984
  • the sputtering uses any one of Ar, He, Ne, Kr, and Xe as a sputtering gas. Three features.
  • a nonvolatile semiconductor memory device manufacturing method having any one of the above characteristics is characterized in that the sputtering film forming temperature range force is 500 ° C to 800 ° C.
  • the fifth characteristic is that it is an acid oxide of the system.
  • FIG. 6 is a process cross-sectional view showing each process of a manufacturing method of a semiconductor memory device according to the prior art.
  • FIG. 4 shows a resistance value distribution of the nonvolatile semiconductor memory device formed by the method of the present invention and the conventional technique, and a chip of the resistance value of the nonvolatile semiconductor memory device formed by the method of the present invention and the conventional technique.
  • Figure 5 shows the variation.
  • the distribution of the resistance value spreads over one digit, but in the case of the present invention, the distribution is narrowed and the variation is greatly improved. Therefore, it can be said that the variation in the distribution of resistance values was improved under the sputtering conditions according to the method of the present invention.
  • the variation in the chip is also reduced to about 1/10 in the case of the method of the present invention compared to the prior art, and the resistance value is obtained by using the sputtering conditions in an oxygen-free atmosphere by the method of the present invention. It can be said that there was a significant reduction in variability.
  • the variation in resistance value is greatly reduced because the crystallinity of the PCMO film is very high. This is because the crystallization temperature is lowered because sputtering is performed only with Ar gas without oxygen, which is an oxygen-containing gas, during sputtering. Similarly, TiO and NiO are crystallized by sputtering only with Ar gas. Since the crystallization temperature is lowered, the degree of crystallinity is high, and a film can be formed, so that variation in resistance value can be reduced. Also for TiO and NiO, the sputtering gas contains rare metals other than Ar.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne un procédé de production d’un dispositif mémoire semi-conducteur non volatil qui permet de supprimer une variation de la valeur de résistance dérivée de la différence de degré de cristallisation de PCMO dans les résistances variables et permet d’assurer une marge de fonctionnement de circuit satisfaisante. Le procédé de production est un procédé de production d’un dispositif mémoire semi-conducteur comprenant une résistance variable pour enregistrer des données entre une électrode supérieure et une électrode inférieure et comprend une étape de formation d’une résistance variable consistant à pulvériser un oxyde métallique électriquement conducteur dans une atmosphère dépourvue d’oxygène pour constituer la résistance variable.
PCT/JP2006/319131 2005-11-11 2006-09-27 Procédé de production d'un dispositif mémoire semi-conducteur non volatil comprenant des éléments résistifs variables WO2007055071A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005-327982 2005-11-11
JP2005327982A JP4238248B2 (ja) 2005-11-11 2005-11-11 可変抵抗素子を備えた不揮発性半導体記憶装置の製造方法

Publications (1)

Publication Number Publication Date
WO2007055071A1 true WO2007055071A1 (fr) 2007-05-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2006/319131 WO2007055071A1 (fr) 2005-11-11 2006-09-27 Procédé de production d'un dispositif mémoire semi-conducteur non volatil comprenant des éléments résistifs variables

Country Status (3)

Country Link
JP (1) JP4238248B2 (fr)
TW (1) TW200735329A (fr)
WO (1) WO2007055071A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013207130A (ja) * 2012-03-29 2013-10-07 Ulvac Japan Ltd 抵抗変化素子及びその製造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5264139B2 (ja) * 2007-10-09 2013-08-14 スパンション エルエルシー 半導体装置の製造方法
JP5175525B2 (ja) 2007-11-14 2013-04-03 株式会社東芝 不揮発性半導体記憶装置
WO2010103609A1 (fr) 2009-03-09 2010-09-16 株式会社 東芝 Dispositif d'enregistrement/reproduction d'informations
US9269903B2 (en) 2011-06-08 2016-02-23 Ulvac, Inc. Method of manufacturing variable resistance element and apparatus for manufacturing the same
TWI612698B (zh) * 2013-10-09 2018-01-21 財團法人工業技術研究院 多位元儲存之非揮發性記憶體晶胞及非揮發性記憶體
EP4153797A4 (fr) * 2020-05-20 2024-07-17 Hrl Lab Llc Procédé de croissance de films optiques cristallins sur des substrats de si qui peuvent éventuellement présenter une perte optique extrêmement faible dans le spectre infrarouge avec hydrogénation des films optiques cristallins
CN112736198B (zh) * 2020-12-31 2023-06-02 上海集成电路装备材料产业创新中心有限公司 一种阻变存储器及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004234707A (ja) * 2002-12-04 2004-08-19 Sharp Corp 半導体記憶装置及びメモリセルの書き込み並びに消去方法
JP2005123361A (ja) * 2003-10-16 2005-05-12 Sony Corp 抵抗変化型不揮発性メモリおよびその製造方法ならびに抵抗変化層の形成方法
JP2005203463A (ja) * 2004-01-14 2005-07-28 Sharp Corp 不揮発性半導体記憶装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004234707A (ja) * 2002-12-04 2004-08-19 Sharp Corp 半導体記憶装置及びメモリセルの書き込み並びに消去方法
JP2005123361A (ja) * 2003-10-16 2005-05-12 Sony Corp 抵抗変化型不揮発性メモリおよびその製造方法ならびに抵抗変化層の形成方法
JP2005203463A (ja) * 2004-01-14 2005-07-28 Sharp Corp 不揮発性半導体記憶装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013207130A (ja) * 2012-03-29 2013-10-07 Ulvac Japan Ltd 抵抗変化素子及びその製造方法

Also Published As

Publication number Publication date
JP4238248B2 (ja) 2009-03-18
JP2007134603A (ja) 2007-05-31
TW200735329A (en) 2007-09-16

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