WO2007055071A1 - Process for producing nonvolatile semiconductor memory device comprising variable resistive element - Google Patents

Abstract

This invention provides a process for producing a nonvolatile semiconductor memory device that can suppress a variation in resistance value derived from the difference in degree of crystallization of PCMO in variable resistors and can satisfactorily ensure a circuit operation margin. The production process is a process for producing a semiconductor memory device comprising a variable resistor for storing data between upper and lower electrodes and comprises a variable resistor formation step of sputtering an electrically conductive metal oxide in an oxygen-free atmosphere to form the variable resistor.

Description

 Specification

 Manufacturing method of nonvolatile semiconductor memory device provided with variable resistance element

 Technical field

 The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device in which a variable resistor for storing data is formed between an upper electrode and a lower electrode.

 Background art

[0002] In recent years, next-generation non-volatile random access memory (NVRAM) that can operate at high speed instead of flash memory is used as FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), OUM (Ovonic Unified Mem). various device structures such as _ory ) have been proposed, and intense development competition is taking place from the viewpoint of high performance, high reliability, low cost, and process consistency. However, these current memory devices have their merits and demerits, and it is still far from the ideal realization of “universal memory” that combines the advantages of SRAM, DRAM, and flash memory.

 [0003] In contrast to these existing technologies, Shangquing Liu and Alex Ignatiev of the University of Houston in the United States have applied a voltage pulse to a perovskite material known for its giant magnetoresistance effect to reversibly change its electrical resistance. (For example, refer to Patent Document 1 and Non-Patent Document 1). This is an epoch-making thing, with the use of a perovskite material known for its giant magnetoresistive effect, but with resistance changes of several orders of magnitude even at room temperature without the application of a magnetic field.

[0004] Resistive non-volatile memory RRAM (registered trademark of Resistance Co., Ltd., Resistance Random Access Memory) using a variable resistance element that utilizes this phenomenon does not require any magnetic field unlike MRAM, and consumes very little power. Low miniaturization and high integration are easy, and the dynamic range of resistance change is much wider than that of MRAM. Therefore, it has excellent characteristics that multi-value storage is possible. The basic structure of an actual device is extremely simple, with a lower electrode material, a perovskite oxide, and an upper electrode material stacked in that order in the vertical direction of the substrate. In the element structure exemplified in Patent Document 1, the lower electrode material is deposited on a single crystal substrate of lanthanum aluminum oxide LaAlO (LAO). Yttrium barium copper oxide YBa Cu O (YBCO) film, perovskite type oxide is crystalline prasedium calcium manganese oxide Pr Ca MnO (PCMO) film, upper electrode material is deposited by sputtering Each is formed with an Ag film. It has been reported that the operation of this memory element can reversibly change the resistance by applying a positive and negative voltage pulse between the upper and lower electrodes of 51 volts. It means that a novel nonvolatile memory device is possible by reading the resistance value in this reversible resistance change operation (hereinafter referred to as “switching operation” as appropriate).

 [0005] A semiconductor memory device having a cross-point structure has been proposed as a semiconductor memory device having a device structure using such a variable resistance element (see, for example, Patent Document 2).

 [0006] Generally, a semiconductor memory device such as a DRAM, NOR flash memory, or FeRAM has an element portion that stores memory and a selection transistor for selecting the memory element. It is configured. On the other hand, a memory cell having a cross-point structure is formed by eliminating this selection transistor and arranging only a storage material body for storing memory data at the intersection (cross point) between a bit line and a word line. In this memory cell configuration of the cross-point structure, the accumulated data at the intersection of the selected bit line and word line is directly read without using the selected transistor, so the selected bit line connected to the selected memory cell or the selected memory cell is selected. Although the parasitic current flowing through the unselected memory cell connected to the word line is superimposed on the read current flowing through the selected memory cell, there are problems such as a delay in operation speed and an increase in current consumption. Therefore, it has been attracting attention as being capable of large capacity by reducing the memory cell area. The simplest method for manufacturing a crosspoint structure will be described below.

FIG. 1 is a plan layout diagram of a memory cell having a cross-point structure. A region R1 that defines the wiring pattern of the lower electrode wiring B and a region R2 that defines the wiring pattern of the upper electrode wiring T are shown. Here, one of the upper electrode wiring T and the lower electrode wiring B is a word line, and the other is a bit line. 6 and 7 show the conventional manufacturing method in the order of steps. The vertical cross-sectional view along the Χ-ΧΊ of Fig. 1 and the vertical cross-sectional view along the Υ-ΥΊ of Fig. 1 are respectively shown. Show me. First, as shown in FIG. 6A, after forming an interlayer insulating film 12 under the memory cell on a silicon semiconductor substrate 11 on which a transistor circuit or the like (not shown) is formed, a transistor circuit or the like is formed. In order to alleviate the level difference caused by the presence of the surface, the surface is flattened by a so-called CMP method (Chemical Mechanical Polishing Method).

 Subsequently, as shown in FIG. 6 (b), after depositing an electrode material film 13 to be the lower electrode wiring B over the entire surface, the pattern was formed in stripes (lines & spaces) by a photolithography technique. The lower electrode wiring B is formed by etching the electrode material film 13 using the resist R1 as a mask.

 [0010] Subsequently, after removing the resist R1, as shown in FIG. 6 (c), an insulating film 14 having a film thickness sufficient to fill the region between the adjacent lower electrode wirings B is deposited on the entire surface.

 Subsequently, as shown in FIG. 6D, the insulating film 14 is polished to the surface level of the lower electrode wiring B by the CMP method. As a result, the space between the lower electrode wirings B is filled with the insulating film 14. Since the surface of the buried insulating film 14 and the surface of the lower electrode wiring B have substantially the same height, a structure in which the entire surface is substantially smooth is formed. The purpose of the polishing step is to form a variable resistor film to be subsequently formed on the flat surface as much as possible. This is because in the subsequent etching of the variable resistor film, there is no etching selection ratio between the variable resistor film and the lower electrode film, so the variable resistor film is formed on the step of the lower electrode. Due to difficulties.

 Subsequently, as shown in FIG. 7 (a), a metal oxide film 15 to be a variable resistor is formed on the entire surface by sputtering. This sputtering is performed in an atmosphere containing oxygen. Subsequently, as shown in FIG. 7B, an electrode material film 16 to be the upper electrode wiring T is formed on the entire surface.

 [0013] Subsequently, the upper electrode wiring T is formed by etching the electrode material film 16 using the resist R2 patterned in a stripe shape (line & space) by a photolithography technique as a mask. Further, as shown in FIG. 7C, the variable resistor film 15 remaining between the upper electrode wirings T is removed by etching.

Subsequently, after removing the resist R2, as shown in FIG. 7D, an interlayer insulating film 17 under the metal wiring is deposited on the entire surface. After that, contacts to the lower electrode wiring B, the upper electrode wiring T, transistor circuits other than the memory cells, etc. (contact forming portions are not shown) are formed, and metal Perform wiring (not shown).

 [0015] PCMO film formation (see Fig. 7 (a)), which is a variable resistor of the cross-point device described above, is formed by sputtering using a sintered PCMO target. An appropriate amount of oxygen gas is mixed with Ar gas, which is a sputtering gas, and introduced for the purpose of supplementing the missing oxygen. It is known that the PCMO film thus formed is almost amorphous. Amorphous PCMO films usually have extremely high resistance, so they are not suitable for device operation, and it is necessary to crystallize them during the heat treatment step in the process to lower the resistance level to a desired level.

 [0016] Patent Document 1: US Pat. No. 6,204,139

 Patent Document 2: Japanese Patent Laid-Open No. 2003-68984

 Special Reference 1: Liu, Q. Ma Electric- pulse- induced reversible Resis tance change effect m magnetoresistive films, Applied Physics Let ter, Vol. 76, pp. 2749-2751, 2000

 Disclosure of the invention

 Problems to be solved by the invention

 [0017] However, the PCMO film crystallized and reduced in resistance in this way is strongly influenced by the state of the underlying electrode surface or insulating film surface. As a result, the PCMO film, which is a variable resistor, has a different crystallinity of the PCMO film, resulting in a very large variation in the resistance value of each variable resistor. For this reason, the margin necessary for circuit operation has been reduced! Instability and failure rate have been increased!

 [0018] The present invention has been made in view of the above problems, and an object of the present invention is to suppress variation in resistance value due to a difference in PCMO crystallinity of the variable resistor and to ensure a sufficient circuit operation margin. Another object is to provide a method for manufacturing a nonvolatile semiconductor memory device.

 Means for solving the problem

In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a variable resistance element in which a variable resistor for storing data is formed between an upper electrode and a lower electrode. A method of manufacturing a nonvolatile semiconductor memory device comprising: a variable resistance body formed by sputtering a metal oxide in an atmosphere not containing oxygen. The first feature is to execute the resistor forming step.

 In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a plurality of upper electrode wires extending in the same direction and extending in a direction perpendicular to the extending direction of the upper electrode wires. A cross-point structure comprising a plurality of lower electrode wirings and variable resistance elements formed by forming variable resistors for storing data between the upper electrode wirings and the lower electrode wirings in a matrix shape. A method of manufacturing a nonvolatile semiconductor memory device including a memory cell array, wherein a variable resistor is formed by sputtering a metal oxide on the plurality of lower electrode wirings in an oxygen-free atmosphere. The second feature is to execute the resistor forming process.

 [0021] In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention having any one of the above features, the sputtering uses any one of Ar, He, Ne, Kr, and Xe as a sputtering gas. Three features.

 [0022] A nonvolatile semiconductor memory device manufacturing method according to the present invention having any one of the above characteristics is characterized in that the sputtering film forming temperature range force is 500 ° C to 800 ° C.

 [0023] In any one of the above features of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the metal oxide may be represented by the general formula Pr Ca [Mn M] 0 (where 0≤x≤1, 0≤z <1)

 1 -X X 1 -Z Z 3

 The fifth characteristic is that it is an acid oxide of the system.

[0024] In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention having the above characteristics, M in the general formula is any one of Ta, Ti, Cu, Cr, Co, Fe, Ni, and Ga. Inclusion is the sixth feature.

 [0025] In the method for manufacturing a nonvolatile semiconductor memory device according to the first to fourth features of the present invention, the metal oxide is a Ti oxide or a Ni oxide. The seventh feature. The invention's effect

 [0026] According to the method for manufacturing a nonvolatile semiconductor memory device having the above characteristics, it is possible to reduce the variation in resistance value of the variable resistance element. As a result, when a nonvolatile semiconductor memory device including the variable resistance element is configured, the circuit operation margin is increased, stable memory operation is possible, and the defect rate can be further reduced. Become.

Brief Description of Drawings [0027] [FIG. 1] a planar layout of a memory cell array having a cross-point structure

 FIG. 2 is a process cross-sectional view showing each process in the first embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

 FIG. 3 is a process sectional view showing each process in the first embodiment of the method for manufacturing a semiconductor memory device according to the invention.

 [4] Graph showing resistance distribution of the semiconductor memory device according to the present invention and the semiconductor memory device according to the prior art

 FIG. 5 is a graph showing variations in resistance values of the semiconductor memory device according to the present invention and the semiconductor memory device according to the prior art.

 FIG. 6 is a process cross-sectional view showing each process of a manufacturing method of a semiconductor memory device according to the prior art.

[0028] 11: Semiconductor substrate (silicon substrate)

 12: Interlayer insulation film (BPSG film)

 13: Pt film

 14: Silicon oxide film

 15: Variable resistor

 16: Pt film

 17: Interlayer insulation film

 18: Variable resistor

 B: Lower electrode wiring

 T: Upper electrode wiring

 R1: resist

 R2: Resist

 BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention (hereinafter abbreviated as “the method of the present invention” as appropriate) will be described with reference to the drawings.

FIG. 1 is a plan layout view for forming a memory cell array in the method of the present invention. There are a region Rl for defining the wiring pattern of the lower electrode wiring B and a region R2 for defining the wiring pattern of the upper electrode wiring T, respectively. The plan layout diagram is the same as the plan layout diagram of a memory cell array having a conventional cross-point structure. In addition, variable resistance elements formed by forming variable resistors for storing data are arranged in a matrix. In the following embodiments, a CMR material (for example, PCMO: Pr Ca MnO) thin film having a giant magnetic resistance effect is used as a variable resistor of a memory cell to cross

 0. 7 0. 3 3

 A specific manufacturing method of the memory cell array configuration will be described by taking, as an example, a point structure memory cell and an RRAM that constitutes the memory cell array.

 <First Embodiment>

 An embodiment of the method of the present invention will be described with reference to FIGS. Here, FIG. 2 and FIG. 3 show each step of the method of the present invention in this embodiment in order. 2 and 3 show a vertical cross-sectional view along the X-axis in FIG. 1 and a vertical cross-sectional view along the X-axis in FIG. 1, respectively. In the present invention, “vertical” means a case perpendicular to the surface of the semiconductor substrate 11 unless otherwise specified.

 First, as in the conventional manufacturing method, a BPSG film 12 having a thickness of 1300 nm is formed as an interlayer insulating film under a memory cell on a silicon semiconductor substrate 11 on which a transistor circuit or the like (not shown) is formed. Then, the surface is polished to 600 nm by CMP to flatten the surface. Subsequently, as shown in FIG. 2A, a Pt film 13 (corresponding to the first electrode film) to be the lower electrode wiring B is sputtered over the entire surface. In this embodiment, the Pt film 13 is deposited so that the film thickness becomes 200 nm.

 Subsequently, as shown in FIG. 2B, the Pt film 13 is etched by using the resist R1 patterned in stripes (line & space) by a photolithography technique as a mask. Electrode wiring B is formed. In this embodiment, etching was performed using a striped resist pattern having a line width of 0.3 m and a space width of 0.3 / zm.

Subsequently, after removing the resist R1, as shown in FIG. 2 (c), a silicon oxide film 14 as an insulating film is deposited on the entire surface. The film thickness of the silicon oxide film 14 should be sufficient to fill the space between the lower electrode wirings B. In this embodiment, the silicon oxide film 14 is deposited so that the film thickness force becomes 00 nm. Subsequently, a polishing process is performed in which the silicon oxide film 14 is polished to the surface level of the lower electrode wiring B by the CMP method. The above is the lower electrode wiring formation process for forming the lower electrode wiring B.

 As a result of the polishing process, as shown in FIG. 2 (d), the space between the lower electrode wirings B is buried with the silicon oxide film 14, and the surface of the embedded silicon oxide film 14 and the lower electrode wiring B By smoothing the surface to approximately the same height, a planar structure having a substantially uniform surface is formed.

 [0037] Subsequently, as shown in FIG. 3 (e), a variable resistance made of PCMO (Pr Ca MnO) is used.

 0. 7 0. 3 3

 The antibody 18 is deposited on the surface of the lower electrode wiring B and the silicon oxide film 14 so as to have a film thickness of lOOnm. The sputtering conditions are, for example, an Ar gas flow rate of 210 sccm, a pressure of 2 OmTorr, and a substrate temperature of 670 ° C. The only gas introduced into the reaction chamber is Ar, and the PCMO film formed in an oxygen-free atmosphere becomes a crystallized film. In addition, as the variable resistor 18, an oxide such as TiO or NiO can also be formed by sputtering the TiO target or NiO target.

twenty two

 It is possible to use a TiO film or NiO film formed under the same conditions. PC

 2

 The MO film 18 is composed of Pr Ca [Mn M] 0 (where 0≤x≤ 1, 0≤z <1). L -X X 1 -Z Z 3

 It is an oxide. M preferably contains one of Ta, Ti, Cu, Cr, Co, Fe, Ni, and Ga.

 Subsequently, as shown in FIG. 3 (f), a Pt film 16 to be the upper electrode T is formed on the PCMO film 18 by a sputtering method. In this embodiment, the thickness of the Pt film 16 is lOOnm.

 Thereafter, a resist R2 as shown in FIG. 3 (g) is formed on the Pt film 16 in a region to be the upper electrode T by a photolithography technique based on the upper electrode pattern. Then, using this resist R2 as a mask, the Pt film 16 and the PCMO film 18 are simultaneously etched by a dry etching method, and then the resist is removed to form the upper electrode T (Pt film 16) and the variable as shown in FIG. A resistor (PCMO film 18) is formed.

 [0040] After that, as shown in FIG. 3 (h), an SiO film 17 is deposited to a thickness of 400 nm by the CVD method.

 2

 Then, contact holes and metal wiring steps necessary for circuit operation are performed to complete the circuit (not shown).

[0041] The sputtering conditions for the PCMO film 18 described above are not limited to this, and stable sputtering is performed. A rare gas element other than Ar, such as He, Ne, Kr, or Xe, may be used for the gas. The substrate temperature is preferably in the range of 500 ° C to 800 ° C where the PCMO film crystallizes stably.

 FIG. 4 shows a resistance value distribution of the nonvolatile semiconductor memory device formed by the method of the present invention and the conventional technique, and a chip of the resistance value of the nonvolatile semiconductor memory device formed by the method of the present invention and the conventional technique. Figure 5 shows the variation.

 FIG. 4 shows the resistance distribution of the PCMO film formed on the semiconductor substrate by the method of the present invention and the prior art. Note that the sputtering deposition temperature is 670 ° C in all cases. As shown in FIG. 4, under the sputtering conditions using Ar gas of the above embodiment, the resistance value distribution was measured. As a result, the resistance value was 20 to 60 μΩ, and an appropriate resistance value as a variable resistor was obtained. In addition, under the sputtering conditions in an oxygen atmosphere according to the prior art, 1 to 10 Ω was obtained as a result of measuring the distribution of resistance values. That is, in the case of the conventional method, the distribution of the resistance value spreads over one digit, but in the case of the present invention, the distribution is narrowed and the variation is greatly improved. Therefore, it can be said that the variation in the distribution of resistance values was improved under the sputtering conditions according to the method of the present invention.

 [0044] Subsequently, FIG. 5 shows the variation in the resistance value of the PCMO film formed by the method of the present invention and the prior art in the wafer. Here, the variation within the wafer is shown by using the standard deviation 3 σ of the resistance value within the wafer and the average value of the resistance value, and the average value of 3 σ Ζ resistance value as the variation. As shown in FIG. 5, when the resistance value distribution is compared between the sputtering conditions using Ar gas according to the method of the present invention and the sputtering conditions in a conventional oxygen atmosphere, the variation in the chip in the case of the method of the present invention is 8 Compared to about 40%, the conventional method is about 40 to 200%. That is, the variation in the chip is also reduced to about 1/10 in the case of the method of the present invention compared to the prior art, and the resistance value is obtained by using the sputtering conditions in an oxygen-free atmosphere by the method of the present invention. It can be said that there was a significant reduction in variability.

[0045] As described above, the variation in resistance value is greatly reduced because the crystallinity of the PCMO film is very high. This is because the crystallization temperature is lowered because sputtering is performed only with Ar gas without oxygen, which is an oxygen-containing gas, during sputtering. Similarly, TiO and NiO are crystallized by sputtering only with Ar gas. Since the crystallization temperature is lowered, the degree of crystallinity is high, and a film can be formed, so that variation in resistance value can be reduced. Also for TiO and NiO, the sputtering gas contains rare metals other than Ar.

 2

Gas elements such as He, Ne, Kr, and Xe may be used. Therefore, according to the method of the present invention, it is possible to realize a good non-volatile semiconductor memory device that can sufficiently secure an operation margin as a result of extremely small variations.

Claims

The scope of the claims

 [1] A method of manufacturing a nonvolatile semiconductor memory device including a variable resistance element formed by forming a variable resistor for storing data between an upper electrode and a lower electrode,

 A method of manufacturing a nonvolatile semiconductor memory device, comprising performing a variable resistor forming step of sputtering a metal oxide in an oxygen-free atmosphere to form the variable resistor.

 [2] A plurality of upper electrode wirings extending in the same direction and a plurality of lower electrode wirings extending in a direction perpendicular to the extending direction of the upper electrode wirings are provided, and data is provided between the upper electrode wirings and the lower electrode wirings. A method of manufacturing a nonvolatile semiconductor memory device including a memory cell array having a cross-point structure in which variable resistance elements formed by forming variable resistors for storing the charge are arranged in a matrix,

 A non-volatile semiconductor memory device characterized by performing a variable resistor forming step of sputtering a metal oxide on the plurality of lower electrode wirings in an oxygen-free atmosphere to form the variable resistor. Manufacturing method.

 [3] The method for manufacturing a nonvolatile semiconductor memory device according to [1], wherein the sputtering uses any one of Ar, He, Ne, Kr, and Xe as a sputtering gas.

 [4] The method for manufacturing a nonvolatile semiconductor memory device according to any one of claims 1 to 3, wherein a film forming temperature range of the sputtering is 500 ° C to 800 ° C.

 [5] The metal oxide has a general formula Pr Ca [Mn M] 0 (where 0≤x≤ 1, 0≤z <1)

 l -X X 1 -Z Z 3

 4. The method for manufacturing a non-volatile semiconductor memory device according to claim 1, wherein the oxide is a compound represented by the formula:

6. The nonvolatile semiconductor memory device according to claim 5, wherein M in the general formula includes any one of Ta, Ti, Cu, Cr, Co, Fe, Ni, and Ga. Manufacturing method.

7. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the metal oxide is a Ti oxide or a Ni oxide. Method.