CN101159309A - Method for implementing low power consumption resistance memory - Google Patents
Method for implementing low power consumption resistance memory Download PDFInfo
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- CN101159309A CN101159309A CNA2007100479730A CN200710047973A CN101159309A CN 101159309 A CN101159309 A CN 101159309A CN A2007100479730 A CNA2007100479730 A CN A2007100479730A CN 200710047973 A CN200710047973 A CN 200710047973A CN 101159309 A CN101159309 A CN 101159309A
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Abstract
The invention pertains to the field of microelectronic technology, in particular to a method of realizing a low-power resistance memory. Specifically, a layer of binary metal oxide or a binary metal nitride medium film is inserted between a metal oxide resistance memory film and a conducting electrode, thereby reducing the current of restoration operation or reading operation of the resistance memory, and reducing the power consumption of the resistance memory. The inserted metal oxide medium layer has the advantages of easy fabrication and strong process compatibility.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of implementation method of low power consumption resistance memory.
Background technology
Memory is seized of consequence in semi-conductor market.Because constantly popularizing of portable electric appts, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But owing to crosstalk (CROSS TALK) and tunnel layer can not with technology generation develop unrestricted attenuate, with the bottleneck problem of FLASH such as embedded system is integrated development, force people to seek the more superior novel non-volatilization memory of performance.Recently, resistance random access memory (Resistive RandomAccess Memory, abbreviate RRAM as) because its high density, low cost, have very strong causing with characteristics such as technology generation developing abilities to show great attention to, employed material has the SrZrO of phase-change material, doping
3, ferroelectric material PbZrTiO
3, ferromagnetic material Pr
1-xCa
xMnO
3, the binary metal oxide material
[1], organic material etc.The some of them binary metal oxide is (as the oxide of copper
[2], tungsten oxide, titanyl compound, the oxide of nickel, the oxide of aluminium etc.) because accurately control at component, and ic process compatibility and cost aspect potential advantages especially paid close attention to.
Fig. 1 is the characteristic schematic diagram of the I-V of resistive memory cell
[2], curve 101 has represented that primary state is the IV curve of high resistant, the voltage scanning direction increases to V when voltage since 0 to forward as shown by arrows gradually
T1The time, electric current can increase rapidly suddenly, shows that memory resistor is mutated into low resistive state from high resistant, and curve 100 has represented that primary state is the state of low-resistance, gradually increases to V by 0 to negative sense when voltage
T2The time, electric current reaches maximum, and this after-current can reduce rapidly suddenly, shows that memory resistor is mutated into high-impedance state from low-resistance.Under signal of telecommunication effect, but device can be between high resistant and low-resistance inverse conversion, thereby reach the effect of signal storage.Usually claim from what high resistant was converted to low-resistance to be operating as set (set) operation, be converted to operating of high resistant for reset (reset) from low-resistance.
Fig. 2 is traditional resistive memory cell structure chart of having reported
[2]Wherein 21 is metal bottom electrodes, the 23rd, and the resistive memory film, the 25th, electrode of metal, the three forms memory cell 10 jointly, can see, and it has adopted the sandwich structure of metal electrode-resistive memory film one metal electrode (MIM).
Fig. 3 is a kind of I-V performance diagram of Al/CuxO/Cu structural resistance memory, as can be seen from the figure when voltage from 0V when negative voltage scans, memory change to be realized the RESET operation from low resistance state to high-impedance state, the RESET operating current reaches about 0.01A.Because its low resistance state resistance value very low (about tens ohm), the electric current read of store status also will reach the mA order of magnitude at this moment.Therefore, according to power consumption formula P=I
2Rt, the reset operation electric current means big power consumption greatly, this just becomes one of bottleneck of resistive memory technical development.There is the result of literature research to show
[3], the reset operation process is relevant with the Joule heat that electric current flows through generation, is the mechanism that a kind of heat is wiped, when the Joule heat that produces is high, and can be favourable to the reset operation process.Find a kind of method that reduces Memister reset operation electric current to have very big practical application meaning.
Fig. 4 a is another RRAM structure of Sumsang electronics, inc. patent application
[4], the difference of it and traditional MIM sandwich structure is: increased one deck current control layer between two electrodes.Shown in Fig. 4 a, the 21st, metal bottom electrode, the 23rd, resistive memory film, the 25th, electrode of metal, the 26th, current control layer.Wherein current control layer 26 is a kind of oxides, and it can be the ZnOx of the oxide of transition metal element doped ZnOx and RuOx, transition metal, doped with Al and In and RuOx, metal-doped SiO2 and ZrO2.Fig. 4 b is the resistance schematic diagram of structure shown in Fig. 4 a, R
TE, R
R, R
NiO, R
BEShow 25,26,20 and 21 resistance respectively, the resistance range of current control layer 26 at about 10 Ω to 10k Ω.Resistance R by current control layer 26
R, the low resistance state resistance of RRAM unit is raise, thereby can reduce the current value of low resistance state, according to power consumption formula P=I
2Rt, electric current I obviously reduces, and resistance R partly increases, and the power consumption P that reads or writes of global storage unit can be reduced.
But in the manufacture process of actual resistance memory, the realization of the current control layer of structural resistance memory shown in Fig. 4 a is to form by methods such as CVD or sputters, the metal oxide forming process relative complex of the oxide of transition metal and multi-element doping, particularly metal-doped oxide, its film composition proportional control is difficult in the custom integrated circuit manufacture method, uniformity is difficult to guarantee simultaneously, and this will influence the manufacturing cost and the even reliability of Memister.Transition metal is a kind of new element with respect to the front end and the last part technology of CMOS integrated circuit simultaneously, and equipment is had certain contaminative, therefore must careful consideration in the manufacture process kind.
Summary of the invention
The object of the present invention is to provide the implementation method of the low power consumption resistance memory of simple, the even good reliability of a kind of technology.
The implementation method of low power consumption resistance memory provided by the invention specifically realizes that by the reset operation of reduction Memister or the current methods of read operation the power consumption of Memister reduces.Implementation method is that the resistivity of its dielectric film is more than 10 Europe cm by inserting one deck binary metal oxide or binary metal nitride dielectric film between metal oxide resistor memory films and the conductive electrode or between double layer of metal oxide resistor memory films.The dielectric film that is inserted reduces the reset operation electric current and the read current of memory as the series electrical resistance layer; Perhaps the resistive memory film is heated, make the resistive memory layer be more prone to realize reset operation by the heat that produces by institute's dielectric film that inserts, thus reduction reset operation electric current.
Described binary metal oxide dielectric film can be aluminium oxide (Al
2O
3), tantalum oxide (Ta
2O
5), cupric oxide (CuO), hafnium oxide (HfO
2) or tungsten oxide (WO
3) wait material.
Described binary metal nitride dielectric film can be copper nitride (Cu
3Material such as N).
Described metal oxide resistor memory films can be Cu
xO (1＜x≤2), perhaps WO
x(1≤x≤3), perhaps NiO
x(0.66＜x≤1), perhaps TiO
2
The manufacturing of described dielectric film has the advantages that to be easy to the integrated circuit fabrication process compatibility, and cost is low, and thickness and composition are easy to control; When wherein cupric oxide (CuO) dielectric film is formed on the CuxO storage medium layer, can also come cupric oxide by controlled oxidation technology, autoregistration forms cupric oxide.
Description of drawings
The I-V characteristic curve of Fig. 1 Memister.
Fig. 2 is the MIM Memister structure chart of report at present.
The I-V characteristic curve of Fig. 3 CuxO Memister.
The Memister cross-sectional view of Fig. 4 a Samsung report.
Fig. 4 b is the resistance schematic diagram of structure shown in Fig. 4 a.
Fig. 5 is a low power consumption resistance memory embodiment cross-sectional view.
Fig. 6 is to the method schematic diagram of Figure 10 for formation Fig. 5 structure illustrated embodiment.
Number in the figure: the 100th, initial state is a low-resistance voltage scanning curve, and 101 are respectively the voltage scanning curve that initial state is a high resistant, and 10 is resistive memory cell, 11 is resistive memory cell, and 110 is resistive memory cell, 21 expression bottom electrodes, 23 expression resistive memory layers, 26 expression current control layers, 25 expression top electrodes, 200 expression substrates, 201 bottom electrodes, 203 expression resistive memory layers, 204 expression insulating medium layers, 205 expression top electrodes, dielectric layer is inserted in 206 expressions, 601 expression grooves.
Embodiment
Describe the present invention in the reference example more completely in conjunction with being shown in hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, for the clear thickness that has amplified layer and zone, but should not be considered to the proportionate relationship that strictness has reflected physical dimension as schematic diagram.
At this reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
Fig. 5 is the part of the profile of Memister embodiment according to the present invention.
With reference to figure 5,110 is resistive memory cell, and resistive memory cell 110 can form on integrated circuit substrate 200, and substrate 200 can use silicon dioxide, doped silica, and silicon nitride or other material form.Resistive memory cell 110 comprises bottom electrode 201, storage medium layer 203, inserts dielectric layer 206 and top electrode 205.The copper bottom electrode that bottom electrode 201 can be to use the standard Damascus technics to form; Or the W bottom electrode that forms with the method for chemical vapour deposition (CVD); Or other metal or semimetal, it is including but not limited to titanium, platinum, titanium nitride (TiN) or TiAlN (TiAlN), electrode is metal and semimetallic composite bed also, can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or the formation of electrochemical deposition methods such as (ECP).Storage medium layer 203 is formed on the bottom electrode 201, externally between high-impedance state and low resistance state, come under the action of electric signals and can change, it plays storage characteristics, it can be CuxO (1＜x≤a 2) resistive memory film, perhaps WOx (1≤x≤3) resistive memory film, perhaps NiO (0.66＜x≤1) resistive memory film, perhaps TiO
2The resistive memory film can be made the accumulation layer film with the method for thermal oxidation or chemical reaction sputter or physical vapor deposition or chemical vapor deposition or atomic layer deposition (ALD) etc.Top electrode 205 can be metal or conductive metallic compound, and it can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or electrochemical deposition methods such as (ECP) to form.Insert dielectric layer 206 between top electrode 205 and storage medium layer 203, it also can be between bottom electrode 201 and storage medium layer 203, and its position is not limited by present embodiment figure; Inserting dielectric layer 206 can be aluminium oxide (Al
2O
3), tantalum oxide (Ta
2O
5), cupric oxide (CuO), hafnium oxide (HfO
2), tungsten oxide (WO3) etc. is the binary metal oxide dielectric material, also can be copper nitride (Cu
3N) etc. binary metal nitride dielectric thin-film material is inserted the resistivity of dielectric layer 206 resistivity greater than resistive memory layer 203 low resistive state, and its resistivity is more than 10 Ω cm.When storage medium layer 203 is low resistance state, insert dielectric layer resistance 206 and be higher than storage medium layer 203, electric current flows through high-resistance insertion dielectric layer 206, the heat that produces is to 203 heating of resistive memory layer, thereby the transformation when helping reset operation from the low-resistance to the high resistant, in other words, just can produce the required heat of reset operation with less current; Simultaneously, insert dielectric layer 206 and can be used as the series electrical resistance layer, increase the low resistance state resistance of storage device, thereby reduce the read operation electric current of memory; Therefore insert reset operation electric current and the read operation electric current that dielectric layer 206 can reduce resistive memory cell on the whole, the effect of landing low memory power consumption.Because the dielectric layer that inserts 206 is aluminium oxide (Al
2O
3), tantalum oxide (Ta
2O
5), cupric oxide (CuO), hafnium oxide (HfO
2), tungsten oxide (WO3) etc. is the binary metal oxide dielectric material, these materials can form by film growth ways such as ALD, the thickness easy control of components of film can be finished under the ripe integrated circuit technology condition; Also can the way by the oxidized metal form the binary metal oxide medium, for example the method for thermal oxidation and plasma oxidation copper or tungsten forms cupric oxide and tungsten oxide respectively, this method also with the integrated circuit fabrication process compatibility; Thereby can on the implementation method that reduces the power consumption resistive memory, can realize low low-cost on the whole.
Next, will be showing that in conjunction with Fig. 5 embodiment basic structure describes the implementation method method that forms the low power consumption resistance memory unit more completely based on the resistance random access memory of CuxO, Fig. 6 illustrates the profile of method of the resistance random device cell of formation present embodiment to Figure 10.
With reference to figure 6, substrate 200 can be monocrystalline silicon, can be copper wire layer in the copper-connection also, utilizes chemical vapor deposition (CVD) technology to form SiO on substrate 200
2 Dielectric layer 204.
Further enforcement of the present invention with reference to figure 7, utilizes photoetching process to form window, utilizes as etching technics again and removes 204 part formation groove 601 at window place dry etching, and wet method is removed photoresist then.
Further enforcement of the present invention, with reference to figure 8, the method in Damascus in the employing copper-connection forms the Ta/TaN barrier layer earlier, forms inculating crystal layer, electro-coppering, annealing, and then CMP removes unnecessary copper, bottom electrode 201 formation.
Further enforcement of the present invention with reference to figure 9, forms CuxO resistive memory film 203 with the way of plasma oxidation or thermal oxidation on bottom electrode 201.
Further enforcement of the present invention is with reference to figure 10a, at CuxO resistive memory film 203 and SiO
2Atomic layer deposition 2nmAl on the dielectric layer 204
2O
3 Dielectric layer 206.
In another embodiment, with reference to figure 10b, 350 degree annealing are 5 minutes in oxygen atmosphere, Cu
xThe 203 upper surface layer autoregistrations of O resistive memory film become the CuO dielectric layer 206 about 10nm.
Further enforcement of the present invention is with reference to figure 3a, at Al
2O
3Sputter Al forms top electrode 205 on the dielectric layer 206.
In another embodiment, with reference to figure 3b, at CuO dielectric layer 206 and SiO
2Sputter Al forms top electrode 205 on the dielectric layer 204.
So far, resistance memory cell of the present invention forms, and this Memister has less read operation and reset operation electric current, and is low in energy consumption, and implementation procedure is simple relatively simultaneously, and processing compatibility is strong.
List of references
[1]I.G.Baek，M.S.Lee，S.Seo，M.J.Lee，D.H.Seo，.S.Suh，J.C.Park，S.O.Park，H.S.Kim，I.K.Yoo，U-InChung，and?J.T.Moon，“Highly?scalable?non-volatile?resistive?memory?using?simple?binary?oxide?drivenby?asymmetric?unipolar?voltage?pulses”，IEDMTech.Dig.p.587(2004).
[2]A.Chen，S.Haddad，Y.-C.Wu，“on-Volatile?Resistive?Switching?for?Advanced?Memory?Applications”IEDM?Tech?Dig.，p.746，2005
[3]Tzu-Ning?Fang，Swaroop?Kaza，Sameer?Haddad，etal.“Erase?Mechanism?for?Copper?Oxide?ResistiveSwitching”.IEDM?Tech?Dig.，2006
[4]Myoung?Lee，Yongin-si?Yoon-dong?Park，Hyun-sang?Hwang，Dong-soo?Lee，“Resistance?Random?access?memoryDevice?and?a?Method?of?Manufacturing?the?Same”.United?States?Patent?Application，Application?serialnumber：11/654003.
Claims (2)
1. the implementation method of a low power consumption resistance memory is characterized in that: inserting one deck binary metal oxide or binary metal nitride dielectric film between metal oxide resistor memory films and the conductive electrode or between double layer of metal oxide resistor memory films; Described dielectric film is aluminium oxide, tantalum oxide, cupric oxide, copper nitride, hafnium oxide, tungsten oxide or nitrogen cupric oxide; Its resistivity is more than 10 Europe cm; Described metal oxide resistor memory films is Cu
xO, 1＜x≤2, perhaps WO
x, 1≤x≤3, perhaps NiO
x, 0.66＜x≤1, perhaps TiO
2
2. according to the method described in the claim 1, it is characterized in that described cupric oxide dielectric film is formed at Cu
xIn the time of on the O storage medium layer, form cupric oxide by the autoregistration of control technology.
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Cited By (13)
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| CN101577307B (en) * | 2008-05-05 | 2011-11-30 | 中芯国际集成电路制造(北京)有限公司 | Storage unit of resistance storage and manufacture method thereof |
| CN102299258A (en) * | 2010-06-28 | 2011-12-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of memory cell of resistive memory |
| CN102332454A (en) * | 2010-07-15 | 2012-01-25 | 复旦大学 | One-time programmable memory cell, memory and preparation method thereof |
| CN101958397B (en) * | 2009-07-16 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of resistor storage |
| CN102034927B (en) * | 2009-09-25 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Impedance memorizer and manufacture method thereof |
| CN101738419B (en) * | 2008-11-21 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting variable resistance material |
| CN103178207A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Memristor |
| CN103280405A (en) * | 2013-05-28 | 2013-09-04 | 清华大学 | Method of forming stacking structure of ultrathin mixed oxide layer |
| CN101752002B (en) * | 2008-12-11 | 2013-09-18 | 旺宏电子股份有限公司 | Aluminum copper oxide based memory devices and methods for manufacture |
| CN103378103A (en) * | 2012-04-24 | 2013-10-30 | 华邦电子股份有限公司 | Nonvolatile memory and manufacturing method thereof |
| CN107452875A (en) * | 2016-05-30 | 2017-12-08 | 旺宏电子股份有限公司 | Resistive memory element and manufacturing method and application thereof |
| WO2018214142A1 (en) * | 2017-05-26 | 2018-11-29 | 中国科学院微电子研究所 | Resistive memory device, and manufacturing method thereof |
| CN112420923A (en) * | 2020-11-26 | 2021-02-26 | 上海华力微电子有限公司 | Resistive random access memory and manufacturing method thereof |
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2007
- 2007-11-08 CN CNA2007100479730A patent/CN101159309A/en active Pending
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| CN101577307B (en) * | 2008-05-05 | 2011-11-30 | 中芯国际集成电路制造(北京)有限公司 | Storage unit of resistance storage and manufacture method thereof |
| CN101738419B (en) * | 2008-11-21 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting variable resistance material |
| CN101752002B (en) * | 2008-12-11 | 2013-09-18 | 旺宏电子股份有限公司 | Aluminum copper oxide based memory devices and methods for manufacture |
| CN101958397B (en) * | 2009-07-16 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of resistor storage |
| CN102034927B (en) * | 2009-09-25 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Impedance memorizer and manufacture method thereof |
| CN102299258A (en) * | 2010-06-28 | 2011-12-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of memory cell of resistive memory |
| CN102299258B (en) * | 2010-06-28 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of memory cell of resistive memory |
| CN102332454A (en) * | 2010-07-15 | 2012-01-25 | 复旦大学 | One-time programmable memory cell, memory and preparation method thereof |
| CN102332454B (en) * | 2010-07-15 | 2013-04-10 | 复旦大学 | One-time programmable memory cell, memory and preparation method thereof |
| CN103178207B (en) * | 2011-12-21 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Memristor |
| CN103178207A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Memristor |
| CN103378103A (en) * | 2012-04-24 | 2013-10-30 | 华邦电子股份有限公司 | Nonvolatile memory and manufacturing method thereof |
| CN103378103B (en) * | 2012-04-24 | 2016-08-03 | 华邦电子股份有限公司 | Non-volatility memorizer and manufacture method thereof |
| CN103280405A (en) * | 2013-05-28 | 2013-09-04 | 清华大学 | Method of forming stacking structure of ultrathin mixed oxide layer |
| CN107452875A (en) * | 2016-05-30 | 2017-12-08 | 旺宏电子股份有限公司 | Resistive memory element and manufacturing method and application thereof |
| WO2018214142A1 (en) * | 2017-05-26 | 2018-11-29 | 中国科学院微电子研究所 | Resistive memory device, and manufacturing method thereof |
| US11245074B2 (en) | 2017-05-26 | 2022-02-08 | Institute of Microelectronics, Chinese Academy of Sciences | Resistance random access memory and method for fabricating the same |
| CN112420923A (en) * | 2020-11-26 | 2021-02-26 | 上海华力微电子有限公司 | Resistive random access memory and manufacturing method thereof |
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