CN101101960A - A resistance memory for reducing reset operation current - Google Patents

A resistance memory for reducing reset operation current Download PDF

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Publication number
CN101101960A
CN101101960A CNA2007100437070A CN200710043707A CN101101960A CN 101101960 A CN101101960 A CN 101101960A CN A2007100437070 A CNA2007100437070 A CN A2007100437070A CN 200710043707 A CN200710043707 A CN 200710043707A CN 101101960 A CN101101960 A CN 101101960A
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film
resistance
memory
oxide
reset operation
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CNA2007100437070A
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林殷茵
陈邦明
尹明
唐立
吕杭炳
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Fudan University
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Fudan University
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Abstract

The invention is concerned with the resistance storage that can reduce reset operating current, it is: the resistance storage is between the metal oxide resistance storage film and the electrode, or inserts the medium film between the two storage medium, the resistivity of the medium film is over 10 ohm .cm that can reduce the reset operating current by heat creating from the inserting medium film to heat the film.

Description

A kind of Memister of reducing reset operation current
Technical field
The invention belongs to microelectronics technology, be specifically related to Memister and its implementation of a kind of reducing reset operation current.
Background technology
Memory occupies an important position in semi-conductor market.Because constantly popularizing of portable electric appts, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But owing to crosstalk (CROSS TALK) and tunnel layer can not with technology generation develop unrestricted attenuate, with the bottleneck problem of FLASH such as embedded system is integrated development, force people to seek the more superior novel non-volatilization memory of performance.Recently resistance random access memory (Resistive RandomAccess Memory abbreviates RRAM as) is because its high density, low cost, have very strong causing with characteristics such as technology generation developing abilities to show great attention to, and employed material has phase-change material [1], the SrZrO that mixes 3 [2], ferroelectric material PbZrTiO 3 [3], ferromagnetic material Pr 1-xCa xMnO 3 [4], the binary metal oxide material [5], organic material [6]Deng.The some of them binary metal oxide is (as the oxide of copper [7], tungsten oxide, titanyl compound, the oxide of nickel, the oxide of aluminium etc.) because accurately control at component, and ic process compatibility and cost aspect potential advantages especially paid close attention to.
Fig. 1 is the characteristic schematic diagram of the I-V of resistive memory cell [7], curve 101 has represented that primary state is the IV curve of high resistant, the voltage scanning direction increases to V when voltage since 0 to forward as shown by arrows gradually T1The time, electric current can increase rapidly suddenly, shows that memory resistor is mutated into low resistive state from high resistant, and curve 100 has represented that primary state is the state of low-resistance, gradually increases to V by 0 to negative sense when voltage T2The time, electric current reaches maximum, and this after-current can reduce rapidly suddenly, shows that memory resistor is mutated into high-impedance state from low-resistance.Under signal of telecommunication effect, but device can be between high resistant and low-resistance inverse conversion, thereby reach the effect of signal storage.Usually claim from what high resistant was converted to low-resistance to be operating as set (set) operation, be converted to operating of high resistant for reset (reset) from low-resistance.
Fig. 2 be reported based on (a) CuO x [7](b) TiO 2 [11]The resistive memory cell structure chart.Wherein 200 is substrates, the 201st, and metal bottom electrode, the 203rd, resistive memory film, the 204th, insulating dielectric layer, the 205th, electrode of metal.Can see, all be the sandwich structure that adopts metal electrode one resistive memory film one metal electrode.Though the resistive memory film that the present Memister of reporting is used and the material of metal electrode have nothing in common with each other, major part all is to adopt this sandwich structure.
Bibliographical information is also arranged at Ni xAdd layer of conductive material IrO between O resistive memory film and Pt electrode 2 [10], reach improvement in repeatedly set (set) resets (reset) operation, the effect of stable operation voltage, inhibition drift.
According to the data of present report, the magnitude of (reset) electric current that on the device of doing under the 0.18um technology, resets (promptly changing to the electric current of high-impedance state) about about 10uA from low resistance state.There is the result of literature research to show [12], the reset operation process is relevant with the Joule heat that electric current flows through generation, is the mechanism that a kind of heat is wiped, when the Joule heat that produces is high, and can be favourable to the reset operation process.The reset operation electric current means big power consumption greatly, can propose special requirement to peripheral circuit simultaneously, and for example corresponding crystal Guan Yaoneng bears needed big electric current etc.So finding a kind of method that reduces Memister reset operation electric current is its actual application value.
Summary of the invention
The object of the present invention is to provide a kind of Memister of reducing reset operation current.
Memister provided by the invention, its basic structure is identical with common Memister, just between metal oxide resistor memory films and conductive electrode, perhaps between two-layer resistive memory film, be inserted with one deck dielectric film, this layer dielectric film can be between top electrode and resistive memory film, perhaps between bottom electrode and resistive memory film, perhaps be inserted between the two-layer resistive memory film.
The resistance of the dielectric film layer that is inserted is greater than resistive memory film low resistance state, and its resistivity is more than 10 Europe cm, and the heat that produces by the insertion dielectric film is to the heating of resistive memory film, thereby reduces the reset operation electric current.
Described metal oxide resistor memory films can be Cu xO (1＜x≤2) resistive memory, perhaps WO x(1≤x≤3) resistive memory film, or NiO x(0.66＜x≤1) resistive memory film, or TiO 2The resistive memory film.
The resistance of the dielectric film of described insertion is higher than resistive memory film low resistive state resistance, and this medium can be aluminium oxide (Al 2O 3), tantalum oxide (Ta 2O 5), cupric oxide (CuO), copper nitride (Cu 3N), nitrogen cupric oxide (CuON).
Description of drawings
The I-V characteristic curve of Fig. 1 Memister.
Fig. 2 a is the Cu of report at present xO resistance memory structure.
Fig. 2 b is the TiO of report at present 2The resistance memory structure.
Fig. 3 a is for inserting an embodiment cross-sectional view of the Memister of dielectric layer between bottom electrode and memory films.
Fig. 3 b is for inserting the another embodiment cross-sectional view of the Memister of dielectric layer between bottom electrode and memory films.
Fig. 4 is for inserting the Memister cross-sectional view of dielectric layer between top electrode and memory films.
Fig. 5 is for inserting the Memister cross-sectional view of dielectric layer between two-layer memory films.
Fig. 6 is to the method schematic diagram of Figure 10 for formation Fig. 3 structure illustrated embodiment.
Number in the figure: the 100th, initial state is a low-resistance voltage scanning curve, 101 are respectively the voltage scanning curve that initial state is a high resistant, 200 expression substrates, 201 bottom electrodes, 203 expression metal oxide resistor memory films, 203a represents the resistive memory film, 203b represents the resistive memory film, 204 expression insulating medium layers, 205 expression top electrodes, the dielectric layer that 206 expressions are inserted, 601 expression grooves.
Embodiment
Describe the present invention in the reference example more completely in conjunction with being shown in hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, for the clear thickness that has amplified layer and zone, but should not be considered to the proportionate relationship that strictness has reflected physical dimension as schematic diagram.
At this reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
With reference to figure 3 are parts of the profile of one embodiment of the present of invention, and the dielectric film that it inserted is between bottom electrode and metallic oxide storage medium, and the difference of Fig. 3 a, Fig. 3 b is the shape difference of the dielectric layer that inserted.Memister can form on integrated circuit substrate 200, and substrate 200 can use silicon dioxide, doped silica, and silicon nitride or other material form.This Memister bottom electrode 201 forms in the dielectric aperture, the copper bottom electrode that bottom electrode can be to use the standard Damascus technics to form; Or the W bottom electrode that forms with the method for chemical vapour deposition (CVD); Or other metal or semimetal, it is including but not limited to titanium, platinum, titanium nitride (TiN) or TiAlN (TiAlN), electrode is metal and semimetallic composite bed also, can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or the formation of electrochemical deposition methods such as (ECP).
Resistive memory film 203 forms on bottom electrode 201, can be CuxO (1＜x≤2) resistive memory film or WOx (1≤x≤3) resistive memory film, perhaps NiO (0.66＜x≤1) resistive memory film, perhaps TiO 2The resistive memory film can be made of the method for thermal oxidation or chemical reaction sputter or physical vapor deposition or chemical vapor deposition or atomic layer deposition (ALD) etc.
Dielectric film 206 is inserted between resistive memory film 203 and the top electrode 205.Dielectric film 206 can be aluminium oxide (Al 2O 3), tantalum oxide (Ta 2O 5), cupric oxide (CuO), copper nitride (Cu 3N), nitrogen cupric oxide (CuON), electric current flow through the dielectric film of high resistivity, and the heat of generation is to the heating of resistive memory film, the transformation when helping reset operation from the low-resistance to the high resistant.In other words, just can produce the required heat of reset operation with less current.Dielectric film 206 resistivity are greater than the resistivity of resistive memory film low resistive state, its resistivity is more than 10 Europe cm, for making the low resistance state resistance that guarantees memory cell be lower than the resistance of 70% high-impedance state memory cell at least, the resistance range that inserts dielectric film is: R On＜R＜2.33R Off(R OnMemory films is a low resistance state resistance, R OffMemory films is a high-resistance resistors).Can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or atomic layer deposition methods such as (ALD) to make.Some dielectric film layers can also use the method for direct oxidation or nitrogenize to form.
Top electrode 205, can metal or semimetal, it is including but not limited to copper, titanium, platinum, titanium nitride (TiN) or TiAlN (TiAlN), electrode is metal and semimetallic composite bed also, can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or the formation of electrochemical deposition methods such as (ECP).
Should be noted that: the size of Memister can be by the top electrode size, or the bottom electrode size, or the resistive memory film dimensions limits.As: in the embodiment shown in Fig. 3 (comprising Fig. 4, Fig. 5 subsequently), the size of Memister is limited by the bottom electrode size; The structure shown in Figure 2 limit that has access to electricity is fixed.Scope of the present invention is not limited to these concrete structures.
With reference to figure 4 are another embodiment of invention, and among this embodiment, bottom electrode 201 forms in the dielectric aperture, and dielectric film 206 is inserted between storage medium film 203 and the bottom electrode 201.In this structure, dielectric film 206 can use the method for physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or atomic layer deposition (ALD) to make, some resistance dielectric layers can also be used the method for using direct oxidation or nitrogenize, as: oxygenerating copper (CuO) resistance dielectric layer on the copper bottom electrode, just can be by the direct heat oxidation of copper bottom electrode or the method for plasma oxidation are obtained.RRAM medium 203 forms on resistance dielectric layer 206, can use the method for chemical reaction sputter, physical vapor deposition, chemical vapor deposition or atomic layer deposition (ALD) etc. to make.That introduces among upper/lower electrode material and manufacture method and the last embodiment is identical.
With reference to figure 5 are another embodiment of invention, and the main distinction embodiment illustrated in fig. 4 is: dielectric film 206 is inserted between two-layer resistive memory film 203a and the 203b.
Next, to describe the method that forms low reset operation current resistor memory cell more completely in conjunction with Fig. 3 example structure with the resistance random access memory based on CuxO, Fig. 6 illustrates the profile of the method for the resistance random device cell that forms present embodiment to Figure 10.
With reference to figure 6, substrate 200 can be monocrystalline silicon, can be copper wire layer in the copper-connection also, utilizes chemical vapor deposition (CVD) technology to form SiO2 dielectric layer 204 on substrate 200.
Further enforcement of the present invention with reference to figure 7, utilizes photoetching process to form window, utilizes as etching technics again and removes 204 part formation groove 601 at window place dry etching, and wet method is removed photoresist then.
Further enforcement of the present invention, with reference to figure 8, the method in Damascus in the employing copper-connection forms the Ta/TaN barrier layer earlier, forms inculating crystal layer, electro-coppering, annealing, and then CMP removes unnecessary copper, bottom electrode 201 formation.
Further enforcement of the present invention with reference to figure 9, forms CuxO resistive memory film 203 with the way of plasma oxidation or thermal oxidation on bottom electrode 201.
Further enforcement of the present invention, with reference to figure 10a, atomic layer deposition 2nmAl on CuxO resistive memory film 203 and SiO2 dielectric layer 204 2O 3 Dielectric layer 206.
In another embodiment, with reference to figure 10b, 350 degree annealing are 5 minutes in oxygen atmosphere, Cu xO resistive memory film 203 upper surface layers are transformed into the CuO dielectric layer 206 about 10nm.
Further enforcement of the present invention is with reference to figure 3a, at Al 2O 3Sputter Al forms top electrode 205 on the dielectric layer 206.
In another embodiment, with reference to figure 3b, sputter Al forms top electrode 205 on CuO dielectric layer 206 and SiO2 dielectric layer 204.
So far, resistance memory cell of the present invention forms, and compares the resistance memory cell of not inserting dielectric layer 206 among this embodiment, and its reset operation electric current reduces by 10 2-10 4Doubly.
List of references
[1]J.Maimon，E.Spall，R.Quinn，S.Schnur，″Chalcogenide-based?nonvolatile?memory?technology″，IEEEProceedings?of?Aerospace?Conference，p.2289，2001.
[2]C.Y.Liu，P.H.Wu，A.Wang，W.Y.Jang，J.C.Young，K.Y.Chiu，and?T.Y?Tseng，“Bistable?resistiveswitching?of?a?sputter-deposited?Cr-doped?SrZrO3?memory?film”，IEEE?EDL?vol.26，p.351，2005.
[3]J.R.Contreras，H.Kohlstedt，U.Pooppe，R.Waser，C.Buchal，and?N.A.Pertsev，“Resistive?switching?inmetal-ferroelectric-metal?junctions”，Appl.Phys.Lett.vol.83，p.4595，2003.
[4]A.Asamitsu，Y.Tomioka，H.Kuwahara，and?Y.Tokura，“Current?switching?of?resistive?states?inmagnetoresistive?manganites”，Nature(London)vol.388，p.50，1997.
[5]I.G.Baek，M.S.Lee，S.Seo，M.J.Lee，D.H.Seo，.S.Suh，J.C.Park，S.O.Park，H.S.Kim，I.K.Yoo，U-InChung，and?J.T.Moon，“Highly?scalable?non-volatile?resistive?memory?using?simple?binary?oxide?drivenby?asymmetric?unipolar?voltage?pulses”，IEDM?Tech.Dig.p.587(2004).
[6]L.P.Ma，J.Liu，and?Y.Yang，“Organic?electrical?bistable?devices?and?rewriteable?memory?cells”，Appl.Phys.Lett.vol.80，p.2997，2002；L.D.Bozano，B.W.Kean，V.R.Deline，J.R.Salem，and?J.C.Scott，“Mechanism?for?bistability?in?organic?memory?elements”，Appl.Phys.Lett.vol.84，p.607，2004.
[7]A.Chen，S.Haddad，Y.-C.Wu，”Non-Volatile?Resistive?Switching?for?Advanced?Memory?Applications”IEDM?Tech?Dig.，p.746，2005
[8]Tzu-Ning?Fang，Swaroop?Kaza，Sameer?Haddad，An?Chen，”Erase?Mechanism?for?Copper?OxideResistive?SwitchingMemory?Cells?with?Nickel?Electrode”IEDM?2006
[9]S.Seo，a_M.J.Lee，D.C.Kim，”Electrode?dependence?of?resistance?switching?in?polycrystalline?NiOfilms”，Appl.Phys.Lett.vol.87，p.263507(2005)
[10]D.C.Kim，a_，b_M.J.Lee，S.E.Ahn，”Improvement?of?resistive?memory?switching?in?NiO?using?IrO2”Appl.Phys.Lett.vol.88，P.232106(2006).
[11]K.Kinoshita，T.Tamura，“New?Model?Proposed?for?Switching?Mechanism?ofReRAM”Non-VolatileSemiconductor?Memory?Workshop?2006?p.84
[12]Tzu-Ning?Fang，Swaroop?Kaza，Sameer?Haddad，etal.Erase?Mechanism?for?Copper?Oxide?ResistiveSwitching.IEDM?Tech?Dig，2006

Claims (3)

  1. The Memister of 1 one kinds of reducing reset operation currents, it is characterized in that: inserting one deck dielectric film between metal oxide resistor memory films and the conductive electrode or between double layer of metal oxide resistor memory films, the resistivity of this dielectric film is more than 10 Europe cm.
  2. 2 Memisters according to claim 1 is characterized in that described metal oxide resistor memory films is Cu xO, 1＜x≤2, perhaps WO x, 1≤x≤3, or NiO x, 0.66＜x≤1, perhaps TiO 2
  3. 3 Memisters according to claim 1 is characterized in that described dielectric film is aluminium oxide, tantalum oxide, cupric oxide, copper nitride, nitrogen cupric oxide.
CNA2007100437070A 2007-07-12 2007-07-12 A resistance memory for reducing reset operation current Pending CN101101960A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101226988B (en) * 2008-01-17 2011-02-16 复旦大学 Method for reducing CuxO resistance memory write operation current
CN102057438A (en) * 2008-06-11 2011-05-11 Nxp股份有限公司 Phase change memory device and control method
CN102347440A (en) * 2010-08-02 2012-02-08 复旦大学 Resistive memory and preparation method thereof
WO2012048521A1 (en) * 2010-10-15 2012-04-19 复旦大学 Nio-based resistive random access memory and method for manufacturing same
WO2017156755A1 (en) * 2016-03-18 2017-09-21 中国科学院微电子研究所 Selection device for use in bipolar resistive memory and manufacturing method therefor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101226988B (en) * 2008-01-17 2011-02-16 复旦大学 Method for reducing CuxO resistance memory write operation current
CN102057438A (en) * 2008-06-11 2011-05-11 Nxp股份有限公司 Phase change memory device and control method
CN102347440A (en) * 2010-08-02 2012-02-08 复旦大学 Resistive memory and preparation method thereof
WO2012048521A1 (en) * 2010-10-15 2012-04-19 复旦大学 Nio-based resistive random access memory and method for manufacturing same
WO2017156755A1 (en) * 2016-03-18 2017-09-21 中国科学院微电子研究所 Selection device for use in bipolar resistive memory and manufacturing method therefor
US10665780B2 (en) 2016-03-18 2020-05-26 Institute of Microelectronics, Chinese Academy of Sciences Selection device for use in bipolar resistive memory and manufacturing method therefor

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