CN103178207B - Memristor - Google Patents
Memristor Download PDFInfo
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- CN103178207B CN103178207B CN201110431432.4A CN201110431432A CN103178207B CN 103178207 B CN103178207 B CN 103178207B CN 201110431432 A CN201110431432 A CN 201110431432A CN 103178207 B CN103178207 B CN 103178207B
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- resistive memory
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Abstract
The invention discloses a memristor. A resistive random access memory medium layer is stacked through tungsten oxides and titanium oxynitride. By means of the memristor, initial resistance and low-impedance resistance of apparatuses can be improved, the maximum operation current and power consumption of apparatuses can be reduced, and broad selection is provided for development of the memristor.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to one and recall resistance memory.
Background technology
Non-volatile line storage (NVM) technology sends out sexual development so far, mainly contains floating boom (floating gate) technology, dividing potential drop grid (split gate) technology and SONOS technology.And recent years, recalling resistance memory (RRAM) is also that resistance-variable random asccess memory becomes the most popular memory technology of industry, it has numerous proud characteristic, it is more likely technology semiconductor industry being produced to revolutionary change, become a kind of general-purpose storage structure, towards all kinds of markets application such as DRAM, NAND, NOR.
As shown in Figure 1, being the existing structural representation recalling resistance memory, as shown in Figure 2, is the existing SEM photo recalling resistance memory.Existingly recall resistance memory and comprise a resistive memory medium layer be made up of tungsten oxide 14, the bottom electrode material 13 be made up of tungsten, the top electrode 12 be made up of metallic aluminium or aluminium copper, and the bottom electrode 11 be made up of metallic aluminium or aluminium copper.Described bottom electrode material 13 is positioned at the below of described resistive memory medium layer 14 and contacts with described resistive memory medium layer 14, and the bottom of described bottom electrode material 13 connects described bottom electrode 11.Described top electrode 12 directly contacts with described resistive memory medium layer 14, also can comprise a top layer electrode material be made up of titanium or titanium nitride between described top electrode 12 and described resistive memory medium layer 14.As seen from Figure 2, the existing thickness recalling the described resistive memory medium layer 14 of resistance memory that Fig. 2 provides is 61nm.
Existingly recall resistance memory and there will be high resistant characteristic when adding higher forward bias voltage in outside, when there will be low resistance characteristic when carrying out negative sense bias voltage to it in the other direction.Described bottom electrode 11 ground connection is forward bias when described top electrode 12 connects high potential; Described bottom electrode 11 connects high potential, is that negative sense is biased during described top electrode 12 ground connection.
The existing characteristic recalling resistance one of memory restriction application in other words weakness is that the resistance of initial resistance and low resistance state resistance is very low, as with size thus stock size is less than 100 ohm to the resistance of the single through hole resistance of 0.2 × 0.2 microns square, maximumly be also difficult to reach kilohm.Existing recall resistance memory low resistance characteristic decision can make to existing recall resistance memory carry out producing larger current in voltage bias process, the operating voltage of usual resistive characteristic needs 2 volts ~ 5 volts, conversion is come, and recalls the electric current of resistance memory generation for number milliampere when resistive is voltage-operated to the existing of single through hole.This electric current can produce two severe effects: one is that requirement circuit design needs very large current driving ability, and produces very large power consumption, greatly the use of limits storage and capacity; Two be requirement connect this existing recall resistance memory cell metal routing need enough electric current accommodation degree, the electric current of number milliampere needs the metal live width of more than corresponding micron order usually, more than this is wider than the wiring width of the memory of other kind order of magnitude, otherwise the ELECTROMIGRATION PHENOMENON of metal wire will be caused, greatly constrain chip area and application.
Summary of the invention
Technical problem to be solved by this invention is to provide one and recalls resistance memory, can improve initial resistance and the low resistance state resistance of device, can reduce maximum operating current and the power consumption of device, for the development recalling resistance memory provides broader selection.
For solving the problems of the technologies described above, provided by the invention recall resistance memory comprise a resistive memory medium layer, this resistive memory medium layer is formed by stacking by tungsten oxide and titanium oxynitrides.
Further improvement is, described recall resistance memory also comprise the bottom electrode material be made up of tungsten, the top layer electrode material be made up of titanium or titanium nitride, the top electrode be made up of metallic aluminium or aluminium copper, and the bottom electrode be made up of metallic aluminium or aluminium copper; Described bottom electrode material is positioned at the below of described resistive memory medium layer and contacts with the described tungsten oxide of described resistive memory medium layer, and the bottom of described bottom electrode material connects described bottom electrode; Described top layer electrode material is positioned at the top of described resistive memory medium layer and contacts with the described titanium oxynitrides of described resistive memory medium layer, and the top of described top layer electrode material connects described top electrode.
Further improvement is, the thickness of described tungsten oxide is 100 dust ~ 1000 dusts; The thickness of described titanium oxynitrides is 50 dust ~ 300 dusts.
The present invention can improve initial resistance and the low resistance state resistance of device, can reduce maximum operating current and the power consumption of device, for the development recalling resistance memory provides broader selection.Principle is: resistive memory medium layer of the present invention is formed by stacking by tungsten oxide and titanium oxynitrides, has more complicated network configuration in the interface of tungsten oxide and titanium oxynitrides, and the interfacial state condition of binary.When the low-resistance tungsten oxide components migrate in resistive material and resistive memory medium layer is to the interface of two kinds of oxidized metals, electronics is easy to move to interfacial state region, and electronics can form the Tunnel Passing effect of secondary at titanium oxynitrides place, Tunnel Passing electric current is very little relative to the electron transfer electric current of metal, therefore, the low resistance state resistance of device of the present invention can raise several order of magnitude.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the existing structural representation recalling resistance memory;
Fig. 2 is the existing SEM photo recalling resistance memory;
Fig. 3 is the structural representation that the embodiment of the present invention recalls resistance memory;
Fig. 4 is the energy band diagram that the embodiment of the present invention recalls resistance memory.
Embodiment
Fig. 3 is the structural representation that the embodiment of the present invention recalls resistance memory; The embodiment of the present invention is recalled resistance memory and is comprised a resistive memory medium layer, and this resistive memory medium layer is formed by stacking by tungsten oxide 142 and titanium oxynitrides 141.The thickness of described tungsten oxide 142 is 100 dust ~ 1000 dusts; The thickness of described titanium oxynitrides 141 is 50 dust ~ 300 dusts.
Also comprise the bottom electrode material 131 be made up of tungsten, the top layer electrode material 122 be made up of titanium or titanium nitride, the top electrode 121 be made up of metallic aluminium or aluminium copper, and the bottom electrode 111 be made up of metallic aluminium or aluminium copper; Described bottom electrode material 131 is positioned at the below of described resistive memory medium layer and contacts with the described tungsten oxide 142 of described resistive memory medium layer, and the bottom of described bottom electrode material 131 connects described bottom electrode 111; Described top layer electrode material 122 is positioned at the top of described resistive memory medium layer and contacts with the described titanium oxynitrides 141 of described resistive memory medium layer, and the top of described top layer electrode material 122 connects described top electrode 121.
As shown in Figure 4, be the energy band diagram that the embodiment of the present invention recalls resistance memory.Can find out to there is the lower interfacial state of an energy level in the interface of tungsten oxide and titanium oxynitrides.When device is in low resistance state, after the embodiment of the present invention recalls resistance memory making current, electronics is easy to first move to interfacial state region, then titanium oxynitrides layer is passed through by tunnelling mode, namely electronics can form the Tunnel Passing effect of secondary at titanium oxynitrides place, Tunnel Passing electric current is very little relative to the electron transfer electric current of metal, and therefore, the low resistance state resistance of embodiment of the present invention device can raise several order of magnitude.For 0.25 micrometre square (namely wide and long be all 0.25 micron) single through hole resistance, the low resistance state of existing device or the resistance value of initial resistance, in 50 ohm (ohm) left and right, are maximumly no more than 100 ohm.And in the embodiment of the present invention, as the titanium oxynitrides lamination of the tungsten oxide material (WOx) and 150 dusts that adopt 500 dusts, the low resistance state resistance of acquisition can reach more than 3000 ohm.Namely resistance value can improve nearly two orders of magnitude, that is to say, the initial power consumption of device can reduce nearly two orders of magnitude.The application development recalling resistance memory that is reduced to of the resistance value of the low resistance state of embodiment of the present invention device provides more wide selection, if make the electric current accommodation degree of the metal routing of device reduce, the live width of metal routing is reduced; The required current driving ability of device can also be made to reduce.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (2)
1. recall a resistance memory, it is characterized in that: recall resistance memory and comprise a resistive memory medium layer, this resistive memory medium layer is formed by stacking by tungsten oxide and titanium oxynitrides;
Describedly recall resistance memory and also comprise the bottom electrode material be made up of tungsten, the top layer electrode material be made up of titanium or titanium nitride, the top electrode be made up of metallic aluminium or aluminium copper, and the bottom electrode be made up of metallic aluminium or aluminium copper; Described bottom electrode material is positioned at the below of described resistive memory medium layer and contacts with the described tungsten oxide of described resistive memory medium layer, and the bottom of described bottom electrode material connects described bottom electrode; Described top layer electrode material is positioned at the top of described resistive memory medium layer and contacts with the described titanium oxynitrides of described resistive memory medium layer, and the top of described top layer electrode material connects described top electrode;
The interface of described tungsten oxide and described titanium oxynitrides is that electronics adopts tunnelling mode by the resistance of described titanium oxynitrides to the resistance between described top layer electrode material, recalls initial resistance and the low resistance state resistance of resistance memory by this resistance described in being increased.
2. recall resistance memory as claimed in claim 1, it is characterized in that: the thickness of described tungsten oxide is 100 dust ~ 1000 dusts; The thickness of described titanium oxynitrides is 50 dust ~ 300 dusts.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110431432.4A CN103178207B (en) | 2011-12-21 | 2011-12-21 | Memristor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110431432.4A CN103178207B (en) | 2011-12-21 | 2011-12-21 | Memristor |
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| CN103178207A CN103178207A (en) | 2013-06-26 |
| CN103178207B true CN103178207B (en) | 2015-06-03 |
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| CN201110431432.4A Active CN103178207B (en) | 2011-12-21 | 2011-12-21 | Memristor |
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| CN106206936B (en) * | 2015-05-06 | 2019-03-08 | 华邦电子股份有限公司 | Resistive random access memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101159309A (en) * | 2007-11-08 | 2008-04-09 | 复旦大学 | Method for implementing low power consumption resistance memory |
| CN101315969A (en) * | 2008-06-26 | 2008-12-03 | 复旦大学 | Resistor memory with doping control layer |
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| KR20110072920A (en) * | 2009-12-23 | 2011-06-29 | 삼성전자주식회사 | Resistive random access memory device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101159309A (en) * | 2007-11-08 | 2008-04-09 | 复旦大学 | Method for implementing low power consumption resistance memory |
| CN101315969A (en) * | 2008-06-26 | 2008-12-03 | 复旦大学 | Resistor memory with doping control layer |
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