CN101315969A - Resistor memory with doping control layer - Google Patents
Resistor memory with doping control layer Download PDFInfo
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- CN101315969A CN101315969A CNA2008100396075A CN200810039607A CN101315969A CN 101315969 A CN101315969 A CN 101315969A CN A2008100396075 A CNA2008100396075 A CN A2008100396075A CN 200810039607 A CN200810039607 A CN 200810039607A CN 101315969 A CN101315969 A CN 101315969A
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Abstract
The invention belongs to the micro-electron technical field, in particular to a resistance memory with a doped control layer. The resistance memory comprises an upper electrode, a lower electrode, a resistance memory medium layer used for realizing the memory conversion of the resistance value, and a doped control layer used for realizing the metal element doping of the resistance memory medium layer and controlling of the doping content. The doped control layer and the resistance memory medium layer are directly connected with each other and the metal element in the upper electrode or the lower electrode penetrates through the doped control layer to diffuse towards the surface of the memory medium layer so as to realize the controllable low doping of the resistance memory medium layer, thus achieving the object of stabilizing the electric performance of the resistance memory.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of Memister with doping control layer.
Background technology
Memory occupies an important position in semi-conductor market.Because constantly popularizing of portable electric appts, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But owing to crosstalk (CROSS TALK) and tunnel layer can not with technology generation develop unrestricted attenuate, with the bottleneck problem of FLASH such as embedded system is integrated development, force people to seek the more superior novel non-volatilization memory of performance.Nearest resistance random access memory (Resistive Random Access Memory, abbreviate RRAM as) because its high density, low cost, have very strong causing with characteristics such as technology generation developing abilities to show great attention to, its material that mainly uses has phase-change material, multivariant oxide (as: SrZrO
3, PbZrTiO
3, Pr
1-xCa
xMnO
3), the binary metal oxide material
[1]
Fig. 1 is conventional resistor accidental memory structure, and wherein 201 is metal bottom electrodes, the 202nd, and resistive memory film, the 203rd, electrode of metal.Though the resistive memory film that the present Memister of reporting is used and the material of metal electrode have nothing in common with each other, substantially all be the sandwich structure that adopts metal electrode-resistive memory film-metal electrode.
Fig. 2 (a) is the I-V characteristic curve of this conventional resistive memory cell.Curve 101 has represented that primary state is the IV curve of high resistant, the voltage scanning direction as shown by arrows, institute's making alive increases to V gradually since 0 to forward between upper/lower electrode
TSThe time, electric current can increase rapidly suddenly, shows that memory resistor is mutated into low resistive state from high resistant.Curve 100 has represented that primary state is the state of low-resistance.Gradually increase to V by 0 to negative sense when voltage
TRThe time, electric current reaches maximum, and this after-current can reduce rapidly suddenly, shows that memory resistor is mutated into high-impedance state from low-resistance.Under signal of telecommunication effect, but device can be between high resistant and low-resistance inverse conversion, thereby reach the effect of signal storage.Usually claim from what high resistant was converted to low-resistance to be operating as set (set) operation, be converted to operating of high resistant for reset (reset) from low-resistance.
Fig. 2 (b) is that this conventional resistive memory cell is done one group of I-V curve of set repeatedly, reset operation under the logarithmic coordinates system.Can see V
TSAnd V
TRBe not a stationary value, it has a bigger fluctuation range.Fig. 2 (c) is that this conventional resistive memory cell is done set repeatedly, the low ancestral and the high resistant distribution situation of correspondence when reset operation is.The maximum high resistant in back that also resets as can be seen among the figure is hundreds of times of minimum high resistant, and the low-resistance after the same set distributes and also disperses very much, also differs tens of times between maximin.The unsteadiness of these above-mentioned electrical parameters can be brought a lot of troubles to application, as: operating voltage is difficult to determine that the operation power consumption is difficult to prediction.
According to present result of study, to the resistor memory media surface mix can the steady resistance random asccess memory electrical parameter, improve this device performance
[1] [2]For example, list of references [1] is thought and is mixed the destruction Ni-O key that a small amount of Ti can be slight among the NiO, strengthens oxonium ion moving in film, and the write operation speed of NiO Memister is significantly improved, the write operation voltage of this device, high and low resistance state resistance are also obviously stable.Current a kind of doping method is to allow doping metals directly contact with storage medium, realizes diffusing, doping
[1] [3], so the difficult control of doping method doping, for the metal oxide resistor memory films that only needs low-mix and inapplicable, for example, Cu
xO resistive memory laminar surface is mixed a small amount of Ta and can be played and put forward the reduction device power consumption, the effect of stabilizing device performance, but Ta and Cu
xThe O film directly contacts to mix and can make Cu
xTa too high levels among the O and cause the devices switch loses in performance.
Summary of the invention
The object of the present invention is to provide a kind of Memister with high electric property.
Memister provided by the invention is a kind of Memister with doping control layer.It realizes controllable doped to the resistor memory media layer in the described Memister by described doping control layer, thereby improves the electric property of Memister.
Memister provided by the present invention comprises:
Lower electrode layer;
The resistor memory media layer;
Directly and the contacted doping control layer of storage medium layer;
And, upper electrode layer.
Described doping control layer can be between described resistor memory media layer and described upper electrode layer, also can be between described resistor memory media layer and described lower electrode layer.
Wherein, described doping control layer is used for realizing the doped with metal elements to described resistor memory media layer, and doping content control, and it can be metal nitride, metal oxide or metal oxynitride film; This selects assorted key-course can be the single thin film that same material constitutes, perhaps the composite bed film that is enough become by same material not.
Described doping control layer is between described resistor memory media layer and described upper electrode layer the time, described upper electrode layer can be used as the doping metals of realization to the store electricity resistance layer simultaneously, described upper electrode layer can be the elemental metals layer, or the alloy-layer of multiple metal, or the metal compound layer of non-stoichiometric, or the mixture layer of the metallic compound of multiple non-stoichiometric.Described doping control layer is between described resistor memory media layer and described lower electrode layer the time, described lower electrode layer can be used as the doping metals of realization to the store electricity resistance layer simultaneously, described lower electrode layer can be the elemental metals layer, or the alloy-layer of multiple metal, or the metal compound layer of non-stoichiometric, or the mixture layer of the metallic compound of multiple non-stoichiometric.
Described upper electrode layer can be the single-layer metal layer, also can be the composite bed metal level; Described lower electrode layer can be the single-layer metal layer, also can be the composite bed metal level.
Described resistor memory media layer is in order to the accumulation layer that realizes that resistance is changed, and it can realize the conversion between high-impedance state and the low resistance state under the effect of electrical signal.Described resistor memory media layer can be CuO, WO, and TiO, NiO, HfO, ZnO, ZrO, FeO, TaO, CoO, NbO, LiNiO, InZnO, VO, SrZrO, SrTiO, a kind of, the wherein several mixture among the CrO also can be two kinds a lamination in the above-mentioned metal oxide.
Among the present invention, the thickness of described resistor memory media layer is 1-300nm, and the thickness of doping control layer is 0.5-100nm, and upper and lower electrode layers thickness can be 100-300nm, but be not limited thereto without limits.
Memister provided by the invention, be primarily characterized in that between described resistor memory media layer and described top electrode, insert one deck doping control layer between perhaps described resistor memory media layer and the described bottom electrode, the metallic element of top electrode or bottom electrode can spread through described doping control layer described resistor memory media layer is carried out doped with metal elements, and can reach the purpose of control to resistor memory media layer doping by composition and the thickness of regulating described doping control layer, by the material of selection, can realize selection to the doped chemical of resistive memory layer with direct contacted top electrode of doping control layer or bottom electrode.Owing to the doped chemical of store electricity resistance layer and the content of doped chemical are had controllability, therefore make Memister provided by the present invention have stable electrical properties, low in energy consumption, the controlled advantage of programming polarity.
Description of drawings
The resistor accidental memory structure of Fig. 1 routine.
The I-V characteristic curve of the Memister of Fig. 2 a routine.
The resistive memory cell of Fig. 2 b routine is done one group of I-V curve of set repeatedly, reset operation.
The resistive memory cell of Fig. 2 c routine does set repeatedly, the low-resistance and the high resistant distribution map of correspondence when reset operation is.
The cross-sectional structure figure of first embodiment of Fig. 3 Memister provided by the present invention.
The cross-sectional structure figure of second embodiment of Fig. 4 Memister provided by the present invention.
The cross-sectional structure figure of the 3rd embodiment of Fig. 5 Memister provided by the present invention.
The cross-sectional structure figure of the 4th embodiment of Fig. 6 Memister provided by the present invention.
The cross-sectional structure figure of the 5th embodiment of Fig. 7 Memister provided by the present invention.
The I-V characteristic curve of a kind of specific embodiment device of Fig. 8 (a) the present invention.
The high and low resistance Distribution Statistics comparison diagram of a kind of specific embodiment Memister of Fig. 8 (b) the present invention and conventional Memister.
Number in the figure: 100 for initial state be the set operation voltage scanning curve of low-resistance, 101 for initial state be the voltage scanning curve of high resistant, 102 for initial state be low-resistance voltage scanning curve, 201 is bottom electrode, 202 is the resistor memory media layer, 203 is top electrode, 204 is insulating medium layer, 205 is doping control layer, 206 is the TaN layer in the copper wiring technique of standard Damascus, 207 is the Ta layer in the copper wiring technique of standard Damascus, 208 is Cu through hole lead in the interconnected technology of standard Damascus copper, and 111 are the low-resistance Distribution Statistics curve of the present invention's one concrete Memister, and 112 are the high resistant Distribution Statistics curve of the present invention's one concrete Memister, 121 is the low-resistance Distribution Statistics curve of conventional Memister, and 122 is the high resistant Distribution Statistics curve of conventional Memister.
Embodiment
Describe the present invention in the reference example more completely in conjunction with being shown in hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, for the clear thickness that has amplified layer and zone, but should not be considered to the proportionate relationship that strictness has reflected physical dimension as schematic diagram.
At this reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
With reference to figure 3 are cross-sectional structure figure of first embodiment of Memister provided by the present invention.As shown in Figure 3, doping control layer 205 is between top electrode 203 and resistor memory media layer 202.The copper bottom electrode that described Memister bottom electrode 201 can be to use the standard Damascus technics to form; Or the W bottom electrode that forms with the method for chemical vapour deposition (CVD); Or other metal or metallic compound, it is including but not limited to titanium, platinum, titanium nitride (TiN) or TiAlN (TiAlN); Bottom electrode 201 is metal and semimetallic composite bed also.Bottom electrode 201 can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or electrochemical deposition methods such as (ECP) to form.
Resistor memory media layer 202 deposits formation on bottom electrode 201, resistor memory media layer 202 can be CuO, WO, TiO, NiO, HfO, ZnO, ZrO, FeO, TaO, CoO, NbO, LiNiO, InZnO, VO, SrZrO, SrTiO, a kind of among the CrO, or multiple mixture.Resistor memory media layer 202 can be made of the method for thermal oxidation or chemical reaction sputter or physical vapor deposition or chemical vapor deposition or atomic layer deposition (ALD).
The ions diffusion of doped metallic elements has the semi-transparent effect of crossing in 205 pairs of top electrodes 203 of doping control layer, can regulate the amount that spreads the doping metals that sees through by the thickness of controlled doping key-course film 205, thereby arrive controllable doped purpose.Reasonably dopant dose can arrive stable electric property or reduce power consumption or adjust programming polarity optimization purpose, also can reach above-mentioned 2 or 3 simultaneously and optimize purpose.
With reference to figure 4 are cross-sectional structure figure of second embodiment of Memister provided by the present invention.As shown in Figure 4, among this embodiment, doping control layer 205 is between resistor memory media layer 202 and lower electrode layer 201, in this structure, bottom electrode 201 is the thin layers that contain required doped metallic elements, and this layer can be a metal, or the compound of the metal pair ratio of dosage non-chemically of answering, it comprises and is but is not limited to Ta, Ti, Ni, Zn, Ru, Cu, In, the nitride or the oxide of the ratio of dosage non-chemically that Ir and these metal pairs are answered.It should have excellent conducting performance as the electrode layer film, and its resistance should be less than R
On(R
OnMemory films is a low resistance state resistance).Can use methods such as physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition to form.Power on the very metal or the semimetal of this structure, it is including but not limited to titanium, platinum, titanium nitride (TiN) or TiAlN (TiAlN), electrode is metal and semimetallic composite bed also, can use methods formation such as physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition.The material of resistor memory media layer 202 and doping control layer 205 and manufacture method and middle introduce identical embodiment illustrated in fig. 3.
With reference to figure 5 are cross-sectional structure figure of the 3rd embodiment of Memister provided by the present invention.As shown in Figure 5, among this embodiment, the resistor memory media layer is the double-layer film structure of metal oxide, and first kind of resistor memory media film 202 forms on bottom electrode 201, material and manufacture method and middle introduce identical embodiment illustrated in fig. 4.Second kind of resistor memory media film 212 forms on following first kind of resistor memory media film 202, and its material can be CuO, WO, TiO, NiO, HfO, ZnO, ZrO, FeO, TaO, CoO, NbO, LiNiO, InZnO, VO, SrZrO, SrTiO, a kind of among the CrO, or multiple mixture, but constituent is different from first kind of resistor memory media film 202.It can be made of the method for chemical reaction sputter or physical vapor deposition or chemical vapor deposition or atomic layer deposition (ALD) etc.Bottom electrode 201, the material of top electrode 203 and doping control layer film 205 and manufacture method and middle introduce identical embodiment illustrated in fig. 3.
With reference to figure 6 are cross-sectional structure figure of the 4th embodiment of Memister provided by the present invention.As shown in Figure 6, itself and be that doping control layer 205 is between double-deck resistor memory media layer 202,212 and lower electrode layer 201 with reference to difference embodiment illustrated in fig. 5.Among this embodiment, the material of doping control layer 205 and manufacture method and middle introduce identical embodiment illustrated in fig. 3, the material of bottom electrode 201 and top electrode 203 and manufacture method and embodiment illustrated in fig. 4 in introduce identical, that introduces in the material of double-deck resistor memory media layer 202,212 and manufacture method and figure five illustrated embodiments is identical.
With reference to figure 7 are cross-sectional structure figure of the 5th embodiment of Memister provided by the present invention.As shown in Figure 7, this example structure forms at standard Damascus copper wiring technique, 3 layers of lamination layer structure that top electrode 203 is made up of the TaN layer in standard Damascus copper wiring technique of dosage ratio non-chemically and Ta layer 207 in the copper wiring technique of standard Damascus and copper wire layer.Bottom electrode 201 is copper wire layer in the copper-connection.Insulating medium layer 204 forms on lower electrode layer 201 and utilizes photoetching process to form window, and resistor memory media film 202 forms on bottom electrode 201, and it can be CuO, WO, TiO, NiO, HfO, ZnO, ZrO, FeO, TaO, CoO, NbO, LiNiO, InZnO, VO, SrZrO, SrTiO, a kind of among the CrO, or multiple mixture.Can form by thermal oxidation, plasma oxidation, physical vapor deposition, chemical vapor deposition, atomic layer deposition methods such as (ALD), CuxO that a kind of direct plasma oxidation bottom electrode Cu201 obtains is provided in this specific embodiment the method as resistor memory media layer 202.Doping control layer 205 forms on bottom electrode 202, and doping control layer 205 can be metal nitride, metal oxide or metal oxynitride film, and it includes but not limited to TaN, TiN, TaON, TiON.The doping control layer film should have certain electric conductivity, and its resistance should be less than 2.33R
Off(R
OnMemory films is a low resistance state resistance).Again through chemico-mechanical polishing (CMP), or the method for photoetching forms figure shown in Figure 7 after can using physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or atomic layer deposition methods such as (ALD) to make.Upper electrode layer 203 forms on doping control layer 205, uses standard Damascus copper wiring technique to make.TaN layer in standard Damascus copper wiring technique of the ratio of dosage non-chemically that Damascus technics forms in this specific embodiment and the Ta layer in the copper wiring technique of standard Damascus provide doping metals Ta jointly, mix by 205 pairs of resistor memory media layers of doping control layer 202, and control its doping content.
Next, further will use the improvement of resistance random access memory of the present invention on performance in conjunction with structure explanation embodiment illustrated in fig. 3.Bottom electrode 201 is copper wire layer in the copper-connection, the thickness that direct plasma oxidation Cu bottom electrode 201 obtains is 100nm CuxO resistor memory media layer 202, the method formation thickness that spatters with chemical reaction is 15nm TaN doping control layer 205 again, and the method formation thickness with sputter is the compound upper electrode layer 203 of 10nm Ru metal level and 50nm Cu metal level then.By the TaN doping control layer of 15nm, realize the metal Ru of CuxO resistor memory media layer 202 is mixed distribution and stable content thereof that the Ru metallic element mixes in CuxO resistor memory media layer 202.Fig. 8 (a) shows the improvement of this device on programming polarity, and curve 101 and 102 has represented that primary state is the IV curve of high resistant, can see and can not realize set (set) operation when top electrode adds malleation, and set operation can only be used negative voltage.But reset (reset) still can realize (shown in curve 100) with positive operation.Fig. 8 (b) has showed the effect of this device in the resistance of stablizing high-impedance state or low resistance state.Low-resistance distribution curve 111 and high resistant distribution curve 112 be the high resistant and the low-resistance distribution situation of device for this reason.Low-resistance distribution curve 121 and high resistant distribution curve 122 be device high resistant and low-resistance distribution situation when not using doping control layer.The distribution of high-impedance state and low resistance state has been concentrated much after the suitable as can be seen structure of the present invention.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
List of references
[1]K.Tsunoda，K.Kinoshita，“Low?Power?and?High?Speed?Switching?of?Ti-doped?NiOReRAM?under?the?Unipolar?Voltage?Source?of?less?than?3V”，IEDM?Tech?Dig.，2007
[2]Kyoobo?Jung，Joonhyuk?Choi，Yongmin?Kim，“Resistance?SwitchingCharacteristics?in?Li-doped?NiO”，J.Appl.Phys..vol.103，P.034504
[3]Dongsoo?Lee，Dong-jun?Seong，Hye?jung?Choi，“Excellent?uniformity?andreproducible?resistance?switching?characteristics?of?doped?binary?metal?oxidesfor?non-volatile?resistance?memory?applications”IEDM?Tech?Dig.，2007。
Claims (9)
1. the Memister with doping control layer comprises lower electrode layer, resistor memory media layer and upper electrode layer, it is characterized in that described Memister also comprises: with the direct contacted doping control layer of resistor memory media layer.
2. according to the described Memister of claim 1, it is characterized in that described doping control layer is metal nitride, metal oxide or metal oxynitride film.
3. according to the described Memister of claim 1, it is characterized in that described doping control layer is between described resistor memory media layer and described upper electrode layer.
4. according to claim 1 or 3 described Memisters, it is characterized in that described upper electrode layer is the elemental metals layer, or the alloy-layer of multiple metal, or the metal compound layer of non-stoichiometric, or the mixture layer of the metallic compound of multiple non-stoichiometric.
5. according to the described Memister of claim 1, it is characterized in that described doping control layer is between described resistor memory media layer and described lower electrode layer.
6. according to claim 1 or 5 described Memisters, it is characterized in that described lower electrode layer is the elemental metals layer, or the alloy-layer of multiple metal, or the metal compound layer of non-stoichiometric, or the mixture layer of the metallic compound of multiple non-stoichiometric.
7. according to the described Memister of claim 1, it is characterized in that described upper electrode layer is the single-layer metal layer, perhaps is the composite bed metal level.
8. according to the described Memister of claim 1, it is characterized in that described lower electrode layer is the single-layer metal layer, perhaps is the composite bed metal level.
9. according to the described Memister of claim 1, it is characterized in that described storage medium layer is a kind of metal oxide, or the mixture of multiple metal oxide, or the composite laminate of metal oxide of the same race not.
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| CNA2008100396075A CN101315969A (en) | 2008-06-26 | 2008-06-26 | Resistor memory with doping control layer |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005536A (en) * | 2010-10-15 | 2011-04-06 | 复旦大学 | Improved NiO-based resistive random access memory (RRAM) and manufacturing method thereof |
| CN102543173A (en) * | 2010-12-31 | 2012-07-04 | 上海丽恒光微电子科技有限公司 | MEMS (Micro Electro Mechanical System) static storage and MEMS programmable device |
| CN102655210A (en) * | 2011-03-04 | 2012-09-05 | 夏普株式会社 | Variable resistive element, method for producing the same, and nonvolatile semiconductor memory device including the variable resistive element |
| CN103178207A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Memristor |
| CN105280810A (en) * | 2014-06-11 | 2016-01-27 | 华邦电子股份有限公司 | Resistance type random access memory and manufacturing method thereof |
| CN107240642A (en) * | 2017-06-23 | 2017-10-10 | 河南工程学院 | A kind of complementary type resistance-variable storing device and preparation method thereof |
| US10164179B2 (en) | 2017-01-13 | 2018-12-25 | International Business Machines Corporation | Memristive device based on alkali-doping of transitional metal oxides |
| CN111341909A (en) * | 2020-02-07 | 2020-06-26 | 中国科学院微电子研究所 | Memory device and manufacturing method thereof, memory and electronic equipment |
| CN113130741A (en) * | 2021-02-26 | 2021-07-16 | 华中科技大学 | Vanadium oxide gate tube with high-heat-resistance heat-insulation layer and preparation method thereof |
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2008
- 2008-06-26 CN CNA2008100396075A patent/CN101315969A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102005536A (en) * | 2010-10-15 | 2011-04-06 | 复旦大学 | Improved NiO-based resistive random access memory (RRAM) and manufacturing method thereof |
| CN102543173A (en) * | 2010-12-31 | 2012-07-04 | 上海丽恒光微电子科技有限公司 | MEMS (Micro Electro Mechanical System) static storage and MEMS programmable device |
| CN102543173B (en) * | 2010-12-31 | 2014-01-08 | 张家港丽恒光微电子科技有限公司 | MEMS (Micro Electro Mechanical System) static storage and MEMS programmable device |
| CN102655210B (en) * | 2011-03-04 | 2015-04-22 | 夏普株式会社 | Variable resistive element, method for producing the same, and nonvolatile semiconductor memory device including the variable resistive element |
| CN102655210A (en) * | 2011-03-04 | 2012-09-05 | 夏普株式会社 | Variable resistive element, method for producing the same, and nonvolatile semiconductor memory device including the variable resistive element |
| CN103178207B (en) * | 2011-12-21 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Memristor |
| CN103178207A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Memristor |
| CN105280810A (en) * | 2014-06-11 | 2016-01-27 | 华邦电子股份有限公司 | Resistance type random access memory and manufacturing method thereof |
| CN105280810B (en) * | 2014-06-11 | 2018-03-27 | 华邦电子股份有限公司 | Resistive random access memory and its manufacture method |
| US10164179B2 (en) | 2017-01-13 | 2018-12-25 | International Business Machines Corporation | Memristive device based on alkali-doping of transitional metal oxides |
| CN107240642A (en) * | 2017-06-23 | 2017-10-10 | 河南工程学院 | A kind of complementary type resistance-variable storing device and preparation method thereof |
| CN111341909A (en) * | 2020-02-07 | 2020-06-26 | 中国科学院微电子研究所 | Memory device and manufacturing method thereof, memory and electronic equipment |
| CN113130741A (en) * | 2021-02-26 | 2021-07-16 | 华中科技大学 | Vanadium oxide gate tube with high-heat-resistance heat-insulation layer and preparation method thereof |
| CN113130741B (en) * | 2021-02-26 | 2022-09-13 | 华中科技大学 | Vanadium oxide gate tube with high-heat-resistance heat-insulation layer and preparation method thereof |
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