JP5464148B2 - Variable resistance element - Google Patents

Description

  The present invention relates to a resistance change element constituted by sandwiching a resistance change layer made of an insulating material between two electrodes.

  In the field of non-volatile memory, with flash memory at the top, ferroelectric memory (FeRAM), MRAM (magnetic RAM), OUM (Ovonic Unified Memory), and phase change memory (Reference 1: JP 2007-149170 A) (See the publication)). Recently, a resistance variable nonvolatile memory (ReRAM) different from these nonvolatile memories has been proposed (Reference 2: WWZhuang et al. "Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)", IEDM, paper number 7.5, pp.193-196, 2002.).

In this variable resistance nonvolatile memory, information is written by setting the resistance value of the variable resistance layer of the memory cell by applying a voltage pulse. In addition, the resistance change type nonvolatile memory can perform nondestructive reading of written information. In addition, the resistance change type nonvolatile memory is promising as having a possibility of surpassing the existing nonvolatile memory because the cell area is small and the multi-value can be increased. In Literature 1, PCMO (Pr _0.7 Ca _0.3 MnO ₃ ) and YBCO (YBa ₂ Cu ₃ O _y ) are used as the resistance change layer.

  Other proposals have been made for variable resistance nonvolatile memory (Reference 4: G.-S. Park, et al. "Observation of electric-field induced Ni filament channels in a NiOx film", APPLIED PHYSICS LETTERS, Vol.91, 222103, 2007, Literature 5: JP 2007-300082, Literature 6: C. Yoshida, et al. "High speed resistive switching in Pt / TiO2 / TiN film for nonvolatile memory application", APPLIED PHYSICS LETTERS , Vol.91, 223510, 2007.).

Document 4 uses about 50 nm of polycrystalline NiO _x (x = 1 to 1.5) as a resistance change layer, and changes to a low resistance state or a high resistance state by applying a positive voltage to the upper electrode. It is described.

Document 5 shows a method of realizing a switching operation in which a buffer layer such as ruthenium oxide is stacked between a resistance change layer and a lower electrode to suppress an increase in reset current value. Reference 6 describes the use of 80 nm microcrystalline TiO ₂ for the variable resistance layer. In this technique, two operation methods are shown. First, there is shown an operation method in which the resistance is reduced by applying a negative voltage to the upper electrode and the resistance is increased by applying a positive voltage. Secondly, a method of reducing the resistance and increasing the resistance only by applying a positive voltage is shown.

  When the resistance change element is miniaturized by using a polycrystalline or microcrystalline material for the resistance change layer as in the techniques shown in Documents 2, 4, and 6, the size of the crystal grain is larger than the element size. Cannot be ignored. In particular, there is a problem that variation in electrical characteristics between elements increases due to unevenness of the surface of the resistance change layer due to crystal grains. On the other hand, unevenness can be suppressed by reducing the thickness of the variable resistance layer. However, when the resistance change layer is thinned, a resistance change operation cannot be obtained due to a significant increase in leakage current, so a thick resistance change layer of 50 nm or more is used. In Reference 1, a buffer layer is introduced to realize a resistance change operation that suppresses an increase in the reset current value, but the composition and structure of the buffer layer are not disclosed.

As described above, in the resistance variable nonvolatile memory described above, the initial leakage current is large,
There is a problem that a stable resistance change operation cannot be obtained.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a variable resistance element having a small initial leakage current and a stable variable resistance operation.

A resistance change element according to the present invention includes at least a first electrode, a resistance change layer formed on the first electrode, and a second electrode formed on the resistance change layer, The change layer has a first layer made of an oxide of a transition metal other than tantalum and a second layer made of amorphous tantalum oxide, and the first layer is formed in contact with the first electrode , The second layer is such that silicon is added .

  As described above, according to the present invention, since the resistance change layer includes the first layer made of an oxide of a transition metal other than tantalum and the second layer made of amorphous tantalum oxide, the resistance change In the element, an excellent effect that an initial leakage current is small and a stable resistance changing operation can be obtained can be obtained.

FIG. 1 is a cross-sectional view partially showing a configuration example of a variable resistance element according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view partially showing a configuration example of the variable resistance element according to Embodiment 2 of the present invention. FIG. 3 is a characteristic diagram showing XPS spectra of O1s and Ni2p orbitals of the formed nickel oxide layer. FIG. 4 is a characteristic diagram showing XPS spectra of O1s and Ti2p orbitals of the formed titanium oxide layer. FIG. 5 is a characteristic diagram showing XPS spectra of Ta4f and O1s orbitals of the formed tantalum oxide layer. FIG. 6 is a characteristic diagram showing XRD spectra of these five types of samples obtained by subjecting the tantalum oxide layer to high temperature annealing at 500 ° C., 600 ° C., 700 ° C., and 800 ° C. in an oxygen atmosphere. FIG. 7 is a characteristic diagram showing resistance change characteristics of the resistance change element of the sample element 2. FIG. 8 is a characteristic diagram showing resistance change characteristics of the variable resistance element of the sample element 3. FIG. 9 is a characteristic diagram showing resistance change characteristics of the variable resistance element of the sample element 4. FIG. 10 is a cross-sectional view illustrating a configuration example of a memory device using the resistance change element according to the present invention. FIG. 11 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to the present invention. FIG. 12 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to the present invention. FIG. 13 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to the present invention. FIG. 14 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to the present invention. FIG. 15 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to the present invention. FIG. 16 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to the present invention. FIG. 17 is a cross-sectional view showing the configuration of the memory device using the variable resistance element according to Embodiment 3 of the present invention. FIG. 18 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to Embodiment 3 of the present invention. FIG. 19 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to Embodiment 3 of the present invention. FIG. 20 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to Embodiment 3 of the present invention. FIG. 21 is a process diagram illustrating a method for manufacturing a memory device using a resistance change element according to Embodiment 3 of the present invention. FIG. 22 is a process diagram for explaining the manufacturing method of the memory device using the resistance change element according to Embodiment 3 of the present invention. FIG. 23 is a characteristic diagram showing current-voltage characteristics of the variable resistance element according to the third embodiment of the present invention. FIG. 24 is a characteristic diagram showing variation in “Forming” voltage of the variable resistance element according to the third embodiment of the present invention. FIG. 25 is a characteristic diagram showing variations in the “Set” voltage and the “Reset” voltage of the variable resistance element according to the third embodiment of the present invention. FIG. 26 is a characteristic diagram showing variation in “Set” resistance and “Reset” resistance of the variable resistance element according to the third embodiment of the present invention. FIG. 27 is a characteristic diagram showing variation in “Forming” voltage of the resistance change element according to the third embodiment of the present invention when silicon tantalum oxide is used. FIG. 28 is a characteristic diagram showing variations in “Set” voltage and “Reset” voltage of the resistance change element according to the third embodiment of the present invention when silicon tantalum oxide is used. FIG. 29 is a characteristic diagram showing variation in “Set” resistance and “Reset” resistance of the variable resistance element according to the third embodiment of the present invention when silicon tantalum oxide is used.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a partial configuration example of the variable resistance element according to Embodiment 1 of the present invention. The variable resistance element includes a lower electrode (first electrode) 101, an upper electrode (second electrode) 103, and a variable resistance layer 102 sandwiched between the lower electrode 101 and the upper electrode 103. The resistance change layer 102 includes a nickel oxide layer (first layer) 121 and an amorphous tantalum oxide (Ta ₂ O ₅ ) layer (second layer) 122. It is formed in contact with the electrode 101. Here, in this embodiment, the nickel oxide layer 121 is used. However, the present invention is not limited to this, and the resistance change layer 102 includes a layer made of an oxide of a transition metal other than tantalum and the tantalum oxide layer 122. It only has to be formed. Hereinafter, in this embodiment, the case where the nickel oxide layer 121 is used will be described.

  For example, the nickel oxide layer 121 may have a thickness of about 2 nm, and the tantalum oxide layer 122 may have a thickness of about 10 nm. The tantalum oxide layer 122 preferably has a stoichiometric composition (stoichiometric composition). The nickel oxide layer 121 has a thickness of less than 50 nm.

  The lower electrode 101 may basically have conductivity. The lower electrode 101 is made of, for example, Au, Ni, Co, Pt, Ru, Ir, Ti, Cu, Ta, iridium-tantalum alloy (Ir-Ta), tin-added indium oxide (ITO), or an alloy thereof, or What is necessary is just to comprise from these oxides, nitrides, fluorides, carbides, silicides, and the like. Moreover, the laminated body of these materials may be sufficient.

  The upper electrode 103 may basically have conductivity. The upper electrode 103 is made of, for example, Au, Ni, Co, Pt, Ru, Ir, Ti, Cu, Ta, iridium-tantalum alloy (Ir-Ta), tin-added indium oxide (ITO), or an alloy thereof, or These oxides, nitrides, fluorides, carbides, silicides and the like can be used. Moreover, the laminated body of these materials may be sufficient.

  In the MIM (Metal Insulator Metal) structure included in the variable resistance element according to the present embodiment, adjacent layers may be stacked in at least some of these regions. Needless to say, the lower electrode 101 and the upper electrode 103 may be interchanged.

  According to the variable resistance element in the present embodiment, as will be described later, the resistance value in the high resistance state can be increased, and the leakage in the high resistance state can be reduced. Thereby, the difference in resistance value between the high resistance state and the low resistance state can be increased. For example, when miniaturization of the element is advanced, if the difference between the high resistance state and the low resistance state is small, the difference between the elements is detected as a distinction between the element in the high resistance state and the element in the low resistance state. There are cases where it becomes difficult. On the other hand, if the difference between the high resistance state and the low resistance state is large, even if some variation occurs between the elements, it is possible to easily distinguish between the element in the high resistance state and the element in the low resistance state. It becomes like this. Thus, according to the resistance change element in the present embodiment, stable resistance change operation can be realized in a large number of integrated elements.

[Embodiment 2]
Next, Embodiment 2 of the present invention will be described with reference to FIG. Also in this embodiment, the case where nickel oxide is used will be described. FIG. 2 is a cross-sectional view schematically showing a partial configuration example of the variable resistance element according to Embodiment 1 of the present invention. The variable resistance element includes a lower electrode (first electrode) 201, an upper electrode (second electrode) 203, and a variable resistance layer 202 sandwiched between the lower electrode 201 and the upper electrode 203. The resistance change layer 202 includes a nickel oxide layer (first layer) 221, an amorphous tantalum oxide (Ta ₂ O ₅ ) layer (second layer) 222, and a nickel oxide layer 221 and a tantalum oxide layer 222. And a titanium oxide layer (third layer) 223 sandwiched between the layers. The nickel oxide layer 221 is formed in contact with the lower electrode 201.

  For example, the nickel oxide layer 221 may have a thickness of about 2 nm, the tantalum oxide layer 222 may have a thickness of about 10 nm, and the titanium oxide layer 223 may have a thickness of about 3 nm. The tantalum oxide layer 222 preferably has a stoichiometric composition (stoichiometric composition). The nickel oxide layer 221 has a layer thickness of less than 50 nm.

  The lower electrode 201 may basically have conductivity. The lower electrode 201 is made of, for example, Au, Ni, Co, Pt, Ru, Ir, Ti, Cu, Ta, iridium-tantalum alloy (Ir-Ta), tin-added indium oxide (ITO), or an alloy thereof, or What is necessary is just to comprise from these oxides, nitrides, fluorides, carbides, silicides, and the like. Moreover, the laminated body of these materials may be sufficient.

  The upper electrode 203 may basically have conductivity. The upper electrode 203 is made of, for example, Au, Ni, Co, Pt, Ru, Ir, Ti, Cu, Ta, iridium-tantalum alloy (Ir-Ta), tin-added indium oxide (ITO), or an alloy thereof, or These oxides, nitrides, fluorides, carbides, silicides and the like can be used. Moreover, the laminated body of these materials may be sufficient.

  In the MIM (Metal Insulator Metal) structure included in the variable resistance element according to the present embodiment, adjacent layers may be stacked in at least some of these regions. Also in this embodiment, it goes without saying that the lower electrode 201 and the upper electrode 203 may be interchanged.

  According to the variable resistance element in the present embodiment, as will be described later, the resistance value in the high resistance state can be increased, and the leakage in the high resistance state can be reduced. Thereby, the difference in resistance value between the high resistance state and the low resistance state can be increased. For example, when miniaturization of the element is advanced, if the difference between the high resistance state and the low resistance state is small, the difference between the elements is detected as a distinction between the element in the high resistance state and the element in the low resistance state. There are cases where it becomes difficult. On the other hand, if the difference between the high resistance state and the low resistance state is large, even if some variation occurs between the elements, it is possible to easily distinguish between the element in the high resistance state and the element in the low resistance state. It becomes like this. Thus, according to the resistance change element in the present embodiment, stable resistance change operation can be realized in a large number of integrated elements.

  Further, according to the resistance change element in the present embodiment, since the titanium oxide layer 223 is added to the configuration of the first embodiment described above, the resistance value in the high resistance state can be further increased, and the high resistance The leak in the state can be made smaller. As a result, according to the present embodiment, a more stable resistance changing operation can be realized as compared with the first embodiment described above.

  Next, the variable resistance element in the first embodiment and the second embodiment described above will be described in more detail.

  First, each of the tantalum oxide layer and the nickel oxide layer does not function as a resistance change element in a single layer. By stacking a tantalum oxide layer and a nickel oxide layer to form a resistance change layer, the layer functions as a resistance change element. This was found for the first time by the inventors' experiments.

  Here, in the resistance change element of the present invention, a voltage is applied between the lower electrode and the upper electrode, and the resistance value between the lower electrode and the upper electrode (resistance change layer) is a single layer of the tantalum oxide layer. An initial process for lowering the resistance value is important. This process is called “Forming” (see Non-Patent Documents 2 and 3). After performing this treatment, by applying a predetermined positive voltage to the electrode (lower electrode) in contact with the nickel oxide layer, the resistance change from the high resistance state to the low resistance state, or from the low resistance state to the high resistance state, Either resistance state can be maintained.

  An experiment using a sample element manufactured under each condition will be described. First, the sample element will be described.

  A lower electrode in which a 5 nm thick Ti layer and a 40 nm Ru layer are stacked is formed on a semiconductor (single crystal silicon) substrate. These are common to each sample element.

Next, as the sample element 1, a tantalum oxide layer (single layer) having a layer thickness of 10 nm is formed on the lower electrode.
Further, as the sample element 2, a nickel oxide layer having a thickness of 2 nm and a tantalum oxide layer having a thickness of 10 nm are formed on the lower electrode.
Further, as the sample element 3, a nickel oxide layer having a thickness of 6 nm and a tantalum oxide layer having a thickness of 10 nm are formed on the lower electrode.
Further, as the sample element 4, a 2 nm nickel oxide layer, a 3 nm thick titanium oxide layer, and a 10 nm thick tantalum oxide layer are formed (laminated) on the lower electrode.

  Further, a Pt layer having a layer thickness of 40 nm is formed as the upper electrode. This upper electrode is also common to each sample element. Table 1 shows the layer structure of each sample element.

  Next, the production of the sample element will be briefly described. First, using a DC sputtering apparatus, Ti and Ru are continuously formed on a semiconductor substrate at room temperature to form a lower electrode. Subsequently, the sample elements 2 to 4 perform reactive sputtering with a DC sputtering apparatus, deposit nickel oxide so as to have a layer thickness of 2 nm or 6 nm, and form a nickel oxide layer. The sample element 1 does not form nickel oxide.

  In film formation by reactive sputtering of nickel oxide, Ni is used as a sputtering target, and a flow rate ratio of oxygen gas and argon gas is supplied (supplied) in a chamber in which film formation is performed at 1: 7. The pressure in the chamber is about 1.5 Pa, the film forming temperature is 300 ° C., and the DC power is 0.5 kW.

  Next, the results of evaluating the composition of the formed nickel oxide layer by XPS (X-ray photoemission spectroscopy) will be described. FIG. 3 shows XPS spectra of O1s (517-537 eV) and Ni2p (845-885 eV) orbitals. O1s is shown in FIG. 3 (a), and Ni2p is shown in FIG. 3 (b). Al (Kα ray) was used as the X-ray source. As shown in FIG. 3, the composition ratio (O / Ni) of nickel oxide obtained from the peak areas of O1s and Ni2p is approximately 1, indicating that NiO is formed. As described above, the nickel oxide layer formed by the reactive sputtering method is in a polycrystalline state.

  Next, formation of titanium oxide in the sample element 4 will be described. Also in the formation of titanium oxide, reactive sputtering is used by a DC sputtering apparatus. Ti is used as a sputtering target, and a flow rate ratio of oxygen gas and argon gas is supplied into the chamber at 1: 5. The pressure in the chamber is about 1 Pa, the film forming temperature is 300 ° C., and the DC power is 4.2 kW.

Next, the result of evaluating the composition of the formed titanium oxide layer by XPS will be described. FIG. 4 shows XPS spectra of O1s (525-545 eV) and Ti2p (450-480 eV) orbitals. O1s is shown in FIG. 4A, and Ti2p is shown in FIG. 4B. Al (Kα ray) was used as the X-ray source. As shown in FIG. 4, the composition ratio (O / Ti) of the titanium oxide obtained from the peak areas of O1s and Ti2p is approximately 2, indicating that TiO ₂ is formed. As described above, the titanium oxide layer formed by the reactive sputtering method is in a polycrystalline state.

Next, formation of tantalum oxide will be described. In forming the tantalum oxide layer, an RF sputtering apparatus is used. Ta ₂ O ₅ is used as a sputtering target, and oxygen gas and argon gas are supplied into the chamber at 10 sccm and 5 sccm. The film forming temperature was 350 ° C. and the power was 2 kW. Note that sccm is a unit of flow rate, and indicates that a fluid at 0 ° C. and 1 atm flows 1 cm ³ per minute.

Next, the results of evaluating the composition of the formed tantalum oxide layer by XPS will be described. FIG. 5 shows XPS spectra of Ta4f (25-35 eV) and O1s (525-540 eV) orbitals. Ta4f is shown in FIG. 5A, and O1s is shown in FIG. 5B. Al (Kα ray) was used as the X-ray source. As shown in FIG. 5, in the Ta4f region, Ta ⁵⁺ 4f _5/2 and Ta ⁵⁺ 4f _7/2 peaks derived from Ta ₂ O ₅ and Ta ⁰ 4f _5/2 and Ta ⁰ derived from the weak metal Ta. A 4f _7/2 peak is observed. In the O1s region, a peak derived from the Ta—O bond is observed. The composition ratio (O / Ta) of the tantalum oxide obtained from these peak areas is 2.5, indicating that a stoichiometric tantalum oxide layer is formed.

  Next, the results of examining and evaluating the crystallinity and crystallization temperature of the formed tantalum oxide layer by XRD (X-Ray diffraction) will be described. In this investigation, high temperature annealing at 500 ° C., 600 ° C., 700 ° C., and 800 ° C. was performed in an oxygen atmosphere on the tantalum oxide layer formed on silicon by the sputtering method described above, and these five types of samples were subjected to the annealing. Do.

FIG. 6 shows the XRD spectrum of each sample. From FIG. 6, it can be confirmed that Ta ₂ O ₅ is crystallized at 700 ° C. or higher and the (001) plane, (200) plane and (201) plane are formed. Note that the peak observed at a temperature lower than 700 ° C. is derived from Si of the substrate. Here, in the above-described sample element 1, sample element 2, sample element 3, and sample element 4, since the high temperature annealing at 700 ° C. or higher is not performed, the tantalum oxide (Ta ₂ O ₅ ) layer is amorphous. is there. Even when the variable resistance element of the present invention is mounted on a wiring layer of an integrated circuit, the temperature of the manufacturing process of the wiring layer is 600 ° C. or lower, so that the tantalum oxide (Ta ₂ O ₅ ) layer is amorphous. Keep state.

  After forming each layer constituting the variable resistance layer as described above, a platinum layer serving as an upper electrode is formed by an “electron-gun” vapor deposition method. In the formation of the Pt layer, a pattern to be the upper electrode is formed using a stencil mask.

  The initial leakage current and resistance change characteristics between the upper and lower electrodes of the sample element 1, the sample element 2, the sample element 3, and the sample element 4 manufactured as described above were evaluated. The planar shape of the electrode formed on each sample element is 90 μm square. In addition, the resistance change characteristic is evaluated after applying a positive bias to the lower electrode to lower the resistance change layer (Forming). By this “Forming” process, a current path is formed in the resistance change layer of the variable resistance element having the MIM structure, and it is considered that a resistance change phenomenon occurs in the current path (resistance change path).

  The evaluation results are shown in Table 2. In Table 2, the case where the initial leakage current was as large as 1E-5A or higher when a voltage of 1V was applied x the case where the initial leakage current was as small as less than 1E-5A when a voltage of 1V was applied, indicating good insulation Was evaluated as ◯, when the resistance change characteristic was not shown as x, and when the resistance change characteristic was shown as ◯. Also, when the ON / OFF ratio of the current when the voltage of 1 V is applied is 5 digits or less, × when the ON / OFF ratio of the current when the voltage of 1 V is applied is 5 digits or more, ○, resistance change voltage ( The case where the reproducibility of the current) was low was judged as x, and the case where the resistance change voltage (current) was reproducible was judged as ◯.

As shown in Table 2, the sample element 1 using the tantalum oxide single layer has a low initial leakage current but does not exhibit switching characteristics. The resistance change characteristics of Ta ₂ O ₅ have not been reported in papers. Note that it is already known that a sample using a NiO single layer film has a very large initial leakage current, and can obtain resistance change characteristics only with a thick film of 50 nm or more (Non-patent Document 2). In addition, it is already known that a sample using a TiO ₂ single layer film has a very large initial leakage current and cannot obtain a resistance change characteristic (Non-patent Document 3).

  Next, the sample element 2 and the sample element 3 in which the resistance change layer has a stacked structure of a nickel oxide layer having a thickness of 2 nm and 6 nm and a tantalum oxide layer having a thickness of 10 nm have a relatively low initial leakage current and “Forming”. Later, switching characteristics were shown. FIGS. 7 and 8 are diagrams showing resistance change characteristics of the resistance change elements of the sample element 2 and the sample element 3, respectively.

  7 and 8, (a) can be said to indicate the state of the initial leakage current of the sample element 2 and the sample element 3 before “Forming”. 7 and 8, (b) shows a state of resistance change when a positive bias (a negative bias is applied to the upper electrode) is applied to the lower electrode after “Forming”. (C) of FIG. 7 is reference data and shows an initial leakage current before “Forming” of the sample element 1 having a single layer of tantalum oxide having a layer thickness of 10 nm.

  As shown in FIG. 7B, the “Forming” sample element 2 applies a positive bias (a negative bias to the upper electrode) to the lower electrode in contact with the nickel oxide layer, thereby increasing the resistance from the low resistance state. The resistance changes to the resistance state. In contrast, the reverse bias does not change the resistance to the high resistance state. Further, as shown in FIG. 8B, the resistance of the sample element 3 subjected to “Forming” changes from the low resistance state to the high resistance state by applying a negative bias to the upper electrode. In contrast, the reverse bias does not change the resistance to the high resistance state.

It is considered that these resistance changes toward the high resistance side are caused by oxygen ion (O ⁻ ) diffusion toward the electrode (lower electrode) in contact with the nickel oxide layer. Oxygen ions (O ⁻ ) diffuse in the direction of the lower electrode due to the electric field in the nickel oxide layer / tantalum oxide layer, and resistance in the nickel oxide layer, the nickel oxide layer / tantalum oxide layer interface, or the lower electrode / nickel oxide layer interface It is considered that the oxidation reaction of the change path occurs, and as a result, the resistance change described above occurs. From the above-described experiment, it is considered that the resistance change path in the nickel oxide layer / tantalum oxide layer stack is formed so as to penetrate from the nickel oxide layer to the inside of the tantalum oxide layer.

  Further, the current between the upper electrode and the lower electrode in the low resistance state after “Forming” of the sample element 2 shown in FIG. 7B is based on the initial leakage current of the sample element 1 shown in FIG. Is also big. Therefore, it can be said that the resistance value of the tantalum oxide layer in the sample element 2 is lower than the resistance value before “Forming”. From this, it is considered that a resistance change path is also formed in the tantalum oxide layer of the sample element 2 by the “Forming” process.

  As described above, the phenomenon of resistance change is considered to occur in the nickel oxide layer, the nickel oxide layer / tantalum oxide layer interface, or the lower electrode / nickel oxide layer interface along the resistance change path. Here, in the case of a configuration in which a tantalum oxide layer is formed on a nickel oxide layer, each interface described above is hidden when the upper electrode is formed, and is not easily damaged by sputtering when the upper electrode is formed. Become. As a result, it is considered that a stable resistance changing operation can be obtained.

  By the way, in the sample element 3 in which the nickel oxide layer is thickened to 6 nm, the reproducibility of the resistance change operation is poor as shown in FIG. Here, the nickel oxide layer formed by reactive sputtering is a polycrystal as described above, and as the layer thickness is increased, the crystal grains increase and the surface irregularities increase. It is considered that the surface unevenness deterioration due to the increase in film thickness is one of the causes of the decrease in reproducibility in the sample element 3.

  Next, the sample element 4 will be described with reference to FIG. In the sample element 4 subjected to “Forming”, as shown in FIG. 9A, when the negative bias applied to the upper electrode is increased from the low resistance state, a predetermined voltage value (−1.2 V) is obtained. 9), the resistance value increases rapidly as shown in FIG. 9B, and the resistance changes to the high resistance state as shown in FIG. 9C. The high resistance state shown in FIG. 9C is stable in the range of about 0 to −2.5V. In this high resistance state, when a negative bias exceeding −2.5 V is applied to the upper electrode, the resistance value decreases rapidly as shown in FIG. 9D, and the low resistance shown in FIG. Resistance changes to the state. Thus, resistance can be changed by a negative bias (positive bias) applied to the upper electrode (lower electrode). The state of each resistor is stable in the predetermined voltage range as described above. Such a resistance change does not occur in reverse bias.

The resistance change described above is also considered to be caused by oxygen ion (O ⁻ ) diffusion toward the lower electrode in contact with the nickel oxide layer, as described above. In the sample element 4, oxygen ions (O ⁻ ) are diffused in the direction of the lower electrode due to the electric field in the nickel oxide layer / titanium oxide / tantalum oxide layer, and the lower electrode / nickel oxide layer interface, in the nickel oxide layer, and oxidized. It is considered that the oxidation reaction of the resistance change path occurs at the nickel layer / titanium oxide layer interface, the titanium oxide layer, or the titanium oxide layer / tantalum oxide layer interface, and as a result, the above-described resistance change occurs.

  In the sample element 4, the ratio (ON / OFF ratio) between the low resistance state shown in FIG. 9A and the high resistance state shown in FIG. It shows that a variable resistance element having an OFF resistance can be obtained. In the sample element 4, a titanium oxide layer is provided between the tantalum oxide layer and the nickel oxide layer, and the titanium oxide layer functions as a storage / supply source of the above-described oxygen (ion), so that the resistance change can be performed more easily. It is considered that

  From the above experimental results, it is possible to realize a variable resistance element with reduced initial leakage by using a laminated structure of a nickel oxide layer and an amorphous tantalum oxide layer as the variable resistance layer of the variable resistance element according to the present invention. It has been shown. In addition, since the resistance change element of the present invention can form a very flat interface between the upper electrode and the tantalum oxide layer, there is less variation in the resistance change path between elements, which is advantageous for miniaturization (high integration). is there. In addition, by introducing a titanium oxide layer, a very high resistance state can be realized, and the leakage current at OFF can be reduced, which is more preferable.

  When a polycrystalline tantalum oxide layer is used, current leakage in the initial state is large, making it difficult to use as a resistance change element. For this reason, it is important to use the tantalum oxide layer in an amorphous state. Further, by increasing the thickness of the tantalum oxide layer, it is possible to reduce the initial leakage current. Moreover, when forming a tantalum oxide layer after forming a nickel oxide layer or a titanium oxide layer, the surface roughness (surface irregularities) of the nickel oxide layer or the titanium oxide layer can be reduced by increasing the thickness of the tantalum oxide layer. Can do.

  On the other hand, when the tantalum oxide layer is thinned, various damages easily enter the nickel oxide layer and the titanium oxide layer made of the tantalum oxide layer, such as when the upper electrode is formed on the tantalum oxide layer by sputtering. In such a state, it becomes difficult to obtain the above-described resistance change (switching) characteristics. Therefore, the tantalum oxide layer should have a thickness that does not cause damage in accordance with the manufacturing conditions.

  Further, when the tantalum oxide layer is made thinner than the nickel oxide layer or the titanium oxide layer, the initial leakage current is increased. In addition, as described above, the nickel oxide layer and the titanium oxide layer, which are polycrystals, have a problem in that the surface unevenness increases as the film becomes thicker. For this reason, it is important to form the nickel oxide layer and the titanium oxide layer thinner than the tantalum oxide layer.

  Next, application examples of the variable resistance element according to the present invention will be described. Below, the case where the resistance change element in this invention is applied to a memory | storage device is demonstrated.

  As shown in the sectional view of FIG. 10, the memory device includes, for example, a MOS transistor including a gate insulating film 1002, a gate electrode 1003, a source 1004, and a drain 1005 on a semiconductor substrate 1001 made of single crystal silicon. . This MOS transistor becomes a control transistor. Further, on the interlayer insulating film 1006 formed on the gate electrode 1003, a resistance change element according to the present invention including the lower electrode 1008, the resistance change layer 1009, and the upper electrode 1010 is formed. The resistance change layer 1009 has, for example, a stacked structure of a nickel oxide layer and an amorphous tantalum oxide layer. The resistance change layer 1009 includes a titanium oxide layer sandwiched between a nickel oxide layer and an amorphous tantalum oxide layer. Note that the lower electrode 1008 is connected to the drain 1005 through a contact via 1007 formed in a contact hole of the interlayer insulating film 1006.

  Further, an interlayer insulating film 1011 is formed on the variable resistance element, and a wiring 1014 serving as a bit line and a grounded wiring 1015 are formed on the interlayer insulating film 1011. The wiring 1014 is connected to the contact via 1012 that contacts the source 1004 through the interlayer insulating film 1011 and the interlayer insulating film 1006, and the wiring 1015 is connected to the upper electrode 1010 by the via 1013 formed in the via hole of the interlayer insulating film 1011. Connected to. Note that the gate electrode 1003 is connected to a word line.

  The control transistor described above is, for example, an N-type field effect transistor (NFET). The control transistor may be a P-type field effect transistor (PFET). The gate insulating film 1002 may be made of, for example, silicon oxide. For example, it can be formed by thermally oxidizing the surface of a semiconductor substrate 1001 made of single crystal silicon. Note that the gate insulating film 1002 may be formed of a metal oxide such as hafnium oxide, zirconium oxide, or aluminum oxide. Moreover, silicate and nitride may be sufficient and these laminated structures may be sufficient.

  The gate electrode 1003 may be made of polysilicon to which phosphorus is added, for example. Note that the gate electrode 1003 may be a metal gate or a silicide gate. The lower electrode 1008 and the upper electrode 1010 may be made of ruthenium, for example. As described above, each electrode basically has only to be electrically conductive. For example, Au, Ni, Co, Pt, Ru, Ir, Ti, Cu, Ta, iridium-tantalum alloy ( Ir—Ta), tin-added indium oxide (ITO), or an alloy thereof, or an oxide, nitride, fluoride, carbide, silicide, or the like thereof.

  The variable resistance layer 1009 may have a stacked structure of a nickel oxide layer with a thickness of 2 nm and a tantalum oxide layer with a thickness of 10 nm. Note that in the resistance change layer 1009, a nickel oxide layer may be disposed on the lower electrode 1008 side, and a tantalum oxide layer may be disposed on the lower electrode 1008 side. Here, the places where the resistance changes are the interface between the lower electrode 1008 and the nickel oxide layer, and the inside of the nickel oxide layer. For this reason, from the viewpoint of reducing the influence of sputtering damage when forming the upper electrode 1010 in these regions, a nickel oxide layer is disposed on the lower electrode 1008 side, and after the tantalum oxide layer is formed thereon, the upper electrode 1010 is formed. Should be formed.

  Next, a process for the resistance change layer 1009 (an operation method of the resistance change element) will be described. First, in order to perform “Forming”, for example, a positive voltage is applied to the gate electrode 1003 to turn on the control transistor, a positive voltage is applied to the wiring 1014, and a positive voltage is applied to the lower electrode 1008. The resistance change layer 1009 is reduced in resistance. At this time, the voltage applied to the gate electrode 1003 is adjusted so that the current is limited by the control transistor so that the resistance change layer 1009 has a desired resistance value. In “Forming”, a voltage may be applied to the wiring 1015 instead of the wiring 1014.

  In addition, when switching between the low resistance state and the high resistance state after “Forming” as described above, a positive voltage of a predetermined voltage is applied to the wiring 1014 while the control transistor is on. At this time, when the resistance is changed to the low resistance state, a higher voltage may be applied to the wiring 1014 than when the resistance is changed to the high resistance state. Further, the voltage applied to the gate electrode 1003 is adjusted so that the current is limited by the control transistor so that the resistance change layer 1009 has a desired (predetermined) resistance value. Note that when the resistance is changed from the high resistance state to the low resistance state, a positive voltage may be applied to the wiring 1015 instead of the wiring 1014.

  Next, a method for manufacturing the above-described storage device will be described. First, as illustrated in FIG. 11, a gate insulating film 1002 and a gate electrode 1003 are formed over a semiconductor substrate 1001. For example, the gate insulating film 1002 and the gate electrode 1003 can be formed by depositing silicon oxide and phosphorus-added polysilicon and patterning these films using a known photolithography technique and etching technique.

Next, as shown in FIG. 12, by using the gate electrode 1003 as a mask, phosphorus is ion-implanted at 2 × 10 ¹⁵ cm ⁻² (set value), thereby forming a source 1004 and a drain 1005.

  Next, as shown in FIG. 13, silicon oxide is deposited on the entire surface of the semiconductor substrate 1001, and the surface of the deposited film is planarized by using a CMP (Chemical Mechanical Polishing) method to form an interlayer insulating film 1006. Next, a contact hole is formed in the interlayer insulating film 1006 by using a known photolithography technique and etching technique, and titanium nitride (TiN) and tungsten (W) are deposited to fill the inside of the contact hole. . Further, the metal film on the interlayer insulating film 1006 is removed using a CMP method, and a contact via 1007 is formed.

  Next, a ruthenium layer 40 nm, a nickel oxide layer 2 nm, a tantalum oxide layer 10 nm, and a ruthenium layer 40 nm are sequentially deposited on the interlayer insulating film 1006 in which the contact via 1007 is formed, and these are deposited by a known photolithography technique and etching technique. By patterning, as shown in FIG. 14, a resistance change element including a lower electrode 1008, a resistance change layer 1009, and an upper electrode 1010 is formed. A lower electrode 1008 is connected to the contact via 1007.

  A DC sputtering method is used for depositing the ruthenium layer. For the deposition of the nickel oxide layer, a reactive sputtering method using a DC sputtering apparatus is used. In this case, Ni is used as the sputtering target, and the flow rate ratio of oxygen gas to argon gas is 1: 7. The pressure in the chamber is about 1.5 Pa, the film forming temperature is 300 ° C., and the power is 0.5 kW. RF sputtering is used to deposit the tantalum oxide layer. In this case, a tantalum oxide layer is used as a sputtering target, and oxygen gas and argon gas are supplied at 10 sccm and 5 sccm. The film forming temperature is 350 ° C. and the power is 2 kW.

  Next, silicon oxide is deposited on the interlayer insulating film 1006 on which the variable resistance element described above is formed, and the surface of this silicon oxide deposited film is planarized by the CMP method, as shown in FIG. An insulating film 1011 is formed.

  Next, a through hole reaching the source 1004 and a through hole reaching the upper electrode 1010 are formed in the interlayer insulating film 1011 and the interlayer insulating film 1006 by patterning using a known photolithography technique and etching technique. Next, titanium nitride and tungsten are deposited and filled in the through holes. Thereafter, the surface is planarized using CMP, and titanium nitride and tungsten other than the through holes are removed, thereby forming contact vias 1012 and vias 1013 as shown in FIG. Further, titanium nitride and aluminum are deposited on the interlayer insulating film 1011, and these deposited films are patterned by a known photolithography technique and etching technique, whereby the wiring 1014 and the wiring 1015 are formed.

  In the memory device manufactured as described above, the variable resistance element according to the present invention is connected to the drain 1005 of the control transistor, which is advantageous for high integration. In addition to the features of the present invention that the initial leakage is small and stable resistance change operation can be realized in the memory device, control is performed at the time of voltage application for "Forming" or resistance change from high resistance to low resistance. Since the current can be controlled by the gate voltage of the transistor, a resistance variation operation with low variation can be realized.

  In the above description, the variable resistance layer 1009 is formed from a nickel oxide layer and a tantalum oxide layer. However, the variable resistance layer 1009 includes a nickel oxide layer, a titanium oxide layer, and a tantalum oxide layer as described below. You may form from.

  In the formation of the variable resistance layer 1009 by the three layers, first, the ruthenium layer 40 nm, the nickel oxide layer 2 nm, the titanium oxide layer 3 nm, the tantalum oxide layer 10 nm, and the ruthenium layer 40 nm on the interlayer insulating film 1006 in which the contact via 1012 is formed. Are sequentially deposited and patterned by a known photolithography technique and etching technique. As a result, as shown in FIG. 14, a resistance change element including the lower electrode 1008, the resistance change layer 1009, and the upper electrode 1010 is formed.

  Here, the ruthenium layer, nickel oxide layer, and tantalum oxide layer may be formed in the same manner as described above. For the deposition of the titanium oxide layer, a reactive sputtering method using a DC sputtering apparatus is used. In this case, Ti is used as the sputtering target, and the flow rate ratio of oxygen gas to argon gas is supplied at 1: 5. The pressure in the chamber may be 1 Pa, the film forming temperature may be 300 ° C., and the power may be 4.2 kW.

  As described above, even in the memory device in which the resistance change layer 1009 includes the nickel oxide layer, the titanium oxide layer, and the tantalum oxide layer, the resistance change element according to the present invention is configured to be connected to the drain 1005 of the control transistor. Therefore, it is advantageous for high integration. In addition to the features of the present invention that the initial leakage is small and stable resistance change operation can be realized in the memory device, control is performed at the time of voltage application for "Forming" or resistance change from high resistance to low resistance. Since the current can be controlled by the gate voltage of the transistor, a resistance variation operation with low variation can be realized.

[Embodiment 3]
Next, a third embodiment of the present invention will be described. In this embodiment, the case where a resistance change layer is formed of a zirconium oxide layer and a tantalum oxide layer will be described.

  First, a memory device using a variable resistance element according to the present embodiment (one-transistor one-resistance type ReRAM) will be described. As shown in FIG. 17, the memory device includes a MOS transistor including a gate insulating film 1702, a gate electrode 1703, a source 1704, and a drain 1705 on a semiconductor substrate 1701 made of single crystal silicon. This MOS transistor becomes a control transistor. For example, the region of the semiconductor substrate 1701 where the MOS transistor is formed is a P-type region (P well), and the source 1704 and the drain 1705 are N-type. A wiring layer including a wiring 1710 and a wiring 1711 is formed over the interlayer insulating film 1706 formed over the gate electrode 1703. The wiring 1710 is connected to the source 1704 through a contact via 1707, and the wiring 1711 is connected to the drain 1705 through a contact via 1708.

  An interlayer insulating film 1712 is formed over the wiring layer having the wiring 1710 and the wiring 1711. On the interlayer insulating film 1712, a lower electrode 1714, a first metal oxide layer (first layer) 1715, A resistance change element according to the present invention, which includes the second metal oxide layer (second layer) 1716 and the upper electrode 1718, is formed.

  In the present embodiment, the first metal oxide layer 1715 and the second metal oxide layer 1716 constitute a resistance change layer, and the first metal oxide layer 1715 is made of, for example, zirconium oxide, and the second metal oxide layer The layer 1716 is composed of an amorphous tantalum oxide layer. The lower electrode 1714 is connected to the first metal oxide layer 1715, and the upper electrode 1718 is connected to the second metal oxide layer 1716. Note that an interlayer insulating film 1717 is formed on the second metal oxide layer 1716, and an upper electrode 1718 is formed on the interlayer insulating film 1717.

  Here, the lower electrode 1714 may basically have conductivity. The lower electrode 1714 is made of, for example, Au, Ni, Co, Pt, Ru, Ir, Ti, Cu, Ta, iridium-tantalum alloy (Ir-Ta), tin-added indium oxide (ITO), or an alloy thereof, or What is necessary is just to comprise from these oxides, nitrides, fluorides, carbides, silicides, and the like. Moreover, the laminated body of these materials may be sufficient.

  Further, the upper electrode 1718 may basically have conductivity. The upper electrode 1718 is made of, for example, Au, Ni, Co, Pt, Ru, Ir, Ti, Cu, Ta, iridium-tantalum alloy (Ir-Ta), tin-added indium oxide (ITO), or an alloy thereof, or These oxides, nitrides, fluorides, carbides, silicides and the like can be used. Moreover, the laminated body of these materials may be sufficient.

  In the MIM (Metal Insulator Metal) structure included in the variable resistance element according to the present embodiment, adjacent layers may be stacked in at least some of these regions. Needless to say, also in this embodiment mode, the lower electrode 1714 and the upper electrode 1718 may be interchanged.

  In this embodiment mode, the contact area between the upper electrode 1718 and the second metal oxide layer 1716 is smaller than the contact area between the lower electrode 1714 and the first metal oxide layer 1715. Therefore, the area of the MIM structure serving as a resistance change element including the resistance change layer is limited by the contact area between the upper electrode 1718 and the tantalum oxide layer 1716.

  Embodiment 3 of the present invention is characterized in that zirconium oxide having higher film formation controllability than nickel oxide is used. By using a material having high film formation controllability, when a plurality of resistance change elements are integrated, a stable resistance change operation with little variation between elements can be realized. In addition, since the resistance state (high resistance state or low resistance state) of the variable resistance element is controlled by the transistor with the configuration of one transistor and one resistance (1T1R), it is possible to reduce variations in the resistance state to be set. Become.

Next, a method for manufacturing a memory device using the resistance change element in this embodiment will be described. First, the gate insulating film 1702 and the gate electrode 1703 are formed over the semiconductor substrate 1701. For example, the gate insulating film 1702 and the gate electrode 1703 can be formed by depositing silicon oxide and phosphorus-added polysilicon and patterning these films using a known photolithography technique and etching technique. Next, using the formed gate electrode 1703 as a mask, phosphorus is ion-implanted at a dose of 2 × 10 ¹⁵ cm ⁻² (set value), whereby a source 1704 and a drain 1705 are formed.

  Next, as shown in FIG. 19, silicon oxide is deposited on the entire surface of the semiconductor substrate 1701, and the surface of the deposited film is planarized by CMP to form an interlayer insulating film 1706. Next, a contact hole is formed in the interlayer insulating film 1706 using a known photolithography technique and etching technique, and titanium nitride (TiN) and tungsten (W) are deposited to fill the inside of the contact hole. . Further, the metal film on the interlayer insulating film 1706 is removed by CMP to form contact vias 1707 and contact vias 1708.

  Next, titanium nitride and aluminum are sequentially deposited on the interlayer insulating film 1706 in which the contact via 1707 and the contact via 1708 are formed, and these deposited films are patterned by a known photolithography technique and etching technique, thereby providing wiring. 1710 and wiring 1711 are formed. Subsequently, silicon oxide is deposited on the entire surface so as to cover these wirings, and the surface of the deposited film is planarized by CMP to form an interlayer insulating film 1712.

  Next, via holes are formed in the interlayer insulating film 1712 using a known photolithography technique and etching technique, and TiN and tungsten W are deposited, and the via holes are filled with these. Further, the metal film on the interlayer insulating film 1712 is removed by using a CMP method, and a via 1713 is formed.

  Next, a ruthenium layer of 40 nm is deposited on the interlayer insulating film 1712 and is patterned by a known photolithography technique and etching technique, thereby forming a lower electrode 1714 as shown in FIG. A DC sputtering method may be used for depositing the ruthenium layer.

Further, a zirconium oxide layer 1 nm and a tantalum oxide layer 8 nm are sequentially deposited on the interlayer insulating film 1712 so as to cover the lower electrode 1714, thereby forming a first metal oxide layer 1715 and a second metal oxide layer 1716. For the formation of the zirconium oxide layer, an ALD (Atomic Layer Deposition) apparatus may be used. In this case, tetrakisdiethylaminozirconium (ZDEAZ) is used as a raw material, and the temperature condition at the time of deposition may be 140 ° C. Further, the tantalum oxide layer may be formed using an RF sputtering apparatus. In this case, Ta ₂ O ₅ is used as the sputtering target, and oxygen gas and argon gas are supplied at 10 sccm and 5 sccm into the chamber in which the deposition is performed. The temperature condition during deposition is 350 ° C., and the power of RF sputtering is 2 kW.

  After forming the first metal oxide layer 1715 and the second metal oxide layer 1716 as described above, silicon oxide is deposited on the entire surface so as to cover the second metal oxide layer 1716, and the surface of the deposited film is formed. An interlayer insulating film 1717 is formed by planarization by a CMP method.

  Next, a via hole reaching the second metal oxide layer 1716 in the upper region of the lower electrode 1714 is formed in the interlayer insulating film 1717, and then a ruthenium layer of 40 nm is deposited, and this is formed by a known photolithography technique and etching. By patterning using a technique, an upper electrode 1718 is formed as shown in FIG. A DC sputtering method may be used for depositing the ruthenium layer.

  Next, the characteristics of the variable resistance element according to the present embodiment will be described. First, the resistance change characteristic will be described. First, the current-voltage characteristics of the variable resistance element in this embodiment will be described with reference to FIG. FIG. 23 is a characteristic diagram showing the resistance change characteristic of the resistance change element (resistance change layer), showing the relationship between the voltage applied to the upper electrode 1718 and the current flowing between the electrodes. The first metal oxide layer 1715 and the second metal oxide layer 1716 constitute a resistance change layer.

  In FIG. 23, a process of forming a resistance value between the electrodes (resistance change layer) lower than the resistance value of the tantalum oxide layer formed as a single layer by voltage application, from the high resistance state of the resistance change layer to the low resistance state. The current-upper electrode applied voltage curve in each operation of switching (Set) and switching (Reset) from the low resistance state to the high resistance state of the variable resistance layer is shown. 23A shows a change in “Forming”, FIG. 23B shows a change in “Reset”, and FIG. 23A shows a change in “Set”.

  In “Forming” and “Set”, the level resistance in “Set” is controlled by the saturation current (Isat.) Of the control transistor, and a positive voltage is applied to the upper electrode 1718. In FIG. 23, the characteristic curve indicated by the arrow in the range where the upper electrode voltage is 4 V or more and the current is 200 μA or more shows the drain current-applied voltage characteristic (saturation current of the control transistor) of the control transistor at the gate voltage Vgate = 4V. Show.

In “Forming” and “Set”, as shown in FIGS. 23A and 23C, when the upper electrode applied voltage is around 4 V, a rapid current increase occurs due to the lower resistance of the resistance change layer. It can be seen that the current increase is limited by the saturation current value of the control transistor.
On the other hand, in “Reset”, a negative voltage is applied to the upper electrode 1718. In this “Reset”, the current is not limited by the control transistor, and a current flows between the upper electrode 1718 and the semiconductor substrate 1701 (p-well). “Reset” can also be performed by applying a positive voltage to the wiring 1711 (drain 1705) and the gate electrode 1703.

  Next, variation in voltage value during each operation (resistance change) will be described. 24 shows variation in “Forming” voltage, FIG. 25 shows variation in “Set” voltage and “Reset” voltage, and FIG. 26 shows variation in resistance values in “Set” state and “Reset” state. Both are Weibull plots.

  As shown in FIG. 24, FIG. 25, and FIG. 26, a laminated film of zirconium oxide and tantalum oxide is used for the resistance change layer and the “Forming” and “Set” operations are controlled by the control transistor (1T1R). It can be seen that a stable variable resistance element with a small resistance variation and a voltage at which the resistance state changes can be realized.

  Note that an excellent resistance change element can be realized even if silicon tantalum oxide to which silicon is added is used instead of tantalum oxide, in other words, even if silicon is added to the second metal oxide layer 1716.

Hereinafter, the variation in voltage value during each operation (when the resistance is changed) in the case where the resistance change layer is formed of a laminated film composed of a zirconium oxide layer having a thickness of 1 nm and a silicon tantalum oxide layer having a thickness of 8 nm will be described. Note that silicon is added to the silicon tantalum oxide layer so that Ta ₂ O ₅ : SiO ₂ = 76 mol%: 24 mol%. 27 shows variation in “Forming” voltage, FIG. 28 shows variation in “Set” voltage and “Reset” voltage, and FIG. 29 shows variation in resistance values in “Set” state and “Reset” state. Both are Weibull plots.

  As shown in FIGS. 27, 28, and 29, even when a laminated film of zirconium oxide and silicon tantalum oxide is used for the variable resistance layer, a stable variable resistance element having a small resistance variation voltage and resistance variation is obtained. It can be seen that it can be realized. Further, as can be seen from the comparison between FIG. 24 and FIG. 27, when the silicon tantalum oxide layer is used, the “Forming” voltage can be greatly reduced as compared with the case where the tantalum oxide layer is used.

  The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. For example, although the case where nickel oxide and zirconium oxide are used has been described above, the present invention is not limited to this, and oxides of other transition metals may be used. The present invention is characterized in that the variable resistance layer has a first layer made of an oxide of a transition metal other than tantalum and a second layer made of amorphous tantalum oxide.

  Here, the transition metal is defined as an element excluding lanthanoids and actinides among elements existing between Group 3 elements and Group 11 elements in the periodic table. The transition metal element has a feature that a large number of electrons widely distributed outside the d orbit or f orbital exist. This property means that there are many electrons that can participate in metal bonding, and there are many possible oxidation numbers. Therefore, when a transition metal oxide is used as the resistance change layer, the oxidation number can be controlled by applying a voltage, and the resistance value can be changed.

  On the other hand, amorphous tantalum oxide, which is also a transition metal oxide, stabilizes in a low-resistance state after having once lowered its resistance. By laminating a transition metal oxide different from tantalum oxide and amorphous tantalum oxide, a stable path (current path) is formed in the amorphous tantalum oxide layer. The transition metal oxide layer different from the formed tantalum oxide functions as a resistance change layer. Since the portion where the resistance changes is limited to a part of the conduction path, variation in electrical characteristics can be suppressed.

  Further, by forming a transition metal oxide layer different from tantalum oxide into a thin film, unevenness can be suppressed, and variation in electrical characteristics can be further suppressed. The transition metal oxide different from tantalum oxide is preferably a nickel oxide film, a titanium oxide film, a zirconium oxide, or a laminated film thereof.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-333163 for which it applied on March 36, 2008, and takes in those the indications of all here.

Claims (7)

A first electrode and a resistance change layer formed on the first electrode;
At least a second electrode formed on the variable resistance layer,
The variable resistance layer has a first layer made of an oxide of a transition metal other than tantalum and a second layer made of amorphous tantalum oxide,
The first layer is formed in contact with the first electrode ;
The variable resistance element according to claim 1, wherein silicon is added to the second layer . The resistance change element according to claim 1,
The resistance change element includes a third layer sandwiched between the first layer and the second layer and made of titanium oxide. The resistance change element according to claim 2,
The resistance change element, wherein the third layer is formed thinner than the second layer. The resistance change element according to claim 1,
The variable resistance element, wherein the first layer is formed thinner than the second layer. The resistance change element according to claim 1,
The variable resistance element, wherein the second layer is made of tantalum oxide having a stoichiometric composition. The resistance change element according to claim 1,
The variable resistance element according to claim 1, wherein the first layer is made of nickel oxide. The resistance change element according to claim 1,
The variable resistance element according to claim 1, wherein the first layer is made of zirconium oxide.

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