JP2007134603A - Method for manufacturing nonvolatile semiconductor memory device comprising variable resistive element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a nonvolatile semiconductor memory device capable of suppressing variations in resistance value according to the difference of a PCMO crystallinity of a variable resistive element and completely securing a circuit operational margin. <P>SOLUTION: The method for manufacturing the semiconductor memory device with the variable resistive element for storing data formed between an upper electrode and a lower electrode comprises the steps of sputtering an electrically conductive metallic oxide in an atmosphere including no oxygen, and forming the variable resistive element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device in which a variable resistor for storing data is formed between an upper electrode and a lower electrode.

  In recent years, next-generation non-volatile random access memory (NVRAM) capable of high-speed operation in place of flash memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), OUM (Ovonic Unified Memory), etc. A structure has been proposed, and intense development competition has been conducted from the viewpoint of high performance, high reliability, low cost, and process consistency. However, each of these current memory devices has advantages and disadvantages, and it is still far from the ideal realization of a “universal memory” having the advantages of SRAM, DRAM, and flash memory.

  In contrast to these existing technologies, a method of reversibly changing electrical resistance by applying a voltage pulse to a perovskite material known for its giant magnetoresistive effect is disclosed by Shangquing Liu and Alex Ignatiev of Houston University in the United States. (For example, refer to Patent Document 1 and Non-Patent Document 1). This is an extremely epoch-making phenomenon in which a perovskite material known for its supergiant magnetoresistance effect is used, and a resistance change of several orders of magnitude appears even at room temperature without applying a magnetic field.

Unlike a MRAM, a resistive non-volatile memory RRAM using a variable resistance element utilizing this phenomenon (registered trademark of Sharp Corporation, Resistance Random Access Memory) does not require a magnetic field at all, and therefore has extremely low power consumption and miniaturization. High integration is also easy, and since the dynamic range of resistance change is much wider than that of MRAM, it has an excellent feature that multi-value storage is possible. The basic structure of an actual device is very simple, and is a structure in which a lower electrode material, a perovskite oxide, and an upper electrode material are stacked in this order in the direction perpendicular to the substrate. In the element structure exemplified in Patent Document 1, the lower electrode material is yttrium / barium / copper oxide YBa ₂ Cu ₃ O ₇ (YBCO) deposited on a lanthanum / aluminum oxide LaAlO ₃ (LAO) single crystal substrate. ) Film, a perovskite oxide is a crystalline praseodymium / calcium / manganese oxide Pr _1-x Ca _x MnO ₃ (PCMO) film, and the upper electrode material is an Ag film deposited by sputtering. It has been reported that the operation of this memory element can reversibly change the resistance by applying a positive or negative voltage pulse applied between the upper and lower electrodes of 51 volts. It means that a novel nonvolatile memory device is possible by reading the resistance value in this reversible resistance change operation (hereinafter referred to as “switching operation” as appropriate).

  As a semiconductor memory device having a device structure using such a variable resistance element, a semiconductor memory device having a cross-point structure has been proposed (for example, see Patent Document 2).

  In general, a semiconductor memory device such as a DRAM, a NOR flash memory, or an FeRAM has one memory cell including an element portion for storing memory and a selection transistor for selecting the memory element. . On the other hand, a memory cell having a cross-point structure is formed by eliminating this selection transistor and arranging only a storage material body for storing memory data at the intersection (cross point) between a bit line and a word line. In this memory cell configuration of the cross-point structure, the accumulated data at the intersection of the selected bit line and word line is directly read without using the selection transistor, so that the selected bit line or selected word connected to the selected memory cell Although the parasitic current flowing through the non-selected memory cell connected to the line is superimposed on the read current flowing through the selected memory cell, there are problems such as a delay in operation speed and an increase in current consumption. Attention has been paid to the fact that the capacity can be increased by reducing the memory cell area. The simplest method for producing a crosspoint structure will be described below.

  FIG. 1 is a plan layout diagram of a memory cell having a cross-point structure. A region R1 for defining the wiring pattern of the lower electrode wiring B and a region R2 for defining the wiring pattern of the upper electrode wiring T are shown. Here, one of the upper electrode wiring T and the lower electrode wiring B is a word line, and the other is a bit line. 6 and 7 show the conventional manufacturing method in the order of steps, and are a vertical sectional view along XX 'in FIG. 1 and a vertical sectional view along YY' in FIG. Respectively.

  First, as shown in FIG. 6A, after an interlayer insulating film 12 under a memory cell is formed on a silicon semiconductor substrate 11 on which a transistor circuit or the like (not shown) is formed, it is generated due to the presence of the transistor circuit or the like. In order to alleviate the level difference, the surface is flattened by a so-called CMP method (Chemical Mechanical Polishing Method).

  Subsequently, as shown in FIG. 6B, after depositing an electrode material film 13 to be the lower electrode wiring B on the entire surface, a resist R1 patterned in a stripe shape (line & space) by a photolithography technique is formed. The lower electrode wiring B is formed by etching the electrode material film 13 as a mask.

  Subsequently, after removing the resist R1, as shown in FIG. 6C, an insulating film 14 having a thickness sufficient to fill a region between adjacent lower electrode wirings B is deposited on the entire surface.

  Subsequently, as shown in FIG. 6D, the insulating film 14 is polished to the surface level of the lower electrode wiring B by the CMP method. As a result, the lower electrode wiring B is filled with the insulating film 14. Since the surface of the buried insulating film 14 and the surface of the lower electrode wiring B have substantially the same height, a structure in which the entire surface is substantially smooth is formed. The purpose of the polishing step is to form a variable resistor film to be subsequently formed on the flat surface as much as possible. This is because in the subsequent etching of the variable resistor film, there is no etching selectivity between the variable resistor film and the lower electrode film, so the variable resistor film is formed on the step of the lower electrode. Due to difficulties.

  Subsequently, as shown in FIG. 7E, a metal oxide film 15 to be a variable resistor is formed by sputtering on the entire surface. This sputtering is performed in an atmosphere containing oxygen. Subsequently, as shown in FIG. 7F, an electrode material film 16 to be the upper electrode wiring T is formed on the entire surface.

  Subsequently, the upper electrode wiring T is formed by etching the electrode material film 16 using the resist R2 patterned in a stripe shape (line & space) by a photolithography technique as a mask. Further, as shown in FIG. 7G, the variable resistor film 15 remaining between the upper electrode wirings T is removed by etching.

  Subsequently, after removing the resist R2, an interlayer insulating film 17 under the metal wiring is deposited on the entire surface as shown in FIG. 7 (h). Thereafter, contacts (contact forming portions are not shown) to the lower electrode wiring B, the upper electrode wiring T, transistor circuits other than the memory cells, etc. are formed, and metal wiring (not shown) is performed.

  The PCMO film formation (see FIG. 7E), which is the variable resistor of the cross-point device described above, is formed by sputtering using a sintered PCMO target. An appropriate amount of oxygen gas is introduced into the Ar gas, which is a sputtering gas, for the purpose of supplementing the deficient oxygen. It is known that the PCMO film thus formed is almost amorphous. Amorphous PCMO films usually have extremely high resistance, so they are not suitable for device operation, and it is necessary to crystallize them in a heat treatment step during the process to lower them to a desired resistance level.

US Pat. No. 6,204,139 Liu, S .; Q. In addition, “Electrical-pulse-induced reversible resistance change effect in magnetosensitive films”, Applied Physics Letter, Vol. 76, pp. 2749-2751, 2000

  However, the PCMO film thus crystallized and reduced in resistance is strongly influenced by the state of the underlying electrode surface or insulating film surface. As a result, the PCMO film that is a variable resistor has a different crystallinity of the PCMO film and causes extremely large variations in resistance values of the individual variable resistors. For this reason, there is a problem that a margin necessary for circuit operation is reduced, leading to an increase in instability and an increase in defect rate.

  The present invention has been made in view of the above problems, and an object thereof is a nonvolatile semiconductor memory capable of suppressing a resistance value variation due to a difference in PCMO crystallinity of a variable resistor and ensuring a sufficient circuit operation margin. The object is to provide a method of manufacturing the apparatus.

  In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a variable resistance element formed by forming a variable resistor for storing data between an upper electrode and a lower electrode. A method for manufacturing a nonvolatile semiconductor memory device, characterized in that a variable resistor forming step of forming a metal resistor by sputtering a metal oxide in an atmosphere not containing oxygen is performed. .

  In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a plurality of upper electrode wires extending in the same direction and a plurality of lower electrodes extending in a direction perpendicular to the extending direction of the upper electrode wires. Nonvolatile including a memory cell array having a cross-point structure in which variable resistance elements formed by forming variable resistors for storing data between the upper electrode wiring and the lower electrode wiring are arranged in a matrix A method for manufacturing a volatile semiconductor memory device, comprising: performing a variable resistor formation step of sputtering a metal oxide on the plurality of lower electrode wirings in an oxygen-free atmosphere to form the variable resistor. This is the second feature.

  A method for manufacturing a nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the sputtering uses any one of Ar, He, Ne, Kr, and Xe as a sputtering gas. To do.

  The manufacturing method of the nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the film forming temperature range of the sputtering is 500 ° C. to 800 ° C.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics, the metal oxide has the general formula Pr _1-X Ca _X [Mn _1-Z M _Z ] O ₃ (where 0 ≦ x The fifth characteristic is that the oxide is a system represented by ≦ 1, 0 ≦ z <1).

  In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention having the above characteristics, M in the general formula includes any one of Ta, Ti, Cu, Cr, Co, Fe, Ni, and Ga. The sixth feature.

  The method for manufacturing a nonvolatile semiconductor memory device according to the first to fourth features of the present invention has the seventh feature that the metal oxide is an oxide of Ti or an oxide of Ni.

  According to the method for manufacturing the nonvolatile semiconductor memory device having the above characteristics, the variation in the resistance value of the variable resistance element can be reduced. As a result, when a nonvolatile semiconductor memory device including the variable resistance element is configured, the circuit operation margin is increased, stable memory operation is possible, and the defect rate can be further reduced.

  Embodiments of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention (hereinafter referred to as “method of the present invention” where appropriate) will be described below with reference to the drawings.

FIG. 1 is a plan layout view for forming a memory cell array in the method of the present invention, showing a region R1 for defining the wiring pattern of the lower electrode wiring B and a region R2 for defining the wiring pattern of the upper electrode wiring T, respectively. ing. The planar layout diagram is the same as the planar layout diagram of a conventional memory cell array having a cross-point structure, and is located at the intersection (cross-point portion) between the upper electrode wiring T and the lower electrode wiring B between the upper electrode and the lower electrode. Variable resistor elements formed by variable resistors for storing data are arranged in a matrix. In the following embodiments, a memory cell and a memory having a cross-point structure using a CMR material (for example, PCMO: Pr _0.7 Ca _0.3 MnO ₃ ) thin film having a giant magnetoresistance effect as a variable resistor of the memory cell. A specific manufacturing method of the memory cell array configuration will be described by taking as an example the RRAM that configures the cell array.

<First Embodiment>
One embodiment of the method of the present invention will be described with reference to FIGS. Here, FIG.2 and FIG.3 has shown each process of this invention method in this embodiment in order. 2 and 3 respectively show a vertical cross-sectional view along XX ′ in FIG. 1 and a vertical cross-sectional view along YY ′ in FIG. In the present invention, “vertical” means a case perpendicular to the surface of the semiconductor substrate 11 unless otherwise specified.

  First, as in the conventional manufacturing method, a BPSG film 12 having a thickness of 1300 nm is formed as an interlayer insulating film under a memory cell on a silicon semiconductor substrate 11 on which a transistor circuit or the like (not shown) is formed, and a CMP method. To 600 nm to flatten the surface. Subsequently, as shown in FIG. 2A, a Pt film 13 (corresponding to the first electrode film) to be the lower electrode wiring B is sputtered on the entire surface. In this embodiment, the Pt film 13 is deposited so that the film thickness becomes 200 nm.

  Subsequently, as shown in FIG. 2B, the lower electrode wiring B is formed by etching the Pt film 13 using the resist R1 patterned in a stripe shape (line & space) by a photolithography technique as a mask. To do. In this embodiment, etching was performed using a striped resist pattern having a line width of 0.3 μm and a space width of 0.3 μm.

  Subsequently, after removing the resist R1, as shown in FIG. 2C, a silicon oxide film 14 as an insulating film is deposited on the entire surface. The film thickness of the silicon oxide film 14 is set to a film thickness sufficient to fill the space between the lower electrode wirings B. In the present embodiment, the silicon oxide film 14 is deposited so as to have a film thickness of 400 nm.

  Subsequently, a polishing process is performed to polish the silicon oxide film 14 to the surface level of the lower electrode wiring B by the CMP method. The above is the lower electrode wiring forming process for forming the lower electrode wiring B.

  As a result of the polishing process, as shown in FIG. 2D, the space between the lower electrode wirings B is filled with the silicon oxide film 14, and the surface of the embedded silicon oxide film 14 and the surface of the lower electrode wiring B are made substantially the same height. By smoothing, a planar structure having a substantially uniform surface is formed.

Subsequently, as shown in FIG. 3E, the variable resistor 18 made of PCMO (Pr _0.7 Ca _0.3 MnO ₃ ) is formed on the surface of the lower electrode wiring B and the silicon oxide film 14 with a film thickness of 100 nm. Sputtering is performed so that The sputtering conditions are, for example, an Ar gas flow rate of 210 sccm, a pressure of 20 mTorr, and a substrate temperature of 670 ° C. The gas introduced into the reaction chamber is only Ar, and the PCMO film formed in an oxygen-free atmosphere becomes a crystallized film. As the variable resistor 18, it is possible to use to form a TiO ₂ film and NiO film oxide such as TiO ₂ and NiO also TiO ₂ target and NiO targets under the same conditions as the sputtering conditions. Note that the PCMO film 18 is an oxide of a system represented by Pr _1-X Ca _X [Mn _1-Z M _Z ] O ₃ (where 0 ≦ x ≦ 1, 0 ≦ z <1). M preferably contains any one of Ta, Ti, Cu, Cr, Co, Fe, Ni, and Ga.

  Subsequently, as shown in FIG. 3F, a Pt film 16 to be the upper electrode T is formed on the PCMO film 18 by a sputtering method. In the present embodiment, the thickness of the Pt film 16 is 100 nm.

  Thereafter, a resist R2 as shown in FIG. 3G is formed in a region to be the upper electrode T on the Pt film 16 based on the upper electrode pattern by a photolithography technique. Then, using this resist R2 as a mask, the Pt film 16 and the PCMO film 18 are simultaneously etched by a dry etching method, and then the resist is removed to form the upper electrode T (Pt film 16) and the variable as shown in FIG. A resistor (PCMO film 18) is formed.

Further, thereafter, as shown in FIG. 3H, a SiO ₂ film 17 is deposited by 400 nm by the CVD method. Then, contact holes and metal wiring steps necessary for circuit operation are performed to complete the circuit (not shown).

  Note that the sputtering conditions for the PCMO film 18 described above are not limited to this, it is sufficient that stable sputtering is performed and the PCMO film 18 is crystallized, and the sputtering gas includes a rare gas element other than Ar, for example, He. , Ne, Kr, and Xe may be used. The substrate temperature is preferably in the range of 500 ° C. to 800 ° C. at which the PCMO film is stably crystallized.

  FIG. 4 shows the resistance value distribution of the nonvolatile semiconductor memory device formed by the method of the present invention and the prior art, and FIG. 4 shows the in-chip variation of the resistance value of the nonvolatile semiconductor memory device formed by the method of the present invention and the prior art. As shown in FIG.

  FIG. 4 shows the resistance distribution of the PCMO film formed on the semiconductor substrate by the method of the present invention and the prior art. Note that the sputtering film formation temperature is 670 ° C. in all cases. As shown in FIG. 4, under the sputtering conditions using Ar gas in the above embodiment, the resistance value distribution was measured, and as a result, the resistance value was 20 to 60 KΩ, and an appropriate resistance value was obtained as a variable resistor. Moreover, under the sputtering conditions in an oxygen atmosphere according to the prior art, 1 to 10 KΩ was obtained as a result of measuring the distribution of resistance values. That is, in the case of the conventional method, the distribution of the resistance value spreads over one digit, but in the case of the present invention, the distribution is narrowed and the variation is greatly improved. Therefore, it can be said that the variation in resistance value distribution was improved under the sputtering conditions according to the method of the present invention.

  Next, FIG. 5 shows the variation in the resistance value of the PCMO film formed by the method of the present invention and the prior art in the wafer. Here, for the variation in the wafer, 3σ of the standard deviation of the resistance value in the wafer and the average value of the resistance values are used, and the average value of 3σ / resistance value is shown as the variation. As shown in FIG. 5, when the resistance value distribution is compared between the sputtering condition using Ar gas according to the method of the present invention and the sputtering condition in the conventional oxygen atmosphere, the variation in the chip in the case of the method of the present invention is 8˜. While it is about 40%, it is about 40 to 200% in the conventional method. That is, the variation in the chip is also reduced to about 1/10 in the case of the method of the present invention compared to the prior art. By using the sputtering conditions in the oxygen-free atmosphere according to the method of the present invention, the resistance value is reduced. It can be said that a significant reduction in the variation was achieved.

As described above, the variation in resistance value is greatly reduced because the crystallinity of the PCMO film is very high. This is because the crystallization temperature is lowered because oxygen, which is an oxidizing gas, is not contained during sputtering and sputtering is performed using only Ar gas. Similarly, sputtering of TiO ₂ and NiO with only Ar gas lowers the crystallization temperature, so that a film with a high degree of crystallinity can be formed, and variations in resistance can be reduced. Also for TiO ₂ and NiO, a rare gas element other than Ar, such as He, Ne, Kr, or Xe, may be used as the sputtering gas. Therefore, according to the method of the present invention, the variation is extremely small, and as a result, it is possible to realize a good non-volatile semiconductor memory device that can ensure a sufficient operation margin.

Planar layout of memory cell array with cross-point structure Sectional drawing which shows each process in 1st Embodiment of the manufacturing method of the semiconductor memory device concerning this invention. Sectional drawing which shows each process in 1st Embodiment of the manufacturing method of the semiconductor memory device concerning this invention. The graph which shows resistance value distribution of the semiconductor memory device which concerns on this invention, and the semiconductor memory device which concerns on a prior art The graph which shows the dispersion | variation in resistance value of the semiconductor memory device which concerns on this invention, and the semiconductor memory device which concerns on a prior art Process sectional drawing which shows each process of the manufacturing method of the semiconductor memory device based on a prior art Process sectional drawing which shows each process of the manufacturing method of the semiconductor memory device based on a prior art

Explanation of symbols

11: Semiconductor substrate (silicon substrate)
12: Interlayer insulating film (BPSG film)
13: Pt film 14: Silicon oxide film 15: Variable resistor 16: Pt film 17: Interlayer insulating film 18: Variable resistor B: Lower electrode wiring T: Upper electrode wiring R1: Resist R2: Resist

Claims (7)

A method for manufacturing a nonvolatile semiconductor memory device comprising a variable resistance element formed by forming a variable resistor for storing data between an upper electrode and a lower electrode,
A method of manufacturing a nonvolatile semiconductor memory device, comprising performing a variable resistor forming step of sputtering a metal oxide in an atmosphere not containing oxygen to form the variable resistor. A plurality of upper electrode wirings extending in the same direction and a plurality of lower electrode wirings extending in a direction orthogonal to the extending direction of the upper electrode wiring, and for storing data between the upper electrode wiring and the lower electrode wiring A method for manufacturing a nonvolatile semiconductor memory device including a memory cell array having a cross-point structure in which variable resistance elements formed by forming the variable resistors are arranged in a matrix,
A non-volatile semiconductor memory device comprising: a step of forming a variable resistor by sputtering a metal oxide on the plurality of lower electrode wirings in an atmosphere not containing oxygen; Production method.   The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the sputtering uses any one of Ar, He, Ne, Kr, and Xe as a sputtering gas.   4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein a film forming temperature range of the sputtering is 500 ° C. to 800 ° C. 5. Said metal oxide has the general formula _{Pr 1-X Ca X [Mn} 1-Z M Z] O 3 ( where, 0 ≦ x ≦ 1,0 ≦ z <1) an oxide of system represented by The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein:   6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein M in the general formula includes any one of Ta, Ti, Cu, Cr, Co, Fe, Ni, and Ga. .   5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the metal oxide is an oxide of Ti or an oxide of Ni.